JP3202491B2 - Direct image forming equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct image forming apparatus for forming an image corresponding to an image signal on a recording medium by restricting the movement of toner through a gate which is selectively opened and closed.

[0002]

2. Description of the Related Art In an image forming apparatus using an electrophotographic method,
A photoreceptor for forming an electrostatic latent image is required, and there is a problem that the apparatus becomes large. Therefore, Tokuhyo Hei 1-5032
As disclosed in JP-A-21, a method and apparatus for opening and closing a passage through which pigment particles pass by an electric field in an electrode matrix so as to form an image of the pigment particles on a recording medium are disclosed. In this image forming apparatus, as shown in FIG. 41, two sets of electrode layers 104 and
105 are arranged vertically between the conveyor roller 101 and the paper 103 in a state where the wires are orthogonal to each other, and a plate electrode 106 is disposed below the paper 103. The conveyor roller 101 magnetically adsorbs the magnetic pigment particles 102 on the peripheral surface, and forms the electrode layers 104 and 10.
By changing the voltage applied to the wires constituting the wire 5, an electrostatic field is selectively formed between the conveyor roller 101 and the plate electrode 106. This electrostatic field causes the electrode layer 104 to move from the conveyor roller 101 to the plate electrode 106 side.
By moving the magnetic pigment particles 102 through 105, the pigment particles 102 are adsorbed on the paper 103 to form an image.

Japanese Unexamined Patent Publication No. Hei 4-21970 discloses a structure of an electrode portion for selectively passing pigment particles in the direct image forming apparatus as shown in FIG.
The passage 213 is circularly surrounded by the electrodes 205 so that each electrode 205 constituting the specific passage 213 does not contact another electrode 205. By configuring the electrode portion in this manner, the electrode 205 is prevented from cross-linking, and only the passage 213 through which the pigment particles are to be passed is opened for consistency with the image information, and accurate image formation is performed. So that you can do it.

[0004]

However, in the conventional direct image forming apparatus, it is necessary to generate an opening / closing signal for opening / closing the gate based on an image signal input from an external device, and this image signal is converted into opening / closing data. There was no one with an inexpensive and high-speed configuration for conversion. For this reason,
When the conversion processing of the image signal is performed by an analog circuit, the circuit becomes large.
However, there is a problem that the processing load increases and the processing time becomes longer.

An object of the present invention is to provide a direct image forming apparatus capable of speeding up a process of converting an image signal into opening / closing data and eliminating an increase in hardware and an increase in processing time. It is in.

[0006]

According to a first aspect of the present invention, there is provided a direct image forming method for selectively opening and closing a plurality of gates arranged in a matrix and forming an image on a recording medium by toner passing through the gates. in the device, attached to the odd-numbered rows
Odd memory and even row for storing all image data
An even memory for storing all image data, and an odd memory and an even memo for each row of image data input from an external device.
An image data writing means for sequentially writing the respective Li, odd
Image data reading means for reading image data from a memory other than the memory in which the image data is written by the image data writing means of the number memory and the even memory; and image data read by the image data reading means. a signal conversion means for generating a closing data of the gate, the provided, the gate
Has a certain odd pixel gap between each row
The configuration is characterized in that

[0007]

[0008]

[0009]

According to the first aspect of the invention, the image data input from the external device is an image data for an odd row.
Data and odd-numbered image data
The data is sequentially written to each of the memory and the even-numbered memory for each row. At this time, one of the odd memory and even memory
While image data is being written to the other memory, the other
Image data is read out already written from memory, closing data of the gate is created on the basis of the read image data. Therefore, odd or even rows
Image data stored in odd or even memory
The image data for even or odd rows
Data from even or odd memory.
Can Ru. For this reason, the time from input of image data to creation of gate opening / closing data is shorter than in the case where image data for all pixels is temporarily stored, image data is sequentially read out, and then converted into gate opening / closing data. Is shortened. The gate is located between the rows for a certain number of odd pixels.
They are arranged with gaps. Therefore, each row of the gate is
Alternately supports odd or even rows of image data
In one image data reading process.
Read image data from both odd and even memory
No need to read, repeat odd and even memory
Alternately used to write and read image data
Can be done.

[0010]

[0011]

FIG. 1 is a schematic diagram showing the configuration of a direct image forming apparatus according to an embodiment of the present invention. The image forming apparatus includes a developing device 1 in the center, a transfer belt 2 disposed above the developing device 1, and a pressure roller 12 further above the transfer belt. A paper transport path 22 including a registration roller 19 and a paper discharge roller 25 is formed between the paper supply cassette 26 and the paper discharge tray 27 via the space between the pressure roller 12 and the transfer belt 2. The toner stored in the developing device 1 is selectively attracted to the surface of the transfer belt 2 and is transferred to a sheet passing between the transfer belt 2 and the pressure roller 12.

The developing device 1 has a stirring roller 4 and a toner carrier 5 supported therein. The stirring roller 4 is a hopper 3b
The insulative magnetic toner housed inside is stirred. The toner carrier 5 is composed of a magnet roller 5a in which N-polar magnets and S-polar magnets are alternately arranged in the circumferential direction, and a cylinder 5b which is fitted around the magnet roller 5a. The toner carrier 5 rotates in the direction of arrow A, and the amount of toner adsorbed on the surface of the toner carrier 5 is adjusted to a predetermined amount by the doctor 6.

On the upper surface of the developing device 1, a toner carrier 5
The electrode 7 is provided in a portion facing the. Developing device 1
Is a powder having a particle size of about 10 μm, which is obtained by kneading and pulverizing a resin obtained by adding 50 parts by weight of magnetite to a resin made of a styrene acrylic copolymer or the like. The toner adsorbed on the surface of the toner carrier 5 passes through the electrode 7 by a magnetic field formed between the back electrode 8 provided inside the transfer belt 2 and the toner carrier 5 and flies on the surface of the transfer belt 2. I do. The transfer belt 2 is formed endlessly with a thickness of about 20 μm using a film material mainly composed of a polyimide resin.

The transfer belt 2 is stretched between a driving roller 9 and a tension roller 11, and a fixing holder 10 is provided inside. The fixing holder 10 is provided with a ceramic heater 10a. The ceramic heater 10a is made of an aluminum ceramic substrate and a planar Mo.
It is configured by printing a system heating resistor and laminating a glass coat thereon. The ceramic heater 10a of the fixing holder 10 heats the transfer belt 2 to a predetermined temperature and melts the toner adsorbed on the surface of the transfer belt 2. A voltage having a polarity opposite to the charged polarity of the toner is applied to the back electrode 8, and the toner magnetically attracted to the surface of the toner carrier 5 is attracted toward the transfer belt 2.

FIG. 2 is a block diagram showing the configuration of the image forming apparatus. The control unit of the image forming apparatus includes an image signal array conversion circuit 29, an odd memory 30, an even memory 3,
The first and second voltage switching circuits 28a and 28b are provided. The image signal array conversion circuit 29 includes:
An image signal is serially input from an image reading device 41 which is an external device. The image signal array conversion circuit 29 converts the input image signal into an odd memory 30 or an even memory 3 for each row.
1 is stored. Further, the image signal array conversion circuit 29 reads an image signal from one of the odd memory 30 and the even memory 31 and outputs it to the first and second voltage switching circuits 28a and 28b as an open / close signal. The first and second voltage switching circuits 28a and 28b store the open / close signal input from the image signal array conversion circuit 29 in a shift register. An opening / closing signal is serially output from the image signal array conversion circuit 29, and the first and second voltage switching circuits 28a and 28b have finished storing the opening / closing signals for all the openings 7a of the electrodes 7 in the shift register. , And selectively applies a voltage to the electrode 7 according to the contents of the stored open / close signal.

FIG. 3 is a block diagram showing the configuration of the image signal array conversion circuit in detail. The image signal array conversion circuit 29 includes a read address pointer 41, a write address pointer 42, a read controller 43, a write controller 44, an interface controller 45, an address selector 46, a read / write selector 47, a data selector 48, and a driver controller 49. ing.

The read address pointer 41 generates read addresses for the odd memory 30 and the even memory 31. The write address pointer 42 generates write addresses for the odd memory 30 and the even memory 31. The read controller 43 includes the odd memory 30 and the even memory 3
Generate a read signal to 1 Light controller 44
Generates a write signal to the odd memory 30 and the even memory 31. The interface controller 45 performs control for receiving data output from an external device such as the image reading device 32.

The address selector 46 alternately switches the read address and the write address to the address of the odd memory 30 and the address of the even memory 31. The read / write selector 47 distributes a read signal and a write signal to the odd memory 30 and the even memory 31. The data selector 48 distributes the image signal input from the image reading device 32 to the odd memory 30 or the even memory 31. The driver controller 49 includes the voltage switching circuit 2
8a and 28b, and generates serial data and a transmission clock.

The data selector 48 includes the image reading device 3
2 receives an image signal SI. The interface controller 45 receives the image signal SI from the image reading device 32.
Signal SICK and reset signal RESE synchronized with
T, synchronization signal CL inside image signal array conversion circuit 29
K, a synchronization signal PAGE issued at the start of input of one page of image data from the image reading device 32, and a synchronization signal HSYNC issued for each line of image data.

The address selector 46 is connected to the odd number memory 30.
And the address signal EADR of the even memory 31 are output. Read / write selector 4
Reference numeral 7 denotes a chip select signal OCE of the odd memory 30, a chip select signal ECE of the even memory 31, a write signal OWR of the odd memory 30, a write signal EWR of the even memory 31, a read signal ORD of the odd memory 30, and a read of the even memory 31. The signal ERD is output.

The data selector 48 divides the image signal SI into image data ODATA of an odd row or image data EDATA of an even row and outputs it. The driver controller 49 outputs an open / close signal S to the first voltage switching circuit 28a.
O1, an open / close signal SO for the second voltage switching circuit 28b
2. Synchronization signal SOCK to voltage switching circuits 28a and 28b
Is output. The open / close signals SO1, SO are synchronized with this signal.
2 is output.

FIG. 4 is a diagram showing an example of an image signal input to the image signal array conversion circuit, and FIG. 5 is a diagram showing an example of an array pattern of gates in the electrodes. The image reading device 32 develops the read image data into image data, and serially outputs, for example, an image signal shown in FIG. Following the output of the reset signal and the synchronization signal PAGE, the image reading device 32 serially outputs an image signal for one row in synchronization with the synchronization signal HSYNC for each row. That is, from the image reading device 32, the (i1, j1), (i1, j2),.
Image signals are output in the order of 32). I2 shown in FIG.
Similarly, an image signal is output for the i20 line.
The electrode 7 is formed, for example, by forming circular electrodes on both sides of an insulating plate using a conductive material so as to face each other.
A gate having a diameter of about 0 μm is perforated. In the electrode 7, the gates 7a are formed in four rows, eight in each row. In the electrode 7, each of the lines X1 to X4 of the gate 7a is formed with a gap corresponding to three pixels of the image signal. Further, a gate is formed at a position shifted by one pixel of the image signal as the line X1 shifts to the line X4. The image signal array conversion circuit 29 converts the image signal SI of FIG.
Received from the i1 line in synchronization with
Store to 0. Subsequently, the i2 line is similarly received and stored in the even memory 31.

Generally, addresses of a memory are divided into a line address and a data address as shown in FIG.
Assuming that the lower two bits of the data address are the head address, the bit width of the address is determined by the arrangement pattern of the gates in the electrode 7. For example, in the gate arrangement pattern shown in FIG. 5, the bit width of the head address is
The number of gate rows (X1 to X4) in the electrode 7 is determined by a binarized value. The bit width of the data address is the total number of gates 7a in electrode 7, and Xmax
It is determined by binarizing the value obtained by × Ymax. This value can also be the product of the number of dots of one line of the image signal and the number of rows of the electrode 7 (jmax × Xmax).

The bit width of the line address is obtained by calculating the number of lines corresponding to Xmin when the maximum row width Xmax of the gate 7a in the electrode 7 is assigned to the first line of the image signal, and adding 1 to this value. It is. That is,
iXmin + 1 is the number of lines of the image signal to be stored. In this embodiment, the odd memory 30 and the even memory 31 are used.
(IYmin + 1)
The binary width of / 2 is the line address bit width. More specifically, since the head address is the number of rows of the gate 7a in the electrode 7, the head address is "4", and
Subtract 1 to include the address and get “3”. When this is binarized, it becomes "11", and the required bit number of the head address is 2 bits.

Since the data address is the total number of the gates 7a in the electrode 7, the data address is 4 × 32 = 128, and similarly, 1 is subtracted to be “127”. When this is binarized, it becomes "11111111", and the number of bits of the data address becomes 8 bits. Since the line address is the maximum number of rows of the electrode 7, the number of lines corresponding to Xmin is 13 in a state where Xmax corresponds to the first line, so that 13 + 1 = 14 from iXmin + 1 and must be stored in the memory. The number of lines that must be provided is 14 lines. Here, since two memories, the odd memory 30 and the even memory 31, are used, the number of lines to be stored in one memory is 14 ÷ 2 = 7 lines. Therefore, the bit width of the line address is binarized by subtracting 1 from “7” to be “110”, which is 3 bits.

As described above, the address of the memory in this embodiment is a 3-bit line address and an 8-bit data address as shown in FIG.
Requires a capacity corresponding to the number of addresses. As shown in FIG. 7A, the odd-numbered memory 30 stores j in the i1 line.
1, j2,..., J32 dot data is the address 0
Stored in order from 00h. As shown in FIG. 3B, the even-numbered memory 31 has j1, j2,.
, J32 dot data are stored in order from address 000h. The j3 line is stored in the odd memory 30,
The line address is incremented by one and stored sequentially from address 100h. After that, when the storing of the i14 line is repeated similarly to the i4 line and the i5 line, the address is set to the address 000h again and the image signal is stored from the i15 line.

FIG. 8 is a flowchart showing the processing procedure of the image signal array conversion circuit. Image signal array conversion circuit 2
9 is an odd memory 30 and an even memory 3 after power-on.
Initialization of each section including 1 is performed (n1), and when a reset signal is input from the image reading device 32, the apparatus waits for input of a one-page synchronization signal PAGE (n2). When the one-page synchronization signal PAGE is input, the one-line synchronization signal HSYNC is output.
After that, the image data SI input in synchronization with the synchronization signal SICK is read (n3) and sequentially stored at a predetermined address of the odd memory 30 (n4).

When the next one-line synchronization signal HSYNC is input, it is determined that the data input of the first line has been completed (n5), and the image signal of the second line (i2) is converted to the synchronization signal S.
The data is read in synchronization with ICK (n6), and is sequentially stored at a predetermined address of the even-numbered memory 31 (n7, n8). At the same time, the data stored in the odd memory 30 is read out and output to the voltage switching circuits 28a and 28b as an open / close signal (n10, n11). Voltage switching circuits 28a, 28b
Is completed, the voltage switching circuits 28a and 28b apply a voltage to the gate 7a of the electrode 7 (n12).

Thereafter, when the image signal of the odd-numbered line is input, the input image signal is stored in the odd-numbered memory 30, and the image signal stored in the even-numbered memory 31 is read out. 29b is output as an open / close signal. Voltage switching circuits 28a, 28b
Applies a voltage to the electrode 7 according to the content of the open / close signal (n
13 to n19). On the other hand, when the image signal of the even line is input, the input image signal is stored in the even memory 31, and the image signal stored in the odd memory 30 is output to the voltage switching circuits 28a and 28b. , A voltage is applied to the electrode 7 (n20 to n26). The processing of n13 to n26 is continuously performed until the input of the image signal is completed for all the lines (n27).

When it is determined that the input of the image signals of all lines from the image reading device 32 has been completed by inverting the one-page synchronization signal PAGE (n27), the data stored in the even-numbered memory 31 is read (n28). Are output to the voltage switching circuits 28a and 28b (n29). When the output of the open / close signal corresponding to the image signal for one line is completed, the voltage is applied to the electrode 7 from the voltage switching circuits 28a and 28b (n31).

As described above, in this embodiment, the image signals input line by line from the image reading device 32 are distinguished into odd lines and even lines and stored in the odd memory 30 and the even memory 31, respectively. At the same time as inputting the image signal of the second and subsequent lines, the input image signal is written to one memory, and at the same time, the image signal is read from the other memory and output to the voltage switching circuits 28a and 28b. When the image signal of the first line is input, the image signal is not stored in the even-numbered memory 31 yet, so that the image signal is read when the image signal of the second and subsequent lines is input. For this reason, as described above, 1 is added to the maximum row width when determining the line address for determining the memory capacity.

As shown in FIG. 2, first and second voltage switching circuits 28a and 28b are provided to control toner passing through a gate 7a formed on the electrode 7.
A voltage is applied to the gate 7a in each of the systems. Specifically, the odd columns (Y1, Y3,.
, Y31) is connected to the voltage switching circuit 28a, and the gates 7a of the even columns (Y2, Y4,..., Y32) are connected to the second voltage switching circuit 28b. The image signal array conversion circuit 29 includes these voltage switching circuits 28a, 2
8b, the image signal is output in parallel in synchronization with the synchronization signal, and (X1, Y1) is applied to the first voltage switching circuit 28a.
(X3, Y3), (X1, Y5), (X3, Y7),
.., (X3, Y31) in the order of (X2, Y2), (X4, Y4), (X2, Y2) in the second voltage switching circuit 28b.
Y6), (X4, Y8),..., (X4, Y32).

When the image shown in FIG. 4 is formed on the sheet conveyed in the direction of arrow A on the electrode 7 shown in FIG. 5, the uppermost position of the image forming position on the sheet is X2 after passing through the line X1 of the electrode 7. Until the line is reached, the memories 30, 31 are stored in the eight gates 7a located in the X1 line.
The image signal read from is output. In the first image forming cycle shown in FIG. 9, i of the image data shown in FIG.
Eight image signals (i1, j1) corresponding to the gate 7a of the X1 line of the electrode 7 among the image signals of one line,
(I1, j5), (i1, j9), ..., (i1, j
29) is read from the odd memory 30 and output to the first voltage switching circuit 28a. At this time, since there is no image signal corresponding to the gates 7a of the X2 to X4 lines of the electrode 7 in the odd memory 30, a signal equivalent to a white image signal that does not allow toner to pass through these gates 7a is a voltage. The signals are output to the switching circuits 28a and 28b.

Thus, in the first to fourth printing cycles, the gate 7a located on the X1 line of the electrode 7
Image signals j1, j5, j of the i1 to i4 lines corresponding to
9,..., J29 are odd memory 30 and even memory 3
1 are alternately read out and output to the voltage switching circuit 28a. 9 to 12 show image signals output to the electrodes 7 during this time and the state of printing on the paper. 3A shows the contents of an image signal output to each gate 7a of the electrode 7, and FIG. 3B shows the state of image formation on paper.

As shown in FIGS. 13 to 16, after the upper end of the image forming range of the sheet reaches the X2 line of the electrode 7, X
Until the third line is reached, the image signals corresponding to the gate 7a of the X1 line of the electrode 7 in the i5 to i8 lines of the image signal by the fifth to eighth image forming cycles, and the i1 to i4 lines Are read alternately from the odd memory 30 and the even memory 31 and output to the voltage switching circuits 28a and 28b.
Thus, an image signal is output to each gate 7a of the electrode 7 in the state shown in FIGS. 13A to 16A, and an image is formed on a sheet as shown in FIG.

As shown in FIGS. 17 to 20, the ninth to twelfth image forming cycles are performed after the upper end of the image forming range of the sheet passes through line X3 of electrode 7 and reaches line X4. As a result, i9 to i1 of the image data
An image signal corresponding to the gate 7a of the X1 line of the electrode 7 among the image signals of the two lines, an image signal corresponding to the gate 7a of the X2 line of the electrode 7 among the image signals of the i5 to i8 lines, Of the image signals on the i1 to i4 lines, the image signal corresponding to the gate 7a on the X3 line of the electrode 7 is alternately read from the odd memory 30 and the even memory 31, and output to the voltage switching circuits 28a and 28b. You. By the ninth to twelfth image forming cycles described above, X1 to X7 of the electrode 7 in the state shown in FIGS.
The gate 7a of the X3 line is selectively opened, and an image is formed on a sheet in the state shown in FIG.

Thereafter, after the uppermost portion of the image forming range of the sheet reaches the X4 line of the electrode 7, in the thirteenth to twentieth image forming cycles, the electrode signal of the i13 to i20 lines of the image data is used. The image signal corresponding to the gate 7a of the X1 line, the image signal corresponding to the gate 7a of the X2 line of the electrode 7 among the image signals of the i9 to i16 lines, and the image signal of the i5 to i12 lines An image signal corresponding to the gate 7a of the X3 line of the electrode 7 and an image signal corresponding to the gate 7a of the x4 line of the electrode 7 among the image signals of the i1 to i8 lines are an odd memory 30 and an even memory. Read from 31 alternately,
It is output to voltage switching circuits 28a and 28b. As a result, the gate 7a of the electrode 7 is selectively opened sequentially in the state shown in FIGS. 21A to 28A, and an image is formed on a sheet in the state shown in FIG.

After the rear end of the image forming area of the sheet reaches the X1 line of the electrode 7 in the twentieth image forming cycle, the second
In the image forming cycle of 1 to 24 times, X2 of the electrode 7 of the image signals of the i17 to i20 lines of the image data is
An image signal corresponding to the gate 7a of the line;
The image signal corresponding to the gate 7a of the X3 line of the electrode 7 among the image signals of the i7 to i16 lines, and the gate 7a of the x4 line of the electrode 7 among the image signals of the i9 to i12 lines
Are alternately read from the odd memory 30 and the even memory 31, and the voltage switching circuit 28
a, 28b. As a result, the gate 7a of the electrode 7 is selectively opened in the state shown in FIGS. 29A to 32A, and an image is formed on a sheet in the state shown in FIG. At this time, a signal equivalent to a white image signal is output to the gate 7a of the X1 line of the electrode 7, and a signal X1 is output.
The gates 7a of the line are all closed.

After the rear end of the image forming area of the sheet reaches the X2 line of the electrode 7 in the 24th image forming cycle, the second
In the image forming cycle of 5 to 28 times, the image signal corresponding to the gate 7a of the X3 line of the electrode 7 among the image signals of the i17 to i02 lines of the image data, and i13 to
The image signal corresponding to the gate 7a of the X4 line of the electrode 7 among the image signals of the i16 line is the odd number memory 30.
And from the even number memory 31 alternately and output to the voltage switching circuits 28a and 28b. As a result, FIG.
36A, the gates 7a of the electrodes 7 are selectively opened, and an image is formed on a sheet as shown in FIG. At this time, a signal equivalent to a white image signal is output to the gate 7a of the X1 line and the X2 line of the electrode 7, and the gate electrodes of the X1 and X2 lines are all closed.

After the trailing end of the image forming range of the sheet reaches the X3 line of the electrode 7 in the 28th image forming cycle, the i17 to i20 lines of the image data are obtained in the 29th to 32nd image forming cycles. X4 of electrode 7 in the image signal
The image signal corresponding to the gate 7a of the line is read from the even memory 31 and output to the voltage switching circuit 28b. At this time, the gate 7a of the X1 to X3 line of the electrode 7
Outputs a signal equivalent to a white image signal.
The gate electrodes of the X3 line are all closed. As a result, the gate 7a of the electrode 7 is selectively opened in the state shown in FIGS. 37A to 40A, and an image is formed on a sheet in the state shown in FIG.

The first image forming cycle is executed by the processes of n9 to n12 shown in FIG. 8, and the second to twentieth image forming cycles are executed during the processes of n13 to n27. The 21st to 32nd image forming cycles are executed by the processes of n28 to n32. Even when the image data corresponding to the gates 7a of the plurality of lines of the electrode 7 is read in each of the fifth to 31st image forming cycles, each line of the gate 7a of the electrode 7 is equivalent to three pixels in the image data. The image data can be read only from either the odd memory 30 or the even memory 31 in each image forming cycle.

For example, in the thirteenth image forming cycle shown in FIG. 21, the image signal to be output to each of the gates 7a of the X1 to X4 lines of the electrode 7 corresponds to the image data i13, i9, i5, i1 line. These are image signals, all of which are data stored in the odd memory 30.
Similarly, in the fourteenth image forming cycle shown in FIG. 22, the image signal to be output to each of the gates 7a of the X1 to X4 lines of the electrode 7 is i14 of the image data,
These are image signals of the i10, i6, and i2 lines, all of which are data stored in the even-numbered memory 31.

As described above, since each image forming cycle is performed based on the image signal alternately read out from either the odd memory 30 or the even memory 31, each image forming cycle is performed based on the even memory 31 or the odd memory 30. And a signal conversion process for setting a voltage to be applied to each gate 7a of the electrode 7 in accordance with an image signal input from an external device. Can be performed at high speed. This is not limited to the case where the gates 7a are arranged in four rows as in the present embodiment.

It is to be noted that the image signal for each pixel is composed of a plurality of bits, and by changing the voltage value of the voltage applied to the gate or the application time in accordance with the weight of the bit for each pixel, an image having gradation can be obtained. Can be formed.

Further, the above-mentioned image signal conversion method is described as Y, M,
A color image can also be formed by repeating a plurality of times corresponding to a plurality of image signals such as C.

[0046]

According to the first aspect of the present invention, the odd number
Simultaneous writing of odd-numbered rows of image data to memory
Reads image data for even rows from even memory
And even lines for even memory
During the execution of the image data writing process,
There is an advantage that odd-numbered rows of image data can be read from the memory, and the time required for image data writing and reading can be reduced. Also, multiple rows of gates
Are arranged with a gap of a certain odd number of pixels.
Therefore, odd-numbered rows of image data are set for one row of gates.
In the case of setting the gates of other rows,
Is set, and similarly, one line
When setting the image data of the even line for the gate of
Sets image data of even-numbered rows for gates of other rows
This means that the odd line image data and the even line image data
Data must be set at the same time
Of odd-numbered image data or even-numbered image data
Either read alternately from odd or even memory
Gates in a matrix with an arbitrary number of rows.
Even if it is formed, signal conversion processing can be performed at high speed.
There are advantages.

[0047]

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a configuration of a direct image forming apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of the direct image forming apparatus.

FIG. 3 is a diagram illustrating details of an image signal array conversion circuit that forms a part of a control unit of the direct image forming apparatus.

FIG. 4 is a diagram illustrating an example of image data input from an image reading device to an image signal array conversion circuit.

FIG. 5 is a view showing an arrangement pattern of electrodes used in the direct image forming apparatus.

FIG. 6 is a diagram showing addresses of a memory constituting a control unit of the direct image forming apparatus.

FIG. 7 is a memory map showing storage contents of the memory.

FIG. 8 is a flowchart showing a processing procedure of the image signal array conversion circuit.

9 to 40 are views showing an open / closed state of electrodes and an image forming state in the direct image forming apparatus.

FIG. 41 is a diagram showing a configuration of a main part of a conventional direct image forming apparatus.

FIG. 42 is a view showing an arrangement state of gates in a conventional direct image forming apparatus.

[Explanation of symbols]

 7-electrode 7a-gate 28a, 28b-voltage switching circuit 29-image signal array conversion circuit 30-odd memory 31-even memory 32-image reading device

Claims (1)

(57) [Claims] In a direct image forming apparatus for selectively opening and closing a plurality of gates arranged in a matrix and forming an image on a recording medium with toner passing through the gates, an odd number for storing image data for an odd number of rows. Memory and
An even memory for storing image data for even rows ,
Odd memory for image data input from external device
And even and sequentially written image data writing means in each of the memory, the image reading image data from the memory other than <br/> outside of the memory where the image data is written by the image data writing means of the odd memory and even memory Data reading means, and signal conversion means for creating gate opening / closing data from the image data read by the image data reading means , wherein the gate provides a gap of a certain odd number of pixels between rows.
A direct image forming apparatus characterized by comprising a matrix .