JP3192845B2 - Input register circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discrete cosine transform (CDC) used for, for example, video conferencing systems and videophones for compressing and encoding image data in digital image processing.
Hereinafter, DCT) and inverse transform (Inverse Discrete C)
Osine Transform, hereinafter, to an input register circuit that is provided to the IDCT hereinafter) circuit or the like.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one described in the following literature. Reference: JP-A-4-17464 FIG. 2 shows a conventional DCT / IDCT described in the above-mentioned reference.
It is a configuration diagram schematically illustrating an example of a device. This DCT / I
The DCT device has a first-dimension DCT / IDCT operation unit 10 that performs a first-dimension DCT operation with a forward transformation instruction F and performs a first-dimension IDCT operation with an inverse transformation instruction I. The first-dimensional DCT / IDCT operation unit 10 is connected to an intermediate random access memory (Random Access Memory, hereinafter referred to as RAM) 20. The intermediate RAM 20 is a circuit that stores a calculation result of the first-dimensional DCT / IDCT calculation unit 10. Further, the intermediate RAM 20 stores the second dimension DCT /
It is connected to the IDCT operation unit 30. 2D DCT
The / IDCT operation unit 30 outputs the second DC
A circuit that performs a T operation and performs a second-dimensional IDCT operation in response to an inverse conversion command I.

Next, the operation of the DCT / IDCT apparatus will be described. The first-dimension DCT / IDCT operation unit 10 receives the row direction input signal IN of the image block, performs the first-dimension DCT operation with the forward conversion instruction F, and performs the first-dimension IDCT operation with the inverse conversion instruction I. In a videophone, image compression is performed by a forward conversion command F at the time of transmission, and the original image before conversion is returned by an inverse conversion command I at the time of reception from the other party. Intermediate R
The AM 20 stores the operation result of the operation unit 10. The second-dimension DCT / IDCT operation unit 30 applies a forward conversion command F to the second-dimension DCT for the column-direction data stored in the RAM 20.
A T operation is performed, a second-dimensional IDCT operation is performed by the inverse conversion command I, and an operation result S30 is output. Figure 3 is a configuration diagram schematically illustrating a configuration example of a first dimension DCT / IDCT arithmetic unit 10 of FIG. Second dimension DCT / IDCT operation unit 30
Have basically the same configuration. The operation unit 10 includes an input register circuit 11 for sequentially inputting and holding an input signal IN.
It has. The input register circuit 11 is connected to a parallel / serial (hereinafter referred to as P / S) converter 12. The P / S converter 12 receives the output signal S11 of the input register circuit 11 and receives the least significant bit (LS
This is a circuit for serially transferring data from B). The P / S conversion unit 12 is connected to one input side of the preprocessing unit 13 and the switching unit 14.
And connected to. The pre-processing unit 13 includes the P / S conversion unit 1
2 is a circuit for performing a butterfly operation by inputting the output signal S12 of FIG. The pre-processing unit 13 is connected to the switching unit 14. The switching unit 14 is a circuit that selects the output signal S13 of the preprocessing unit 13 or the output signal S12a of the P / S conversion unit 12 in accordance with the forward / inverse conversion command F / I. The switching unit 14
It is connected to an operation read only memory (hereinafter referred to as ROM) unit 15. Operation RO
The M unit 15 is a circuit that outputs an operation result S15 corresponding to the output signal of the switching unit 14. Calculating ROM unit 15 is connected to the one input side of the post-processing unit 16 and the switching unit 17. The switching unit 17 outputs the output signal S15a of the operation ROM unit 15 or the post-processing unit 16 in response to the forward / inverse conversion command F / I.
Is a circuit for selecting the output signal S16. Switching unit 17
Are connected to an accumulator 18. The accumulator 18 is a circuit that receives and accumulates the output signal S17 of the switching unit 17. The accumulator 18 is connected to a shift register 19. The shift register 19 receives and holds the output signal S18 of the accumulator 18,
The output signal S19 is an output circuit.

Next, the operation of the first-dimensional DCT / IDCT operation unit 10 will be described. The input signal IN is sequentially input to the input register circuit 11 and held. Next, the data is sequentially and serially transferred from the least significant bit (LSB) by the P / S converter 12. Further, a butterfly operation is performed by the preprocessing unit 13. This preprocessing operation is necessary only for the DCT operation, and is bypassed for the IDCT operation. The switching unit 14 selects the bypassed signal S12a and the preprocessed signal S13 in accordance with the forward / inverse conversion command F / I. The output signal S14 of the switching unit 14 is
The data is input to the operation ROM unit 15. This operation ROM unit 15
Outputs an operation result S15 corresponding to a predetermined input signal. The calculation result S15 is input to the post-processing unit 16. This post-processing operation is necessary only for IDCT, and is bypassed in the case of DCT operation. The bypassed signal S15a
And the post-processed signal S16 are selected by the switching unit 17 in accordance with the conversion mode. Output signal S1 of switching unit 17
7 is input to the accumulator 18 and accumulated. This result is input to and held in the shift register 19, and the output signal S19 is output. Switching units 14 and 17 are supplied with forward / inverse conversion command F / I, and switch input signals S13 and S12a in accordance with the mode of DCT operation and IDCT operation.
Well, switching between S15a and S16 is performed.
ing. FIG. 4 is a schematic configuration diagram showing a configuration example of the input register circuit 11 of FIG. This input register circuit 1
1 is a register group 40 composed of registers 41 to 48 and a shift register group 5 composed of shift registers 51 to 58
0 is provided. The registers 41 to 48 are cascaded so as to sequentially input the output signal of the previous stage to the next stage.
The outputs of the registers 41 to 48 are connected to the inputs of the shift registers 51 to 58, respectively. The shift registers 51 to 58 are circuits that take in the output signals S41 to S48 of the registers 41 to 48, respectively, and output the least significant two bits. The output side of the shift register 51 to 58 are connected respectively to the input side of the P / S conversion unit 12 of FIG.

FIG. 5 is a time chart showing the operation of the input register circuit of FIG. 4, and the operation of the input register circuit of FIG. 4 will be described with reference to FIG. Cycle T1-T
Eight 16-bit data INs are sequentially input to the registers 41 to 48 in eight cycles of 8, and all the registers 41 to 48 are ready for output in cycle T9. In cycle T9, output signals S41 to S48 of registers 41 to 48 are transferred to shift registers 51 to 58. In the cycles T9 to T16, since the data IN is continuously input, the above operation is repeated.
The registers 41 to 48 sequentially store the data IN.
On the other hand, in the cycle T9, the shift registers 51 to 58 in which the data is written repeat the operation of shifting the data IN to the right by two bits at a time during eight cycles of the cycles T10 to T17, and at the same time, the output signals S51 to S58 are output. and it outputs the least significant a (LSB) 2 bits in parallel.

[0006]

However, the conventional input register circuit has the following problems. From eight registers 41 to 48 to eight shift registers 51 to
Since data of 16 × 8 bits is transferred when data is transferred to the memory 58, there is a problem that instantaneous current consumption increases, noise and ripples increase, and adversely affect other circuits such as malfunction. Was. An object of the present invention is to provide an input register circuit in which the amount of data to be transferred in one cycle is reduced and the instantaneous current consumption is small, in order to solve the problem of the conventional technology that the instantaneous current consumption is large. is there.

[0007]

Means for Solving the Problems] To solve the above problems
According to a first aspect of the present invention, an input register circuit includes:
Here, the first shift register group and the second shift
A shift register group, a selection means, and a control circuit are provided.
The number of the first shift register group is n (where n is 1 or more).
First shift register), and the first information
N first shift registers selected based on
The input data is stored in any of them, and the first information is
For information that does not select any of the first shift registers
And each of the n first shift registers is
Outputs stored data sequentially in predetermined bits
It has become. The second shift register group includes n pieces of n shift registers.
A second shift register for selecting based on the second information;
Input to any of n selected second shift registers
Store the data and the second information is n second shifts
When the information does not select any of the registers, n second
Each shift register of the shift registers
Data is output sequentially in predetermined bits.
You. The selection means is configured to perform first and second selections according to selection information.
Select the output from one of the shift registers
It is means for outputting as output data. The control circuit
Controls the selection information based on the first information and the second information.
Control circuit. The second invention provides an input register circuit
The following storage means and output selection means are provided.
I have. The storage means includes a plurality of shift registers.
In each shift register, the logic level of the control signal is
When the logic level is 1, the stored data is m (however,
Where m is an integer of 1 or more)
And n (where n is an integer greater than or equal to 1 and greater than or equal to m)
Each of the input data consisting of bits should be stored
The m bits at the bit position are sequentially stored, and the logic level of the control signal is stored.
A second logic level different from the first logic level
Sometimes, the stored data is output every n bits.
First, the first shift register located at the first stage stores the input data.
Other than the first shift register.
The register is n bits output from the previous shift register.
This is a configuration for storing the data of the The output selection means
When the logic level of the control signal is the first logic level,
M output from each shift register constituting the storage means
Bit data is output in parallel, and the logic level of the control signal is
When the level is at the second logic level, the shift
From the shift register located at the last stage of the
By means of outputting the output n-bit data in parallel
is there.

[0008]

According to the first aspect, as described above, the input register
The first information is stored in the first shift register.
When a shift register in a star group is selected,
Input data is stored in the shift register. Second information
Selects a shift register in the second shift register group
Input data is stored in the shift register
Is done. Here, for example, the second information is stored in the second shift register.
When selecting a shift register in the
1 information in the shift register in the first shift register group.
If the information is not selected, the first shift register group
From the shift register inside, the stored data is
Are output one by one. The first information is the first shift record.
When selecting a shift register in the
2 in the second shift register group.
Data that does not select the second shift register group
From the shift register inside, the stored data is
Are output one by one. Selection information by control circuit
By controlling, the shift in the first shift register group is controlled.
Data sequentially output from the register
From the shift registers in the second shift register group.
The data output sequentially in fixed bits is selected as appropriate.
Output. According to the second invention, the control signal is the second signal.
At the logical level of the first, the first
Shift register takes in n-bit input data,
The other shift registers except the first shift register are
Of n-bit data output from the shift register
Embed. This allows multiple input data to shift multiple times
Stored in a register. Control signal at first logic level
Then, each shift register shifts by m bits and stores
Output the stored data, and each shift register
Output data is selected by the selection means and parallel
Is output to When this control signal is at the first logic level
Indicates that each shift register has m bits at the predetermined position of the input data.
Input data sequentially, so that multiple input data
Each shift register stores a specific m bits side by side
Will be. When the control signal goes to the second logic level,
The data stored in the shift register is shifted in the subsequent stage in order.
Transferred to register. Then, by the output selection means,
N-bit data output from the last- stage shift register
Data is output in parallel.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 shows a conventional DCT / I showing a first embodiment of the present invention.
Schematic structure of an input register circuit provided in a DCT device or the like
It is a formed view. This input register circuit includes a control signal S10
0a, S 1 00b, the control circuit outputs the S 1 00C 10
0, a first shift register group 110 and a second shift register group 120 for taking in input data DIN, and a first shift register group 110 and a second shift register group 12
Selectors 131 to 138 which are a plurality of selection means for selecting and outputting any one of the output signals of 0 and 0 are provided. Write enable terminals WE0, WE1 of control circuit 100
Is the write enable terminal W of the shift register group 110
E0a and the write enable terminal WE1b of the shift register group 120, respectively. The control terminal S of the control circuit 100 is commonly connected to the control input terminals of the selectors 131 to 138. The control circuit 100
The input control signal S100a receives the input data DIN
Is the shift register group 110
Indicates the first information to be selected from the
It is configured to output from the enable terminal WEO.
The control signal S100b is a signal for inputting the input data DIN.
Shift registers selected from shift register group 120
Indicating the second information to be written,
The data is output from the child WE1. Control signal S
100c designates the selection operation of the selectors 131 to 138
To be output from the control terminal S.
It is supposed to be. The shift register group 110 includes shift registers 111 to 118, and a control signal S100
a, 16 bits of input data DIN are fetched from each input terminal D for 8 cycles, and then the least significant 2 bits of each fetched data are read out. During the next eight cycles, this circuit outputs signals in parallel from each output terminal Q.
The shift register group 120 has shift registers 121 to 128 like the shift register group 110, and while the shift register group 110 performs an output operation, the control signal S1
00b, one of the shift registers 121 to 128 is sequentially selected, and 16-bit input data DIN is fetched from each input terminal D.
Reference numeral 10 denotes a circuit for outputting the least significant two bits of each input data taken in parallel from each output terminal Q during the next eight cycles after the output operation is completed. Shift register 1
Output terminals Q of 11 to 118 and 121 to 128 are connected to input terminals of selectors 131 to 138, respectively. The selectors 131 to 138 are connected to the shift register group 11
0 and output signals S111 to S111 of the shift register group 120
18, S121 to 128 are controlled by the control signal S of the control circuit 100.
100c based on the selected output signal S131.
To S138.

FIG. 6 is a schematic circuit diagram showing one configuration example of the control circuit 100 of FIG. This control circuit 100
Bit counter 101, 3-input 8-output decoder (3to
8 decoder) 102, an inverter 103,8 two-input AND gates 104 and 105 are connected as shown in FIG. 7 is a time chart showing an operation of the input register circuit of FIG. 1, FIG. 1 with reference to FIG. 7
The operation of the input register circuit of FIG. Cycle T1
In eight cycles of T8, the control circuit 100 sequentially outputs the output signal S100a from the write enable terminal WE0 to “000”.
00001 "," 00000010 "," 000001 "
00 "," 00001000 "," 0001000 "
0 "," 00100000 "," 01000000 ",
Output as "10000000". On the other hand, output signal S100 output from write enable terminal WE1
b is “00000000”. Therefore, the shift registers 111 in the shift register group 110 can be changed in one cycle.
To 118 are selected and the input data DIN
Is written, and the shift register 11 takes eight cycles.
Data is written to all of 1 to 118. All the shift registers 111 to 118 are ready to output in cycle T9. Thereafter, during the eight cycles of the cycles T9 to T16, the shift registers 111 to 118 maintain the lowest order (LS
B) Outputs 2 bits and repeats a 2-bit shift operation to the right. In this case, the selection control signal S100 c output from the terminal S of the control circuit 100 is "O", selector
Data 131 to 138, the output signal of the shift register 111 to 118 in the shift register 110 S111～S11
8 to output the output signals S131 to S138.

Meanwhile, also in the 8 cycles of the cycle T9～T16, similarly to the cycle T 1 through T 8, the shift register 121 to in the shift register group 120 in one cycle
128 is selected, the input data DIN is written, and the shift register 121 takes eight cycles.
The data is written to all of the addresses .about.128. All the shift registers 121 to 128 are ready for output in cycle T17. Thereafter, during eight cycles of cycles T17 to T24, the shift registers 121 to 128 keep the lowest order (L
SB) Output 2 bits and repeat 2 bit shift operation to the right. In this case, the selection control signal S100 c output from the terminal S of the control circuit 100 is "1", selector
Kuta 131-138, the output signal of the shift register 121-128 during a shift register group 120 S121～S1
28 to output the output signals S131 to S138. In cycles T17 to T24, cycles T1 to T8
The same operation as is repeated. That is, 16 cycles are 1
One of the operating units, in the first half of the eight cycles, with writing to the shift register 111 to 118 of the shift registers 110, and outputs the data in the shift register 121-128 of the shift registers 120 in parallel. On the other hand, in the latter eight cycles, contrary to the first half, writing to the shift registers 121 to 128 of the shift register group 120 is performed and data of the shift registers 111 to 118 of the shift register group 110 are output in parallel. As described above, in the first embodiment, the input data DIN
When entering, among the shift register groups 110 and 120 in shift register 111～118,121～128, since only the data of one of the shift register is moved, the power consumption for the other shift register is almost 0
become. Further, since 16-bit data is divided and shifted by 2 bits, instantaneous current consumption is reduced. Therefore, noise and ripple is reduced is reduced adverse effects such as malfunction of the other circuits, the power supply unit can be miniaturized, the heating value can also be reduced.

Second Embodiment FIG. 8 shows a conventional DCT / I showing a second embodiment of the present invention.
Schematic structure of an input register circuit provided in a DCT device or the like
It is a formed view. This input register circuit controls the control signal S14.
0, a control circuit 140 that outputs 0, an input dividing unit 150 that divides the input data DIN into eight bits of 2 bits , and a shift register 16 that is a storage unit that takes in the input data DIN.
1 to 168, an output dividing means 170 for dividing an output signal of the shift register 168, and selectors 181 to 188 which are output selecting means . The control of the control circuit 140
The control terminal S that outputs the signal S140 is connected to the control input terminals S / L of the shift registers 161 to 168 and the selector 18
1 to 188 are commonly connected to the control input terminals . The input division unit 150 is a circuit that divides 16-bit input data DIN into eight 2-bit data and outputs the divided data. The shift registers 161 to 168 have control input terminals S / L and
A first input terminal DA for receiving input data DIN,
A first output terminal QA for outputting the captured data,
A second input terminal DB for receiving the input data divided by the input dividing means 150, and a second output terminal for shifting and outputting the input data taken from the second input terminal DB by two bits based on a clock signal. each have a QB. Shift register 161 to 168 are cascade to output from the output terminal QA of the shift register 168 of the final stage receives the input data DIN from the preceding stage to the next stage sequentially from a preceding output terminals QA to the subsequent input terminal DA It is connected. The output terminal QA of the shift register 168 is connected to the input side of the output dividing means 170. The output dividing means 170 is a circuit that divides the output signal S168a of the output terminal QA of the shift register 168 into eight low-order 2 bits and outputs the result. The selectors 181 to 188 determine whether each output signal of the output dividing means 170 and the output terminal QB of each shift register 161 to 168 are based on the control signal S140 .
This is a circuit that selects and outputs any one of the output signals S161b to S168b output from each of them.

FIG. 9 shows shift registers 161 to 168.
Schematic configuration showing one configuration exampleDrawingIt is.ThisShift Regis
DelayTypeFlip-flop (hereinafter referred to as D-FF)
F) f1 to f16 are provided. Each D-FFf1 to f1
6 has one data input terminal D, OutForce terminalQ,One ku
Each has a lock terminal C. Each D-FFf1
f16 input terminal D based on the control signal S140
2-input for switching input to D-FFs f1 to f16
ForceSL1 to SL16 are connected respectively.
Have been. This shift registersoIs, for example, the control signal
When “0” is selected in S140,Input terminal DA
And 16-bit data da1 to da16 are simultaneously selected.
D-FFs f1 to f16 via the
Respectively. Also, this shift registerso
When “1” is selected by the control signal S140,
FIG. 2 shows 2-bit data db1 and db2 from input terminal DB.
In synchronization with a clock signal CLK not shown,
To the D-FFs f1 and f2 via the
Be included. D-FFs f1 to f16 are arranged every other
Odd-numbered D-FFs f1, f3, f5, to f1
3 each output terminalQ is, Selectors SL3, SL5, to SL
15, the next odd-numbered D-FFs f3, f5,.
It is connected to the data input terminal D of f15.
Similarly, even-numbered D-FFs f2, f4, f6, to f1
4 output terminalsQ is, Selectors SL4, SL6, to SL
16 through the next even-numbered D-FFs f4, f6,.
It is connected to the data input terminal D of f16.
FIG. 10 is a time chart showing the operation of the input register circuit of FIG.
It is a chart, this figure10While referring to FIG.
The operation of the transistor circuit will be described. 8 of cycles T1 to T8
During the cycle, the control signal S140 is in the state of "1".
The input data DIN input every cycle is shifted
Write sequentially to each input terminal DA of registers 161 to 168
I will. Output signal S168a of shift register 168
Are output via selectors 181 to 188. Rhinoceros
During eight cycles of the cycles T9 to T16, the control signal S1
40 is a state of "0", and each shift register 161-
168 shifts right by two bits per cycle
Execute At the same time, the input data DIN is input divided.
The means 150 divides the data into 8 bits of 2 bits each,
Write to each input terminal DB of the star 161 to 168
I will. After eight cycles, each shift register 161-1
68 ends the right shift operation of all the data,
Output the least significant 2 bits from each output terminal QB.
And output signals S161 to 168 of the selector 181
188. In cycles T9 to T16
Input from the input terminal DB in two 8-bit increments
The input data is stored in each of the shift registers 161 to 168.
Fills all bits, and the contents are on input data DIN
Eight pieces of specific 2-bit data of
Is equal to Therefore, the next cycle T17 to T24
, The operation of cycles T1 to T8 is repeated
In cycles T9 to T16, selectors 181 to 188
The same type of data as the data output via
It is.

As described above, in the second embodiment, as in the first embodiment, 16-bit data is divided into two bits and shifted, so that instantaneous current consumption is reduced. Also, since the number of registers used is half that of the conventional case, the power consumption is about half that of the conventional case. Therefore, noise and ripples are reduced, adverse effects such as malfunctions on other circuits are reduced, the power supply unit can be downsized, and the amount of heat generated can be reduced.
Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications. (A) The shift register groups 110 and 120 in FIG.
May be cascaded similarly to the conventional register group 40. (B) The number of shift register groups in FIG.
It can be changed according to the number of N bits. (C) The control circuit 100 of FIG. 1 may use a counter or the like. (D) The input division circuit 150 shown in FIG.
You may comprise with a gate etc. (E) The output dividing circuit 170 shown in FIG.
You may comprise with a gate etc. (F) The input register circuits of FIGS. 1 and 8 can also be used for the input section of another arithmetic processing circuit.

[0015]

As described in detail above, according to the first invention, the first and second shift registers for taking in and shifting the input data are provided, and the data is output alternately. First, instantaneous current consumption can be reduced without transferring much data at one time. Therefore, noise and ripple can be reduced, and other circuits do not have adverse effects such as malfunction. Further, the power supply unit for supplying power to the first and second shift registers can be reduced in size, and the amount of heat generated can be reduced. According to a second aspect of the present invention takes the input data, writes the data directly to a plurality of shift registers for shifting performs operation for m bit by bit shift operation of the shift register, the transfer of data between the respective shift registers Since two types of operations are provided, a reduction in instantaneous current consumption can be expected without transferring much data at one time. Therefore, noise and ripples are reduced, adverse effects such as malfunctions on other circuits are reduced, the power supply unit can be downsized, and the amount of heat generated can be reduced. In addition, the shift
Registers are halved, and the number of D-FFs used for this is reduced.
Therefore, the area for forming the input register circuit can be reduced.
You.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an input register circuit showing a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a conventional DCT / IDCT apparatus.

3 is a <br/> configuration diagram schematically one dimension DCT / IDCT circuit of FIG.

FIG. 4 is a schematic configuration diagram of a conventional input register circuit.

FIG. 5 is a time chart of FIG. 4;

6 is a configuration diagram of a schematic of a control circuit of Figure 1.

FIG. 7 is a time chart of FIG. 1;

FIG. 8 is a schematic configuration diagram of an input register circuit showing a second embodiment of the present invention.

9 is a configuration diagram of a schematic of a shift register in FIG.

FIG. 10 is a time chart of FIG.

[Explanation of symbols]

110, 120
Shift register group 111-118, 121-128, 161-168
Shift register 100,140
Control circuits 131-138, 181-188
selector

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 9/00 H03M 7/30

Claims (2)

(57) [Claims] (1) n (where n is an integer of 1 or more) first n
Having a shift register selected based on the first information.
Input to any of the n first shift registers
Data, and the first information is stored in the n first systems.
When the information does not select any of the shift registers,
Each of the first shift registers stores
A first system for sequentially outputting the stored data bit by bit
Shift register group, and n second shift registers, and based on the second information.
Any of the n second shift registers selected
Input data, and the second information is the n
When the information does not select any of the second shift registers
Each of the shift registers of the n second shift registers.
The stored data sequentially outputs the stored data bit by bit.
A second shift register group, and the first and second shift registers according to selection information.
Output from one of the
Selecting means for outputting the selected information based on the first information and the second information.
An input register circuit , comprising: a control circuit for controlling information . 2. A semiconductor device comprising : a plurality of shift registers;
The shift register has a logic level of the control signal of the first logic level.
At the level, the stored data is represented by m (where m is
(1 or more integers)
Where n (where n is an integer of 1 or more greater than m) bits
Bits to be stored in the input data consisting of
The m bits of the position are sequentially stored, and the logic level of the control signal is stored.
Is at a second logic level different from the first logic level
Output the stored data n bits at a time
In addition, the first shift register located at the first stage stores the input data.
And the other shift registers except the first shift register
The register is n bits output from the previous shift register
Storage means for storing the data of the control signal; and when the logic level of the control signal is the first logic level.
To, outputting the storage unit from the shift register to configure
M bits of data to be output in parallel.
When the logic level of the signal is the second logic level,
Located in the last stage of the shift register
N bits of data output from the shift register
An input register circuit , comprising: output selection means for outputting in parallel .