JP3189887B2 - Output circuit of solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit of a solid-state imaging device, and more particularly to an output circuit of a solid-state imaging device that outputs a plurality of voltages detected by a plurality of series of charge detection units in a time-division multiplexed manner.

[0002]

2. Description of the Related Art As an example of a conventional solid-state imaging device, red,
Three rows of photodiodes, three rows of transfer registers, three charge detection areas,
Take a charge coupled device (CCD) with two signal outputs as an example. FIG. 5 is a block diagram of an output circuit that converts charges from the CCD into a voltage and performs time division multiplexing, FIG. 6 is a timing chart of the output circuit, and FIG. 7 is a timing chart of transfer of charges of the CCD. The charge generated by the photodiode is clock φ1,
By driving φ2 as shown in FIG. 7, the data is sequentially transferred to the charge detection unit.

In FIG. 7, when T = Ta, the charge of the charge detection unit 3 is absorbed by the drain 21 by turning on the reset gate φR. When T = Tb, the reset gate φR is turned off, and the charge detection unit 3 has no charge. When T = Tc, the electric potential is changed to the Low level by the clock of φ1, so that electric charges are sent to the electric charge detection unit 3.

[0004] The detected charge is a capacitor 3a,
The voltage is converted into a voltage by 3b or 3c, and the signal is amplified and output by the source follower-type amplifiers 4a, 4b, and 4c.
FIGS. 6D, 6E, and 6F show signal waveforms during one transfer period.
The non-signal region (T = t0) and the signal region (T = t1 + t2 + t3) including a reset period and a feed-through period (a period during which signal charge is input to the charge detection unit after reset) as shown in FIG. ). Then, the changeover switches 6a, 6b, 6c, 7a, 7b,
And 7c to signals s1 (FIG. 6 (g)) and s2 (FIG. 6 (g)).
(H)), three voltages (point c-1 and point c-1) as shown in the signal waveform of FIG.
-2 and the voltage at point c-3) are output from one output terminal (point d). As described above, the signal is internally switched during the signal period of one transfer period by the internal switch 6a,
The method of outputting three color signals within one transfer period in which the signals are sequentially output in 6b, 6c, 7a, 7b, and 7c has a simpler circuit configuration than the method of outputting signals of each color from three terminals. There are benefits.

[0005]

However, the output signal (FIG. 6) generated by the output circuit of the conventional solid-state imaging device described above.
(I)) includes a non-signal period (a period indicated by T = t0) including a reset period and a feed-through period.

Therefore, in the conventional output circuit of the solid-state imaging device, when the data rate of the signal transfer is increased, the period of the signal section is short, and it is difficult to stably sample three types of color signals in the subsequent stage. was there.

According to the present invention, there is provided an output circuit of a solid-state imaging device for outputting an output signal in which three kinds of color signals are time-division multiplexed during one charge transfer period, wherein the output signal includes a reset period and a feed-through period. An object of the present invention is to provide an output circuit of a solid-state imaging device in which a signal period is reduced and a signal period is long.

[0008]

According to the present invention, there is provided an output circuit of a solid-state imaging device which outputs a plurality of voltages detected by a plurality of series of charge detection sections of the solid-state imaging device in a time-division multiplexing manner. In the circuit, based on a sample signal for sampling each of the plurality of voltages, a plurality of sample hold circuits corresponding to all of the plurality of sequences for sampling each of the plurality of voltages, and the sample hold circuit And a multiplexing means for time-division multiplexing the output of the above based on the selection signal.

Further, the output circuit of the solid-state imaging device according to the present invention is characterized by further comprising means for generating the sample signal from the selection signal by logic synthesis.

Further, the output circuit of the solid-state imaging device according to the present invention is the output circuit of the solid-state imaging device, which outputs a plurality of voltages detected by a plurality of series of charge detection units of the solid-state imaging device in a time-division multiplexed manner. On the basis of a sample signal for sampling each except one of the plurality of voltages, 1 is selected from the number of a plurality of series corresponding to all except one of the plurality of series which samples each except one of the plurality of voltages. Fewer sample hold circuits, multiplexing means for time-division multiplexing, based on a selection signal, the output of the charge detection unit of the series whose sampling is excluded and the output of the sample hold circuit of the series whose sampling is not excluded, It is characterized by having.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment 1] FIG. 1 is a block diagram of an output circuit of the solid-state imaging device, and FIG. 2 is a timing chart of the output circuit of the solid-state imaging device shown in FIG. The charges charged to the photodiodes (not shown) are generated by changing the clocks φ1 and φ2 as shown in FIG.
By driving at the timing shown in (b), the data is sequentially transferred to the charge detection units 3a, 3b, and 3c of the output circuit.

In FIG. 7, when T = ta, φR becomes LO
Becomes W and reset gate 2 (2a, 2b, 2c) turns on
, The charge of the charge detection unit 3 (3a, 3b, 3c) is absorbed by the drain 21 and the charge detection unit 3 (3
The voltages a, 3b, 3c) are predetermined voltages. T = tb
, Reset gate 2 (2a, 2b, 2c) is OFF
However, at this time, the charge detection unit 3 (3a, 3b, 3c)
Charge is gone.

When T = tc, the voltage of clock φ1 is Lo.
When the charge detection units 3a, 3b, 3
The charge is transferred to c. Charge detection unit 3 by charge transfer
The voltages generated at a, 3b and 3c are amplified by the source follower type amplifiers 4a, 4b and 4c. Output points A-1, A-2, A-3 of source follower-type amplifier sections 4a, 4b, 4c
The waveforms at are as shown in FIGS. 2 (d), (e) and (f). The sample hold circuits 5a, 5b, 5c are shown in FIG.
The output voltage of the sample hold circuits 5a, 5b, 5c is controlled by the sample hold signal shown in FIG.
(H), (i) and (j) are obtained. FIG.
Sample hold circuit 5 shown in (h), (i) and (j)
The output voltages a, 5b, and 5c do not have a wide non-signal period including reset and feedthrough, and have a sampling noise period (T = t0) and a signal period (T = ta + tb +
tc) only exists.

When signals of three colors are output from one output terminal (point d in FIG. 1), selection is made up of two bits changing as shown in FIGS. 2 (k) and (l). Signal s1,
The transistors 6a, 6b, 6c, 7a, 7
b and 7c are controlled. As a result, FIG.
The signal shown in (m) can be output from the output terminal (point d in FIG. 1).

The sample hold signal is a selection signal s
It may be generated by using a two-input OR gate having 1, s2 as an input.

Table 1 shows the relationship between the selection signals s1 and s2, the output signal at the output terminal (point d), and the sample hold signal.

[0017]

[Table 1] In the present embodiment, the signal periods t1, t2, and t3 in one bit
, The output signal from this output terminal can be sampled stably at the subsequent stage.

[Embodiment 2] Embodiment 2 is equivalent to Embodiment 1.
In the non-signal period of sample hold noise (t
0) has been removed. FIG. 3 is a block diagram showing the configuration of the output circuit of the charge transfer device according to the present embodiment. The difference in the configuration of the present embodiment from the first embodiment is as follows.
The point is that the sample hold circuit 5a is deleted from the sample hold circuits 5a, 5b, and 5c of the first embodiment.

FIG. 4 shows the timing of the output circuit in this embodiment. Referring to FIG. 4, during a period t0 in which the selection signals s1 and s2 take a combination of (Low, Low) in the first embodiment, the selection signals s1 and s2 are set to (H).
(high, High). Accordingly, the sampling period t0 is eliminated, and the period during which the signal at the point B-1 is selected becomes longer.

[0020]

As described above, according to the present invention, two or more types of signals output from the light receiving portion of the solid-state imaging device are switched and output during the charge transfer period in the light receiving portion after the sample hold. Thus, a stable output signal period can be secured. Therefore, it is possible to provide a solid-state imaging device in which the output data rate is improved by including the output circuit according to the present invention.

Further, according to the present invention, even if the data rate is increased, the signal period of each color can be secured stably, so that the conventional charge transfer rate can be increased to twice or more in the same output signal period. Becomes possible. Therefore, for example, it is possible to cope with progressive scan which is one of the television systems.

[Brief description of the drawings]

FIG. 1 is a block diagram of an output circuit of a charge transfer device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of an output circuit of the charge transfer device according to the first embodiment of the present invention.

FIG. 3 is a block diagram of an output circuit of a charge transfer device according to a second embodiment of the present invention.

FIG. 4 is a timing chart of an output circuit of the charge transfer device according to the second embodiment of the present invention.

FIG. 5 is a block diagram of an output circuit of a conventional charge transfer device.

FIG. 6 is a timing chart of an output circuit of a conventional charge transfer device.

FIG. 7 is a potential diagram of charge transfer in a charge detection region of a charge transfer device according to the present invention and a conventional example.

[Explanation of symbols]

 3a to 3c Charge detection unit 4a to 4c Source follower type amplifier unit 5a to 5c Sample hold circuit 6a to 6c, 7a to 7c Output changeover switch 8a to 8c Capacitor 15 N-type diffusion layer 16, 17, 18 P-type diffusion layer 19 N-type Substrate 20 Insulating film 21 Vod drain layer 22, 23 Output gate electrode 24 to 27 Transfer electrode

Claims (3)

(57) [Claims] 1. An output circuit of a solid-state imaging device for time-division multiplexing and outputting a plurality of voltages detected by a plurality of series of charge detection units of the solid-state imaging device, wherein a sample for sampling each of the plurality of voltages is provided. A plurality of sample hold circuits corresponding to all of the plurality of sequences that sample each of the plurality of voltages based on the signal; and an output of the sample hold circuit ,
Multiplexing means for performing time-division multiplexing based on a selection signal within a charge transfer period in the light receiving unit, and an output circuit of the solid-state imaging device. 2. The output circuit according to claim 1, further comprising: means for generating the sample signal from the selection signal by logic synthesis. 3. An output circuit of a solid-state imaging device for time-division multiplexing and outputting a plurality of voltages detected by a plurality of series of charge detection units of the solid-state imaging device, wherein each of the plurality of voltages except one is sampled. A sample hold circuit for sampling each of the plurality of voltages except for one of the plurality of voltages based on a sample signal for performing the sampling, excluding one of the plurality of sequences corresponding to all except one of the plurality of voltages; Multiplexing means for time-division multiplexing, based on a selection signal, the output of the charge detection unit of the series and the output of the sample hold circuit of the series whose sampling is not excluded. Output circuit.