JP3189784B2 - Layer 3 multicast transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a multilayer switch that supports VLAN and Layer 3 multicast, and more particularly to a Layer 3 multicast transmission system in a multilayer switch.

[0002]

2. Description of the Related Art Conventionally, between networks, for example, LA
A multi-layer switch is known as an inter-network connecting device for connecting N nodes. The multilayer switch is a device that identifies a layer 2 address or a layer 3 address of a received packet and transfers the packet. Such a multilayer switch includes a virtual LAN (hereinafter referred to as a VLAN) constructed regardless of a physical configuration.
) And layer 3 multicast (broadcast) communication. FIG. 5A is a block diagram of a conventional multilayer switch that supports VLAN and Layer 3 multicast, and FIG. 5B is a block diagram of a MAC controller for one port of the multilayer switch.

The control circuit 5 in the MAC controller 31a
3 is a PHY (Physicallayer protocol: not shown):
When an Ethernet packet as shown in FIG. 2 is received via the (physical layer protocol) controller, the packet data is stored in the reception FIFO 51 and the switch controller 33 is notified of the arrival of the packet. The DMA controller (hereinafter, referred to as DMAC) 43 in the switch controller 33
When the report of the packet reception is received from a, the packet data stored in the reception FIFO 51 of the MAC controller 31a is transferred to the packet buffer RAM32. Also,
At the same time, the DMAC 43 transfers from the head of the packet shown in FIG. 2 to a part of the data of the field 105 (layer 3 header) to the header register 41.

The search engine 42 includes a header register 41
Is compared with the search data in the search table RAM 34, the destination of the received packet is determined, and the destination information acquired by the destination determining process is reported to the queue writing block 44. In the queue buffer RAM 35, a transmission queue is provided for each port of the multiport MAC controller 31. The queue writing block 44 writes the destination information (queue data) received from the search engine 42 to a queue in the queue buffer RAM 35 corresponding to the port connected to the destination. The queue read block 45 reads the set destination information and activates the DMAC 43.
The DMAC 43 transfers the transmission data stored in the packet buffer RAM 32 to the transmission FIFO 52 of the MAC controller 1b connected to the transmission destination. At this time, when the layer 3 switch is performed, it is necessary to rewrite the MAC source address in the transmission data and the VLAN identifier in the tag of the transmission data. The control circuit 53 in the MAC controller 1b sequentially transfers the packet data written in the transmission FIFO 52 to the PHY controller, and finally calculates a frame check sequence and transfers it to the PHY controller.

If the received packet is a Layer 3 multicast packet, the search engine 42 notifies the queue writing block 44 of destination information indicating a plurality of destinations. Write the destination information. Even when packets are transmitted from the same port to a plurality of VLANs, destination information for the number of times of multicasting is set in the same queue. The queue read block 45 reads one piece of transmission destination information, activates the DMAC 43, and starts transferring data in the packet buffer RAM 32 to the transmission FIFO 52 of the output port of the MAC controller 31b. At this time, the MAC source address and the VLAN identifier are replaced and transferred. When the transfer of the packet is completed, the next destination information is read out, the DMAC 43 is started, and the data in the packet buffer RAM 32 is transferred again to the transmission FIFO 52 of the output port of the MAC controller 1b. The previous packet is the MAC source address and VL to be replaced
The only difference is the AN identifier.

[0006]

In such a multilayer switch as described above, different Vs connected to one port
When performing Layer 3 multicast for simultaneously transmitting packets to a plurality of VLANs specified by a LAN identifier, the same transmission data is repeatedly read from the packet buffer RAM by the number of times of multicasting (the number of VLANs to be transmitted). Because of the necessity, the transfer efficiency of the packet buffer bus is deteriorated. The reason is that the MAC controller for each port does not have a built-in FIFO memory for one packet, and when data read from the packet buffer RAM is transmitted, the data cannot be used again. This is because data must be input for the number of times of multicasting for transmission. The present invention has been made in order to solve the above-mentioned problem, and performs layer 3 multicast for simultaneously transmitting packets to a plurality of VLANs connected to the same port.
It is an object of the present invention to provide a layer 3 multicast transmission system capable of improving the transfer efficiency of a packet buffer bus.

[0007]

According to the present invention, there is provided a MAC which is provided for each communication port connected to an Ethernet and transmits and receives data to and from the Ethernet.
A multi-layer switch comprising a controller, a packet buffer RAM for storing a packet received by the MAC controller, and a switch controller for determining a destination of the packet based on a header of the received packet. If the packet is a Layer 3 multicast packet to be transmitted to a plurality of VLANs set to Ethernet connected to one communication port, the packet buffer RAM is sent to the MAC controller of the one communication port connected to the destination VLAN. Transfer the transmission data of one packet and the destination information including the number of multicasts stored in the
The MAC controller stores the transmitted transmission data for one packet and transmission destination information, and performs packet transmission for the number of times of multicast based on the transmission data and transmission destination information. As described above, the destination information including the transmission data for one packet and the number of times of multicasting is transmitted to the destination V
By storing it in the MAC controller of the communication port connected to the LAN,
Data transfer to the AC controller is performed only once, and M
While the transmission data is copied by the AC controller, packets can be transmitted for the number of times of multicasting. Further, as set forth in claim 2, the switch controller transfers, as the destination information, the number of multicasts, a VLAN identifier and a MAC source address for the number of multicasts, and the MAC controller is configured to transmit one packet. And a register for storing transmission data and transmission destination information, and VL in the transmission data for one packet.
A control circuit for transmitting packets for the number of times of multicasting while sequentially replacing the AN identifier and the MAC source address with the VLAN identifier and the MAC source address stored in the register.

[0008]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1A is a block diagram of a multilayer switch showing an embodiment of the present invention, and FIG. 1B is a block diagram of a MAC controller for one port of the multilayer switch. The multilayer switch of FIG. 1 is connected to an Ethernet (not shown), and transmits and receives data. The multi-port MAC controller 1, a packet buffer RAM 2 for temporarily storing received packets, and a header of a received packet based on the header. Switch controller 3 that determines destination of packet
A search table RAM 4 for storing search data for determining a destination of a received packet; and a queue buffer RAM 5 for storing destination information obtained by determining the destination.
And a CPU 6 for controlling the entire switch.

The switch controller 3 includes a header register 11 for storing a header of a received packet, a header stored in the header register 11 and a search table RAM 4.
A search engine 12 that determines the transmission destination and the like by checking the search data stored in the
Controller (hereinafter, referred to as DMAC) 13 that controls transfer of transmission / reception data between the controller 13 and the MAC controller 1
A queue writing block 14 for writing destination information to the queue buffer RAM 5;
Queue read block 15 for reading destination information from
It is composed of

The multi-port MAC controller 1 has a plurality of ports for exchanging data with the Ethernet, and each port has a one-port MAC controller 1a,
1b is provided (only two ports are shown in FIG. 1A). Each one-port MAC controller 1a,
1b, a reception first-in first-out memory (hereinafter abbreviated as reception FIFO) 21 for storing reception data, a VLAN multicast register 22 for storing transmission data of one packet transferred from the switch controller 3 and transmission destination information, And a control circuit 23 for controlling data transmission and reception. In FIG. 1B,
Although only the configuration of the one-port MAC controller 1a is shown, the other one-port MAC controllers have exactly the same configuration.

Next, the operation of the multilayer switch according to the present embodiment will be described with reference to the drawings. FIG.
FIG. 3 shows an example (IEEE 802.1Q) of an Ethernet packet format in which a LAN is set, and FIG.
FIG. 4 is a diagram showing an example of the structure of a VLAN multicast register 22 in each of the port MAC controllers 1a and 1b. FIG. 4 shows a multilayer switch using layer 3 multicast for simultaneously transmitting packets to a plurality of VLANs connected to the same port. FIG. 3 is a diagram showing a transmission packet transmitted from the STA.

In FIG. 2, 101 is a 6-byte MAC.
Destination address (MACDest.Add.: Media A
ccess Control Destination Address, 102 is a 6-byte MAC source address (MAC Sour.Add .: Media Access Control Source Addr)
ess), a field 103 stores a 4-byte tag including a 2-byte VLAN identifier for identifying a VLAN, a field 104 stores a 4-byte type, and a field 105 46 ~
A field in which 1500-byte data of the upper protocol is stored, and a field 106 in which a 4-byte frame check sequence (Frame Check Sequence) is stored.

In the following, packets received by the MAC controller 1a are transmitted to the Nth ports specified by the VLAN identifiers ID0 to IDN-1 connected to the ports of the MAC controller 1b.
A process in the case of a layer 3 multicast packet for VLANs will be described.

Control circuit 23 in MAC controller 1a
When an Ethernet packet as shown in FIG. 2 is received via a PHY (Physical layer protocol) controller (not shown), this packet data is stored in the reception FIFO 21 and the arrival of the packet at the switch controller 3 is notified. Report.

DMAC 13 in switch controller 3
When receiving the report of the packet reception from the MAC controller 1a, the reception FIFO 21 of the MAC controller 1a
The packet data stored in the buffer buffer RAM
Transfer to 2. At this time, the frame check sequence at the end of the packet is not transferred. At the same time, the DMAC 13 transmits a part of the data of the field 105 (Layer 3 header) from the top of the packet shown in FIG.
Are transferred to the header register 11.

Search data for determining a destination of a received packet is registered in the search table RAM 4 in advance. The search data includes a layer 2 address and a corresponding destination terminal address, a layer 3 address and a corresponding port address of the MAC controller 1, a layer 3 multicast address and a corresponding MAC controller 1 port Address and VLA
There are N identifiers.

The search engine 12 includes a header register 11
Is compared with the search data in the search table RAM 4 to determine the destination of the received packet, etc., and report the destination information acquired by the destination determining process to the queue writing block 14.

In the queue buffer RAM 5, a transmission queue is provided for each port of the multiport MAC controller 1. The queue writing block 14 is the destination information (queue data) received from the search engine 12
Is written to the queue in the queue buffer RAM 5 corresponding to the port connected to the transmission destination.

As described above, the packet received by the MAC controller 1a is a layer 3 multicast packet for N VLANs specified by VLAN identifiers ID0 to IDN-1 connected to the port of the MAC controller 1b. Therefore, when the search engine 12 searches the search table RAM 4 based on the packet header stored in the header register 11, the layer 3 in the header is searched.
According to the multicast address, the address of the port of the MAC controller 1b is obtained as the address of the port connected to the transmission destination, and the number of multicasts N indicating the number of packet transmissions (the number of VLANs to be transmitted) and the number of multicasts VLAN identifier ID0
~ IDN-1 and MAC source address SA0 ~ SAN-1
Is obtained.

In this manner, the search engine 12 determines the number of multicasts N, the MAC source addresses SA0 to SAN-1 and the VLAN identifiers ID0 to I for the number of multicasts.
DN-1, a packet buffer RA storing transmission data
The packet buffer address indicating the position on M2 is passed to the queue writing block 14 as the destination information, and the queue writing block 14 writes the destination information to the queue in the queue buffer RAM 5 corresponding to the port of the MAC controller 1b.

The queue reading block 15 reads the destination information set in the queue buffer RAM 5, and
Activate the MAC 13. As a result, the DMAC 13
The transmission data D0 stored at the position designated by the packet buffer address in the packet buffer RAM 2 is transmitted to the MAC controller 1b connected to the destination VLAN.
To the VLAN multicast register 22.

The DMAC 13 further includes a multicast number N and MAC source addresses SA0 to SAN-1 out of the destination information stored in the queue buffer RAM 5.
And the VLAN identifiers ID0 to IDN-1 to the VLAN multicast register 22 of the MAC controller 1b.

The MAC source addresses SA0 and V
The LAN identifier ID0 is for the packet to be transmitted first, and when these are transferred, the MAC source address in the transmission data D0 is replaced with the MAC source address SA0, and the tag TAG in the transmission data D0 is replaced.
The VLAN identifier included in 0 is replaced with VLAN identifier ID0.

Thus, the transmission data D0 for one packet
, The number of multicasts N, the number of MAC source addresses SA0 to SAN-1 and the number of VLAN identifiers ID0 to IDN-1 indicated by the number of multicasts N as shown in FIG.
Is written to the LAN multicast register 22 (V
LAN identifiers ID0 to IDN-1 are tags TAG0 to TAG
N-1).

Control circuit 23 in MAC controller 1b
When these are written in the VLAN multicast register 22, first, the transmission data D0 is output to the PHY controller as one packet and transmitted. At this time, the control circuit 23 calculates the frame check sequence FCS0 based on the transmission data D0 and generates a packet P0 by adding it to the last part of the transmission data D0 (FIG. 4).
(A)).

After the transmission of the packet P0 is completed, the control circuit 23
Replaces the MAC source address SA0 in the transmission data D0 with the MAC source address SA1 for the next packet to be transmitted, and replaces the VLAN identifier I in the tag TAG0.
Replace D0 with the following VLAN identifier ID1 and replace tag TA
G1 and the transmission data thus generated is output to the PHY controller. At this time, the control circuit 23 calculates the frame check sequence FCS1 based on the transmission data, and generates a packet P1 by adding it to the last part of the transmission data (FIG. 4B). Hereinafter, the same operation is repeated. As described above, the layer 3 multicast can be performed by repeating the packet transmission for the number of times of the multicast based on the transmission data of one packet and the destination information stored in the register 22 as described above.

[0027]

According to the present invention, as described in claim 1, transmission destination information including transmission data for one packet and the number of times of multicasting is stored in a MAC controller of a communication port connected to a destination VLAN. When performing layer 3 multicast for a plurality of VLANs connected to the same port, the packet buffer RA
Since it is not necessary to repeatedly read the same transmission data from M, the transfer efficiency of the packet buffer bus can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multilayer switch and a block diagram of a MAC controller for one port according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of an Ethernet packet format in which a plurality of VLANs are set.

FIG. 3 is a diagram illustrating an example of a structure of a VLAN multicast register in the MAC controller of FIG. 1;

FIG. 4 is a diagram showing a transmission packet transmitted from a multilayer switch by Layer 3 multicast.

FIG. 5 is a block diagram of a conventional multilayer switch and a block diagram of a MAC controller for one port.

[Explanation of symbols]

1: Multiport MAC controller, 1a, 1b ... 1
Port MAC controller, 2 ... packet buffer RA
M, 3 ... switch controller, 4 ... search table R
AM, 5: queue buffer RAM, 6: CPU, 11 ...
Header register 12: search engine, 13: DMAC,
14: Queue write block, 15: Queue read block, 21: Receive FIFO, 22: VLAN multicast register, 23: Control circuit.

Claims (2)

(57) [Claims] An MA provided for each communication port connected to the Ethernet, for transmitting and receiving data to and from the Ethernet.
A multi-layer switch comprising: a C controller; a packet buffer RAM for storing a packet received by the MAC controller; and a switch controller for determining a destination of the packet based on a header of the received packet. Are multiple Vs set to Ethernet connected to one communication port
If the packet is a layer 3 multicast packet to be transmitted to the LAN, the MAC controller of the one communication port connected to the destination VLAN transmits the transmission data for one packet stored in the packet buffer RAM and the number of multicasts. The MAC controller stores the transferred transmission data for one packet and the transmission destination information, and based on the transmission data and the transmission destination information, transmits the packets for the number of times of multicasting. A layer 3 multicast transmission method for performing transmission. 2. The layer 3 multicast transmission method according to claim 1, wherein the switch controller includes:
Multicast count, VLAN for multicast count
The MAC controller transfers an identifier and a MAC source address. The MAC controller includes a register for storing one packet of transmission data and transmission destination information, and a VLAN identifier and M in the one packet of transmission data.
A layer 3 multicast transmission system, comprising: a control circuit for transmitting packets for the number of times of multicasting while sequentially changing the AC source address to the VLAN identifier and MAC source address stored in the register.