JP3189553B2 - Arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit which is particularly suitable for performing a normalization shift of data having a plurality of types of bit lengths in a fixed length memory.

[0002]

2. Description of the Related Art In recent years, more advanced techniques have been introduced into digital signal processing, and arithmetic devices are required to perform higher speed and higher processing. Many of such processes include an operation of normalizing a plurality of types of bit length data in the memory.

Hereinafter, an example of a conventional arithmetic unit will be described with reference to the drawings. FIG. 2 is a block diagram showing a conventional arithmetic unit.

In FIG. 2, reference numeral 101 denotes an input data bus to which data from a memory or immediate data is given by an instruction; 102, a barrel shifter for arithmetically or logically shifting data on the input data bus 101; A normalized shift number latch for giving a shift number, 104 is a normalized shift number detector for detecting the normalized shift number of input data, 105 is an ALU (arithmetic logic operation circuit), and 106 is an output data bus.

The normalizing operation of the above configuration will be described below. First, the data to be normalized is transmitted from the input data bus 101 to the normalized shift number detector 10.
4 and a normalized shift number is detected. The detected normalized shift number is supplied to a normalized shift number latch 103, and the barrel shifter 102
3, the data supplied to the input data bus 101 is normalized-shifted, and the ALU 105
Output to

[0006]

However, in the above-described conventional arithmetic device, for example, a 1w / 24bit memory 2w stores upper 16 bits and lower 16 bits of 32 bit data, and normalizes this data. When trying, if the upper 16-bit data is 0,
The true normalized shift number is 15 + the lower data shift number, whereas the detected normalized shift number is 23 + the lower data shift number. This means that the maximum value of the normalized shift number is
It is fixed at the value of the bit length of the memory minus one. When there are data of a plurality of types of bit lengths in the memory and the data is to be normalized, normalization exceeding a meaningful bit length is performed. This is because there was a problem of normalizing with the shift number.

SUMMARY OF THE INVENTION The present invention solves the above-described conventional problem. Even when data of a plurality of types of bit lengths exist in a fixed-length memory, normalization that does not exceed the number of meaningful bits of the data is performed. It is an object of the present invention to provide an arithmetic device capable of detecting the number of shifts.

[0008]

According to the present invention, there is provided an input data bus to which input data is supplied, a barrel shifter for arithmetically or logically shifting the data on the bus, and a barrel shifter. A normalized shift number latch for giving a normalized shift number to the input data bus, and a normalized shift number for detecting the normalized shift number of the data supplied to the input data bus and setting the normalized shift number in the normalized shift number latch. A detector, a normalized maximum shift number control unit that controls the maximum value of the normalized shift number output from the normalized shift number detector, and a normalizer that is supplied from the input data bus to the normalized maximum shift number control unit. And a normalized maximum shift number latch in which the maximum value of the normalized shift number is set.

[0009]

Therefore, according to the present invention, when data having a bit length of a plurality of documents exists in the memory and the data is to be normalized, the normalized shift number to be detected is stored in the normalized maximum shift number latch. The normalized maximum shift number control can be limited by a given number.

[0010]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an arithmetic unit according to one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an input data bus to which input data from a memory or immediate data given by an instruction is given; A given normalized shift number latch, 4 is a normalized shift number detector that detects the normalized shift number of input data, 5 is an ALU (arithmetic logic operation circuit),
Reference numeral 6 denotes a normalized maximum shift number control unit for controlling the maximum value of the normalized shift number output from the normalized shift number detector 4;
Reference numeral 8 denotes a normalized maximum shift number latch in which the maximum value of the normalized shift number given from the input data bus 1 to the normalized maximum shift number control unit 6 is set, and eight output data buses.

In the above configuration, the normalizing operation will be described below. First, the normalized maximum shift number is set in the normalized maximum shift number latch 7 via the input data bus 1. Next, data to be normalized is supplied from the input data bus 1 to the normalized shift number detector 4, and the normalized shift number is detected. The detected normalized shift number is the normalized maximum shift number. The number control unit 6 limits the value to the value held in the normalized maximum shift number latch 7.

The normalized shift number detected as described above is applied to the normalized shift number latch 3, and the barrel shifter 2 uses the value of the normalized shift number latch 3 to apply the normalized shift number to the input data bus 1. The data to be shifted is normalized and output to the ALU5.

[0014]

As described above, according to the present invention,
When there are multiple types of bit length data in the memory and this data is to be normalized, the normalized shift number to be detected is determined by the maximum normalized shift number given by the normalized maximum shift number latch. Since the control unit restricts, a normalized shift number that does not exceed the number of significant bits of data can be detected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an arithmetic unit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional arithmetic unit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input data bus 2 Barrel shifter 3 Normalized shift number latch 4 Normalized shift number detector 5 ALU 6 Normalized maximum shift number control unit 7 Normalized maximum shift number latch 8 Output data bus

Claims (1)

(57) [Claims] An input data bus to which input data is supplied, a barrel shifter for arithmetically or logically shifting data on the bus, a normalized shift number latch for giving a normalized shift number to the barrel shifter, A normalized shift number detector for detecting a normalized shift number of given data and setting the normalized shift number in the normalized shift number latch, and a normalized shift number output from the normalized shift number detector And a normalized maximum shift number latch for setting the maximum value of the normalized shift number given from the input data bus to the normalized maximum shift number control unit. Computing device.