JP3188371B2 - MOS drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS drive circuit. More specifically, the present invention relates to a drive circuit for driving a MOS field-effect transistor used to configure a switching regulator.

[0002]

2. Description of the Related Art As a switching regulator, as shown in FIG. 4, a bridge diode BD1 for rectifying an AC input, a transformer T1 having a primary coil L _1, L ₃ and the secondary coil L _2, switching And a power MOS (power MOS type field effect transistor) 1 for performing the above-mentioned operation and an IC (integrated circuit) 1 for driving the MOS 1 are known. Connected capacitor C ₂₀₀ is between the output terminal and the GND of the bridge diode BD1 (ground), which in parallel with the resistor R ₂₀₀ and the Zener diode ZD ₂₀₀ is connected.

[0005] The output terminal G _{A of the} IC 1 is connected to the gate G of the MOS 1 via a resistor _RG . MOS1
A current detecting resistor Rs is interposed between the source S and GND (ground). The resistor Rs, the resistor R _204, capacitor C ₂₀₃ is connected in parallel, the resistance R ₂₀₄
An input terminal of the connection point between the capacitor C ₂₀₃ is IC1 Oc
It is connected to the.

After the SW power supply is started, the primary coil L ₃ , the diode D ₂₀₀ , and the capacitor C ₂₀₁ of the transformer T 1 rectify and smooth the stabilized voltage via the resistor R ₂₀₀ and the Zener diode ZD ₂₀₀ to the power supply of the IC 1. Supply to input terminal Vcc. When the Vcc voltage is supplied, IC1 operates and M1
The switching operation of OS1 starts. Then, electric power is transmitted to the secondary side through the transformer T1.

On the secondary side, an output voltage Vo rectified and smoothed by a diode D ₂₀₁ and a capacitor C ₂₀₂ is output. A shunt regulator SR1 for monitoring the output voltage Vo is provided on the secondary side, and performs feedback as follows.

The output voltage Vo is divided by the resistors R ₂₀₁ and R ₂₀₂ and is input to the Vref terminal of the shunt regulator SR1. In the shunt regulator SR1, when this voltage is higher than about 2.5, I _K increases, and the light amount on the light emitting side (light emitting diode) of the photocoupler PC1 increases. When the light quantity is large light-receiving side of the photocoupler PC1 (phototransistor) is Ic becomes large, the voltage V _FB of the feedback terminal F _B is more low (low). As a result, the switching duty of the MOS1 is reduced. Then, the amount of power transmitted to the secondary side decreases, and the output voltage Vo also decreases.

On the other hand, the output voltage Vo decreases and the input of the Vref terminal of the shunt regulator SR1 becomes 2.5
When the voltage becomes lower than V, the reverse operation occurs.

That is, Vref decreases → _Ik small → PC1
The amount of light becomes large → _VFB increases → the duty of MOS1 increases → the amount of power transmission increases → the output voltage Vo increases.

By adjusting the switching duty of the MOS 1 in this manner, the output voltage Vo can be kept constant (PWM (pulse width modulation) method). As a result, feedback is performed so that the Vref terminal becomes 2.5 V, and the output voltage Vo becomes Vo = ((R ₂₀₁
+ _R202 ) / _R202 ) x 2.5V.

[0010]

By the way, the above MOS
For switching 1, from G _A terminal of the IC1, as shown in FIG. 5 (a), the voltage V _GA is output having a substantially rectangular waveform. This output _VGA is connected to M via a resistor _RG.
Input to the gate of OS1. At this time, since the gate-drain capacitance C _DG (not shown) of the MOS 1 functions as a mirror capacitance, the gate drive current is bypassed to the drain side. As a result, change in the gate voltage V _G of this period slows, as shown in FIG. 5 (b), a predetermined rise time (the time the voltage reaches from 10% to 90% of the total variation) tr and fall The waveform has a time (time when the voltage reaches 90% to 10% of the total change amount) tf.

Here, when the resistance R _G is small, tr,
There is an advantage that the switching loss is reduced by shortening tf. However, since the current change rate becomes large,
At the time of switching, a large surge voltage is generated due to the inductance of the gate wiring, which may exceed the rating of the MOS1. Further, the occurrence of noise may cause the IC 1 to malfunction. Conversely, when R _G is large, t
Since r and tf become longer and the current change rate becomes smaller,
Surge voltage is reduced and ICs caused by noise
1 is less likely to malfunction. However, switching loss increases. Therefore, conventionally, the value of the resistor _RG is set so as to optimize tr and tf, so that the switching loss and the surge voltage of the MOS 1 fall within the allowable ranges.

However, the magnitudes of tr and tf do not depend solely on the value of the resistor _RG , but rather on the value of _RG and MO.
It depends on the magnitude of the CR time constant composed of the gate capacitance of S1. For this reason, there is a problem in that tr and tf are affected by variations in gate capacitance due to the manufacturing process of the MOS1.

Further, since the resistor _RG is externally provided between the IC1 and the MOS1, there is a problem that the number of parts increases and it is difficult to accommodate the IC1 and the MOS1 in one package.

Therefore, an object of the present invention is to provide an
An object of the present invention is to provide a MOS drive circuit which can omit the resistance between the transistor and the OS field effect transistor and can optimize tr and tf irrespective of manufacturing variations of the MOS field effect transistor.

[0015]

According to a first aspect of the present invention, there is provided a MOS driving circuit for switching a MOS type field effect transistor provided on a primary side of a transformer. A MOS drive circuit provided in a switching regulator that outputs a constant output voltage to the secondary side of the MOS field-effect transistor based on a feedback signal indicating the magnitude of the output voltage. And N is inserted between the power supply and the gate of the MOS type field effect transistor.
A single or Darlington-connected plurality of first bipolar transistors having one of the PN type and the PNP type are interposed between a gate of the MOS field effect transistor and a ground, and a base is formed of the first bipolar transistor. NPN or PNP connected to transistor base
A single or a plurality of second bipolar transistors having the other type connected in parallel, a capacitor connected between the base and ground of the bipolar transistors, and a power supply and ground. A constant current circuit section including at least two systems of current paths capable of flowing a current equal to each other by forming a current mirror circuit, wherein one current path of the constant current circuit section includes a current adjusting resistor. On the other hand, a switch is interposed on the ground side in another current path of the constant current circuit unit, and the power supply side terminal of the switch is connected to the base side terminal of the capacitor, and the feedback In response to the signal, the switch increases the duty as the feedback signal increases, while the feedback signal decreases. Brought to ON by reducing the duty, it is characterized by having a duty setting portion for turning off.

According to a second aspect of the present invention, there is provided the MOS drive circuit according to the first aspect, wherein the current adjusting resistor of the constant current circuit section is divided into a plurality of portions. An element that can be short-circuited by external power is connected in parallel to each part.

[0017]

The MOS drive circuit of the first aspect operates as follows. For convenience of description, a MOS field effect transistor to be driven (hereinafter abbreviated as “MOS”) is an N-channel type, and accordingly, the first bipolar transistor is an N-channel type.
The PN type and the second bipolar transistor are PNP type.

When the duty setting section turns off the switch of the constant current circuit section, a constant current flows from the constant current circuit section to the capacitor side, that is, a current adjusting resistor inserted in one current path of the constant current circuit section. A current having a magnitude equal to the current value determined by the above-described method flows, the capacitor is charged at a constant gradient corresponding to the current value, and the current flows into the base of the NPN type first bipolar transistor. Therefore, the NPN type first bipolar transistor is turned on and the gate voltage of the MOS rises, and as a result, the MOS is turned on. The rise time of the gate voltage of the MOS depends on the base current of the NPN first bipolar transistor. Therefore, it depends on the current flowing from the constant current circuit section to the capacitor side, and depends on the time constant between the capacitor and the current adjusting resistor. While the gate voltage of the MOS rises and remains at a high potential, the base of the PNP-type second bipolar transistor is maintained at a higher potential than the emitter, and is turned off.

On the other hand, when the duty setting section turns on the switch of the constant current circuit section, the electric charge accumulated in the capacitor flows to the ground side through the switch at a constant current value, that is, the constant current circuit section of the constant current circuit section. The current flows at a current value determined by a current adjusting resistor inserted in one current path. The capacitor is discharged at a constant gradient according to the current value. At this time, the NPN type first
The bipolar transistor is turned off when the base is at a lower potential than the emitter, and the PNP-type second bipolar transistor is turned on when the base is at a lower potential than the emitter. As a result, the gate voltage of the MOS falls,
The MOS turns off. The fall time of the gate voltage of the MOS depends on the base current of the PNP-type second bipolar transistor. Therefore, it depends on the current flowing to the ground side through the switch of the constant current circuit unit, and depends on the time constant of the capacitor and the current adjusting resistor.

As described above, according to this MOS drive circuit, the rise time of the gate voltage of the MOS to be driven is
The fall time depends on the time constant of the capacitor and the current adjusting resistor, and is adjusted by the time constant. Therefore, the resistance (R _{G in} FIG. 4) between the MOS and the MOS transistor is not required. That is, even without R _G , the surge voltage can be suppressed, noise can be reduced, and switching loss can be reduced. When R _G is omitted in this manner, M
The rise time and fall time of the gate voltage of the OS are not affected by the variation of the gate capacitance, and are almost as set by the time constant. Therefore, MOS
Rise time and fall time are optimized irrespective of manufacturing variations. When _RG is omitted, the MOS drive circuit is formed into an IC (integrated circuit) and
S can be easily accommodated in one package.

Since the duty setting section adjusts the duty of the switch based on the feedback signal, the duty of the MOS switching is also adjusted, and the output voltage of the switching regulator is kept constant as in the prior art.

When the MOS to be driven is a P-channel type, the first bipolar transistor is set to a PNP type and the second bipolar transistor is set to an NPN type accordingly. The operation of the MOS drive circuit is the same as described above except that the direction of the current and the rise and fall of the voltage are reversed.

Further, in the MOS drive circuit according to the second aspect, the current adjusting resistor of the constant current circuit section is divided into a plurality of portions, and the resistor is controlled in parallel with each of the resistors by external power. Since elements that can be short-circuited are connected, after this MOS drive circuit is manufactured, the elements connected in parallel to the respective parts of the resistor are individually short-circuited to fine-tune the value of the resistance (so-called Trimming) becomes possible. Therefore, the rise time and fall time of the MOS can be easily adjusted.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The MOS drive circuit according to the present invention will be described below in detail with reference to embodiments.

FIG. 1 shows an IC (integrated circuit) 2 having a MOS drive circuit according to an embodiment, and a MOS 2 driven by the IC 2. IC2 output terminal G _A is MO of
It is connected to the gate of S2. This MOS2 and IC2
Is the switching regulator shown in FIG.
It is used in place of MOS1 and IC1, and constitutes a part of this switching regulator. MOS2 is the same as MOS1.

As shown in FIG. 1, the IC 2 includes an output unit 1, a constant current circuit unit 2, and a duty setting unit 3.

[0027] The output unit 1 includes a power supply Vcc and the NPN transistor T _N5, T _N6 as a first bipolar transistor connected between the (in this case Vcc = 18V) and G _A terminal, G _A terminal and the ground And NPN transistors T _N7 and T _N9 connected between them. The NPN transistors T _N5 and T _N6 are Darlington connected,
Based rear stage transistor T _N6, bias setting resistor R ₆ is connected between the emitters. The NPN transistors T _N7 and T _N9 are also Darlington connected. A bias setting resistor R ₄ is connected between the base and the emitter of the preceding transistor T _N7 , and a bias setting resistor R ₅ and an NPN constituting a part of the duty setting unit 3 are connected between the base and the emitter of the _subsequent transistor T _N9. Transistor T _N8
And are connected.

[0028] between the G _A terminal and NPN transistor T _N9 Nobesu, the G _A terminal and NPN transistor T _N7
And PNP transistors T _P5 and T _P6 as second bipolar transistors that constitute a current mirror circuit with each other. Bases of the PNP transistors T _P5, T _P6 is connected to the NPN transistor T _N5 total over scan.

The emitter areas of the NPN transistors T _N6 and T _N9 are set sufficiently large so that the gate capacitance of the MOS 2 can be charged instantaneously if necessary.

Further, NPN transistors T _N5 and P _N5
NP transistor T _P5, T _P6 capacitor C ₁ between the Nobesu and ground are connected.

The constant current circuit section 2 is connected between the power supply Vcc # (Vcc # = 13.2 V in this example) and the ground.
It includes current paths 2A, 2B and 2C of the system.

The current path 2A includes a PNP transistor T
_P1 , an NPN transistor T _N1, and a current adjusting resistor R
3 is inserted. A PNP transistor _TP2 and an NPN transistor _TN2 are interposed in the current path 2B. In addition, the current path 2C, PNP transistor T _P3
And an NPN transistor T _N3 as a switch is interposed. Collector side terminal of the NPN transistor T _N3 is connected to the base side of the terminal of the capacitor C _1.

Three PNP transistors T _P1 , T _P2 , T
The base and emitter of _P3 are commonly connected to each other so as to form a current mirror circuit.
Currents equal to each other can be made to flow through A, 2B and 2C. Note that the PNP transistor _TP4 is
This is for _releasing the base current of each of the PNP transistors _TP1 , _TP2 , _TP3 to the ground.

The bias setting resistors R ₁ and R ₂ are connected in series between the constant voltage source Vs (Vs = 4 V in this example) and the ground, and the NPN transistor is connected between the resistors R ₁ and R _2. The base of T _N1 is connected. Resistance R ₁ , R ₂
Bias of the NPN transistor T _N1 is set by and R _3. Thereby, the magnitude of the current flowing through the current path 2A is determined, and accordingly, the remaining current path 2A
The magnitude of the current flowing through B and 2C is also determined.

Further, the bases and emitters of the NPN transistors T _N2 and T _{N3 of} the current paths 2B and 2C are commonly connected to each other so as to form a current mirror circuit. As a result, the flow branches current from the current path 2C to the capacitor C ₁ side, or even flowing current to the current path 2C from the capacitor C ₁ side, a current path 2B, is substantially equal to the current to 2C It is flowing. Note that N
The collector and the base of the PN transistor T _N2 are short-circuited to obtain a base current. An NPN transistor T _N4, which forms a part of the duty setting unit 3, is connected between the base and the emitter of the NPN transistors T _N2 and T _N3 .

The duty setting section 3 includes an oscillator OSC
1, a comparator CMP1, and an NPN transistor T
_N8 and T _N4 . The oscillator OSC1 outputs a triangular waveform signal Vosc having a constant period. Comparator C
MP1 receives an output voltage Vosc of the oscillator OSC _1, and a voltage V _FB inputted to the feedback terminal F _B,
When Vosc is lower than _VFB, H (high) level, Vos
When c is higher than V _FB, a signal Vc having a rectangular waveform that takes an L (low) level is output. The signal Vc of this rectangular waveform is H
Level indicates that MOS2 should be turned on.
When it is at the level, it indicates that MOS2 should be turned off. Since the output Vosc of the oscillator OSC1 is triangular waveform, signal Vc of the rectangular waveform, while the duty increases as the feedback voltage V _FB becomes greater, the duty becomes smaller as the feedback voltage V _FB becomes smaller. The NPN transistors T _N8 and T _N4 turn on and off according to the output of the comparator CMP1.

The MOS drive circuit operates as follows as a whole.

The comparator CMP of the duty setting unit 3
When the signal Vc of the rectangular waveform output from the H. 1 is at the H level, the NPN transistor T _N4 turns on and the NPN transistor T _N3 of the constant current circuit section 2 turns off. This allows
Constant current from the constant current circuit unit 2 to the capacitor C ₁ side, i.e., the current value equal to the magnitude of the current defined flow by the resistance R ₃ interposed in the current path 2A of the constant current circuit 2, The capacitor C ₁ is charged at a constant gradient according to the current value, and the NPN transistor T
Current flows into the _{bases of N5} and T _N6 . Therefore, the NPN transistor T _N5, T _N6 is turned on, the gate voltage V _GA of MOS2 as shown in FIG. 2 rises. This M
Rise time tr of the gate voltage V _GA of OS2 is dependent on the NPN transistor T _N5, T _N6 Nobesu current. Thus, a current path 2A is dependent on the current flowing in the capacitor C ₁ side, depending on the time constant of the said capacitor C ₁ and resistor R _3. Note that while the gate voltage of the MOS2 rises and remains at a high potential, the PNP transistors T _P5 and T _{P5
The base of P6} is maintained at a higher potential than the emitter, and is turned off.

On the other hand, when the rectangular waveform signal Vc of the duty setting unit 3 is at L level, the NPN transistor T _N4
Is turned off, and the NPN transistor T _N3 of the constant current circuit section 2 is turned off.
Turns on. Thus, a constant current value to the ground side through the electric charge stored in the capacitor C ₁ is an NPN transistor T _N3, i.e., defined by the resistance R ₃ interposed in the current path 2A of the constant current circuit part 2 Flows at the current value. Capacitor C ₁ is discharged at a constant gradient corresponding to this current value. At this time, the bases of the NPN transistors T _N5 and T _N6 are turned off because the base has a lower potential than the emitter, and the bases of the PNP transistors T _P5 and T _P6 are turned on because the base has a lower potential than the emitter. As a result, the gate voltage V _GA of MOS2 as shown in FIG. 2 falls. Fall time tf of the gate voltage V _GA of MOS2 is dependent on the base current of the PNP transistor T _P5, T _P6. Therefore, depending through the NPN transistor T _N3 current path 2A to the current flowing to the ground side, dependent on the time constant of the said capacitor C ₁ and resistor R _3.

[0040] Thus, according to the MOS driver circuit, the rise time tr, fall time tf of the gate voltage of MOS2 to be driven, the capacitor C ₁ and a resistor R ₃
And is adjusted by this time constant. Therefore, the resistance between the G _A terminal and MOS2 (R _G in FIG. 4) is unnecessary. That is, even without R _G , the surge voltage can be suppressed, noise can be reduced, and switching loss can be reduced. The NPN transistors T _N6 , T _N6
Since the emitter area of _N9 is set to be sufficiently large, when _RG is omitted in this manner, the gate of MOS2 is substantially controlled by voltage. That is, the rise time tr and the fall time tf of the gate voltage of the MOS 2 are not affected by the variation of the gate capacitance, and are almost as set by the time constant. Therefore, the rise time tr and the fall time tf can be optimized regardless of the manufacturing variation of the MOS2. Further, when _RG is omitted in this manner, IC2 and MOS2 including this MOS drive circuit can be easily accommodated in one package.

Further, as shown in FIG. 3, the constant current circuit portion 2 of the resistor R ₃ a plurality of portions _{R 3a, R 3b, R 3c} , divided into R _3d, relative to each portion of the resistor R ₃ Alternatively, an element that can be short-circuited by external power may be connected. R _3b In this example, R _3c, in parallel with R _3d moiety connects the Zener diode ZD1, ZD2, ZD3. Electrode pads PAD1, PAD2, PAD3, PAD4 are provided at both ends of each Zener diode ZD1, ZD2, ZD3. In this case, by applying power from the outside through the adjacent electrode pads P _AD1 , P _AD2 , P _AD3 , P _AD4 , the Zener diodes Z _D1 , Z _D2 , Z _D3 are applied.
It is the individually be shorted to finely tune the values of the resistor R ₃ (so-called trimming). Therefore, the above M
The rise time tr and the fall time tf of the OS2 can be easily adjusted.

[0042]

As is apparent from the above description, M of claim 1
According to the OS drive circuit, the rise time and the fall time of the gate voltage of the MOS to be driven are controlled by the capacitor connected between the bases of both bipolar transistors in the output section and the ground and the current adjustment of the constant current circuit section. And is adjusted by this time constant. Accordingly, the resistance (R _{G in} FIG. 4) between the MOS and the MOS transistor can be omitted. That is, even without R _G , the surge voltage can be suppressed, noise can be reduced, and switching loss can be reduced. If R _G is omitted in this way,
The rise time and the fall time of the gate voltage of the MOS are not affected by the variation of the gate capacitance, and are almost the values set by the time constant. Therefore, MO
The rise time and the fall time can be optimized regardless of the manufacturing variation of S. If _RG is omitted, the MOS drive circuit formed as an IC (integrated circuit) and the MOS can be easily accommodated in one package.

Further, in the MOS drive circuit according to the second aspect, the current adjusting resistor of the constant current circuit section is divided into a plurality of portions, and the resistor is controlled in parallel with each of the resistors by external power. Since elements that can be short-circuited are connected, after this MOS drive circuit is manufactured, the elements connected in parallel to the respective parts of the resistor are individually short-circuited to fine-tune the value of the resistance (so-called Trimming). Therefore, the rise time and fall time of the MOS can be easily adjusted.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an IC having a MOS drive circuit according to an embodiment of the present invention and a MOS to be driven by the IC.

FIG. 2 is a diagram showing a waveform of a gate voltage of the MOS.

FIG. 3 is a diagram showing a configuration of a current adjusting resistor.

FIG. 4 is a diagram showing a circuit configuration of a switching regulator.

FIG. 5 is a diagram showing a comparison between voltage waveforms at both ends of a resistor _RG provided between an IC and a MOS.

[Explanation of symbols]

First output portion 2 constant current circuit unit 3 duty setting section F _B feedback terminal G _A IC output terminals

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H03K 17/567 H03K 17/56 D (58) Investigated field (Int.Cl. ⁷ , DB name) H02M 3/28 H02M 1 / 08 H02M 7/537 H03K 17/04 H03K 17/14

Claims (2)

(57) [Claims] 1. A MOS type field effect transistor (MOS2) provided on a primary side of a transformer is switched,
Provided to the switching regulator which is adapted to output a constant output voltage on the secondary side of the transformer, a feedback signal representative of the magnitude of the output voltage (F _B) the MOS-type field-effect transistor based on (MOS2) Drive circuit (IC2) for turning on and off a transistor, and one of an NPN type or a PNP type interposed between a power supply (Vcc) and a gate of the MOS type field effect transistor (MOS2). And a plurality of first bipolar transistors (T _N5 , T _N6 ) connected in Darlington connection or a plurality of transistors, and the first bipolar transistor (T _N5 , T _N6 ) is interposed between the gate of the MOS type field effect transistor (MOS2) and the ground, and the base is the first bipolar transistor transistor (T _N5, T _N6) s parallel with the other types of the NPN or PNP type is connected to a total of over scan And a plurality of connected second bipolar transistor (T _P5, T _P6), the both bipolar transistors _{(T N5, T N6, T} P5, T
_P6 ) A capacitor (C ₁ ) connected between the base and the ground, and a current mirror circuit between the power supply (Vcc #) and the ground to allow at least the same current to flow. A constant current circuit section (2) including two current paths (2A, 2B, 2C); a current adjusting resistor (R) is provided in one current path (2A) of the constant current circuit section (2); _{while 3)} is interposed, it said in another current path of the constant current circuit section (2) (2C) switch (T _N3) is interposed to the ground side, and the power source side of the switch (T _N3) Is the capacitor (C ₁ )
Of which is connected to the base side of the terminal, receiving the feedback signal (F _B), the switch (T _N3), while increasing the duty as the feedback signal (F _B) is large, the feedback signal (F _B) by decreasing the duty as decreases on the duty setting unit to turn off (3)
A MOS drive circuit comprising: 2. The MOS drive circuit according to claim 1, wherein said current adjusting resistor (R ₃ ) of said constant current circuit section (2) has a plurality of portions (R _3a , R _3b , R _3c , R ₃ ). is divided into _3d), each portion of the resistor _{(R 3) (R 3b,} R 3c, in parallel with R _3d), elements which can be short-circuited by the power from the outside _{(Z D1, Z D2, Z} D3) Is connected to the MOS drive circuit.