JP3161514B2 - DC power supply - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC power supply capable of performing highly stable switching control even under a light load.

[0002]

2. Description of the Related Art As shown in FIG. 4, for example, a conventional DC power supply device is connected between DC input terminals 1 and 2 to which a DC power supply such as a battery or a rectifier circuit is connected, and between the DC input terminals 1 and 2. Input smoothing capacitor 3 and primary to tertiary winding 4a
4c, a primary winding 4a and a MOS-FET 5 as a switching element of the transformer 4 connected in series to both ends of the input smoothing capacitor 3, and a rectifying diode 6 in the secondary winding 4b of the transformer 4. And a load 9 connected via a rectifying and smoothing circuit 8 comprising an output smoothing capacitor 7 and an output voltage detecting circuit 1 as an output voltage detecting means for detecting a voltage of the load 9 and generating a feedback control signal _VFB.
0 and the MOS-F connected in series with the MOS-FET 5
A current detection resistor 11 as current detection means for detecting a current flowing through the ET 5 as a voltage corresponding thereto, and an output voltage detection input to a feedback signal input terminal 13a via a light emitting portion 12a and a light receiving portion 12b of the photocoupler 12. Circuit 10
_Is applied from the control signal output terminal 13d to the gate terminal (control terminal) of the MOS-FET 5 based on the feedback control signal _VFB and the current detection signal VIS of the current detection resistor 11 input to the current detection signal input terminal 13b. and a control circuit 13 for outputting an oN width variable and off a constant width of the control pulse signal V _G. The control circuit 13 is controlled by varying the signal output ON width of the control pulse signal V _G output from the terminal 13d on the basis of a feedback control signal V _FB and the current detection signal V _IS, the MOS-FET 5 off control To control the DC output voltage V _OUT supplied to the load 9 to a constant value. Also,
In the DC power supply device shown in FIG. 4, the starting resistor 14 connected between the positive (+) DC input terminal 1 and the power supply terminal 13c of the control circuit 13, the tertiary winding 4c of the transformer 4, A control power supply circuit 17 comprising a rectifying diode 15 and a smoothing capacitor 16 and supplying drive power to the power supply terminal 13c of the control circuit 13 from both ends of the smoothing capacitor 16 after the control circuit 13 is started; a MOS-FET 5 and current detection And a voltage resonance capacitor 18 connected in parallel with the series circuit of the resistor 11. Note that the MOS-FET 5 and the control circuit 13 in the DC power supply device of FIG. 4 are integrally formed as a single IC module.

[0003] The control circuit 13 is controlled by a MOSFET 21 based on a control circuit regulator 21 connected to a power supply terminal 13c and a feedback control signal _VFB input to a feedback signal input terminal 13a.
A reference power supply 25 consisting of the constant current circuit 22 and a resistor 23, 24 for generating a reference voltage V _B corresponding to the limit current value of the FET 5, between the output terminal and the current detection signal input terminal 13b of the control circuit for the regulator 21 The voltage value of the non-inverting input terminal 28a connected to the connection point B between the resistances 26 and 27 connected in series and the resistances 23 and 24 of the reference power supply 25 and the resistance 2
A comparator 28 for comparing a voltage value of an inverting input terminal 28b connected to a connection point A between the MOS transistor 6 and the MOS-FET 5 based on an output signal from the control circuit regulator 21;
An oscillation circuit 29 for generating an ON width variable and off a constant width of the control pulse signal V _G to be applied to the gate terminal of the oscillation circuit 2
9 through the control signal output terminal 13d.
Drive circuit 30 connected to the gate terminal of S-FET5
And a transistor 31 connected between the output terminal of the oscillation circuit 29 and the ground terminal 13e and turned on by an output signal from the comparison output terminal 28c of the comparator 28. The oscillation circuit 29 includes resistors 32, 3
3, diodes 34 and 35, transistor 36, comparator 37 and consists OFF period setting capacitor 38 and a resistor 39 for off of the control pulse signal V _G which is output by the time constant of the capacitor 38 and a resistor 39 for off-period setting The width is determined. Further, the output voltage detection circuit 10
As shown in FIG. 5, two voltage dividing resistors 41 and 42 connected between the output voltage input terminals 10a and 10b, a base terminal is connected to a connection point of the voltage dividing resistors 41 and 42, and a collector terminal is a detection output. An error amplifying transistor 43 connected to the terminal 10c; a constant voltage diode 44 connected between the voltage dividing resistor 42 and the emitter terminal of the error amplifying transistor 43; an emitter terminal of the voltage dividing resistor 41 and the error amplifying transistor 43 And a resistor 45 connected therebetween.

In the above configuration, when DC power from a DC power supply (not shown) is supplied from the DC input terminals 1 and 2 via the input smoothing capacitor 3, the smoothing capacitor of the control power supply circuit 17 is connected via the starting resistor 14. 16 is charged and a voltage is applied to the power supply terminal 13c of the control circuit 13, and the control circuit regulator 21 in the control circuit 13 starts operating. Smoothing capacitor 16 of control power supply circuit 17
When the stabilized voltage is output from the control circuit regulator 21 in the control circuit 13 when the charging voltage of the control circuit 13 reaches a predetermined value, the oscillation circuit 29 starts operating, and the control signal output terminal 13 d more control pulse signal V _G to the gate terminal of the MOS-FET 5 is given, MOS-FE
T5 starts the on / off operation. At this time, the non-inverting input terminal (+ terminal) of the comparator 37 in the oscillation circuit 29
And an inverting input terminal - indicating signals are input to (terminal) V _D, the voltage waveform of the V _E in FIG. 6 (A). When the voltage of the signal V _D falls from the high level (6.5V) to low level (3.5 V), constant at high levels when the signal V voltage capacitor 38 and a resistor for the OFF period setting _E 39 (5. 0V). Voltage signal V _E is low (3.
When drops to 5V), the voltage of the signal V _D is low (3.
5V) to a high level (6.5V). By repeating the above operation, the comparator 3 in the oscillation circuit 29
ON width is output through the drive circuit 30 from 7 output terminal of the variable-off constant width of the control pulse signal V _G is formed. By the ON / OFF operation of the MOS-FET 5, the voltage across the input smoothing capacitor 3 is intermittently applied to the primary winding 4a of the transformer 4, and an AC voltage is generated in the primary winding 4a. The AC voltage generated in the primary winding 4a of the transformer 4 induces a stepped-down or boosted AC voltage in the secondary winding 4b. At the same time, an AC voltage is also induced in the tertiary winding 4c of the transformer 4, and this AC voltage is applied to the control power supply circuit 1
8 is rectified and smoothed by the rectifying diode 15 and the smoothing capacitor 16, and after the start-up, a DC voltage is supplied to the control circuit regulator 21 in the control circuit 13 through the power supply terminal 13c. The AC voltage induced in the secondary winding 4b of the transformer 4 is rectified and smoothed by the rectifying diode 6 and the output smoothing capacitor 7 of the rectifying and smoothing circuit 8,
The step-down or step-up DC output voltage V _OUT is supplied to the load 9.

The DC output voltage V _OUT at both ends of the load 9 is divided by two voltage dividing resistors 41 and 42 of the output voltage detecting circuit 10, and the voltage at the voltage dividing point is applied to the base terminal of the error amplifying transistor 43. The constant voltage diode 4 which is inputted and connected to the emitter terminal of the error amplifying transistor 43
A voltage corresponding to the difference between the voltage of V.4 and the voltage at the voltage dividing point of the voltage dividing resistors 41 and 42 is generated at the collector terminal of the error amplifying transistor 43. As a result, the detection output terminal 10 is changed according to the voltage of the collector terminal of the error amplifying transistor 43.
The light-emitting portion 12a of the photocoupler 12 connected to the light-emitting portion 12c emits light and a current flows through the light-receiving portion 12b, and the output of the light-receiving portion 12b is used as a feedback control signal _VFB as a feedback signal input terminal
Input to 3a. The constant current circuit 22 of the reference power supply 25 is _generated by the feedback control signal _VFB input to the feedback signal input terminal 13a.
Is driven, and the resistors 23, 2 based on the feedback control signal V _FB.
The MOS-FET 5 as shown in FIG.
Limit current value reference voltage V _B corresponding to occur in. On the other hand, the current I flowing through the MOS-FET 5 shown in FIG.
_D is detected by the current detection resistor 11 as a voltage corresponding to the current, and the current detection signal V _IS
3 is input to the current detection signal input terminal 13b. At this time, the resistor 2 connected in series between the output terminal of the control circuit regulator 21 and the current detection signal input terminal 13b.
_A voltage _VA shown in FIG. 6B is generated at a connection point A between the terminals 6 and 27. Voltage V _A shown in FIG. 6 (B) is input to the inverting input terminal 28b of the comparator 28 is compared with a reference voltage V _B which is input to the non-inverting input terminal 28a. M shown in FIG.
Increased current I _D flowing through the OS-FET 5, the voltage V _A shown in FIG. 6 (B) is lower than the reference voltage V _B, the output signal to the base terminal of the transistor 31 is sent from the comparison output terminal 28c of the comparator 28 , The transistor 31 is turned on. At this time, the driving circuit 30
Control pulse signal V _G which is output via a becomes low level, MOS-FET 5 is turned off. This allows
The current _ID flowing to the MOS-FET ₃ is limited,
The overcurrent protection of the FET 5 becomes possible. At this time, the MOS-FET is supplied from the oscillation circuit 29 through the drive circuit 30.
5 the voltage waveform of the control pulse signal V _G applied to the gate terminal of FIG. 6 (D).

When the load 9 enters a light load state and the impedance of the load 9 increases, the voltage at the voltage dividing points of the voltage dividing resistors 41 and 42 of the output voltage detecting circuit 10 increases, and the output voltage of the detection output terminal 10c increases. The photo coupler 1
The light intensity of the second light emitting unit 12a increases, the current flowing to the light receiving unit 12b increases, and the voltage of the feedback control signal _VFB increases.
Descent Therefore, the reference voltage V _B at the connection point B of the resistors 23 and 24 is increased, the level of the voltage V _A is the reference voltage V _B at the connection point A of the resistors 26, 27 as shown in FIG. 7 (A) The time to do it is shorter. Therefore, as shown in FIG.
-Control pulse signal V _G applied to the gate terminal of FET5
Is narrowed, and the time width of the current _ID flowing through the MOS-FET 5 is narrowed as shown in FIG. For this reason, the maximum value of the current _ID flowing through the MOS-FET 5 decreases. Conversely, when the impedance of the load 9 is lowered, the operation and reverse operation is performed, a pulse of the control pulse signal V _G applied to the gate terminal of the MOS-FET 5 through the drive circuit 30 from the oscillation circuit 29 Wider. Therefore, the maximum value of the current _ID flowing through the MOS-FET 5 increases. As described above, the oscillation circuit 29 changes the driving circuit 30 according to the fluctuation of the voltage or the impedance of the load 9.
MOS-F with the pulse width of the control pulse signal V _G to be applied to the gate terminal of the MOS-FET 5 is controlled through
The maximum value of the current _ID flowing through the ET 5 is controlled, and the DC output voltage V _OUT supplied to the load 9 is controlled to a constant value.

[0007]

By the way, in the conventional DC power supply device shown in FIG.
If the maximum value of the current I _D flowing through the -FET5 small, 7
As shown in (B), a spike-shaped surge current generated when the MOS-FET 5 is turned on is superimposed on the current _ID flowing through the MOS-FET 5, and the resistance 2
Minimum value of the voltage V _A at the connection point A of 6,27 Figure 7
It may become level equal to or below it and the reference voltage V _B at the connection point B of the resistors 23 and 24 of the reference power supply 25 as shown in (A). Therefore, the comparator 28
There control pulse signal V _G as shown in FIG. 7 (C) becomes instantaneously higher level by detecting the surge current, MOS-FET 5
May turn on instantaneously. Therefore, when the load 9 is in a light load state, there is a disadvantage that the comparator 28 malfunctions due to the surge current and the switching control of the MOS-FET 5 becomes unstable.

Accordingly, an object of the present invention is to provide a DC power supply capable of performing highly stable switching control even under a light load.

[0009]

A DC power supply according to the present invention comprises a DC power supply and a transformer having a plurality of windings.
And one of the transformers (4) connected in series at both ends of the DC power supply.
A secondary winding (4a) and a switching element (5), a load (9) connected to a secondary winding (4b) of a transformer (4) through a rectifying and smoothing circuit (8), and a load (9). Voltage is detected and feedback control signal (V _FB )
Output voltage detection means (10) for generating
(5) a current detecting means (11) for detecting a current flowing as a corresponding voltage value, a feedback control signal (V _FB ) of the output voltage detecting means (10) and a detection signal (V) of the current detecting means (11). _IS ) to output an on / off control signal to be applied to the control terminal of the switching element (5). The switching element (5) is turned on / off by an on / off control signal of the control circuit (13) to control the DC output voltage supplied to the load (9) to a constant value. The control circuit (13) includes a capacitor (52) and receives a feedback control signal (V _FB ) of the output voltage detecting means (10) to control a charging current to the capacitor (52), thereby controlling the capacitor (52). A reference signal generating circuit (55) for varying the charging voltage of the capacitor, a charging voltage value of the capacitor (52) of the reference signal generating circuit (55) and a voltage value of the current detecting means (11).
(V _IS ), a first comparing means (51a, 51c), a reference power supply (25) for generating a voltage for determining a limiting current value of the switching element (5), and a voltage of the reference power supply (25). Second comparing means (51) for comparing the current value with the voltage value (V _IS ) of the current detecting means (11).
b, 51c). When the feedback control signal (V _FB ) is present, the maximum value of the current flowing through the switching element (5) is controlled by the comparison output signal of the first comparing means (51a, 51c) and supplied to the load (9). Control the DC output voltage to a constant value.
At the time of overload or output short circuit, the output voltage detection means (1
0) when there is no feedback control signal (V _FB )
Switching element (5) by comparison output signal of (51b, 51c)
The current flowing through is limited to a constant value. In the embodiment of the present invention, the first comparing means (51a, 51c) and the second comparing means (5
1b, 51c) are provided in the same comparison element (51).

The output voltage applied to the load (9) by the on / off operation of the switching element (5) is detected by the output voltage detecting means (10), and is output as a feedback control signal (V _FB ) to the control circuit (V _FB ). 13) is applied to the reference signal generation circuit (55). The charging current to the capacitor (52) is controlled by inputting the feedback control signal (V _FB ) to the reference signal generation circuit (55),
The charging voltage of the capacitor (52) is varied. On the other hand, the current flowing through the switching element (5) due to the on / off operation of the switching element (5) is detected by the current detecting means (11) as a voltage value (V _IS ) corresponding thereto. The charging voltage of the capacitor (52) of the reference signal generating circuit (55) is variable according to the state of the load (9), and the charging voltage of the capacitor of the reference signal generating circuit (55) is changed.
(52) charging voltage value and current detecting means (11) voltage value (V _IS )
Are compared by the first comparing means (51a, 51c), the maximum value of the current flowing through the switching element (5) is controlled by the comparison output signal, and the DC output voltage supplied to the load (9) becomes constant. Controlled. Therefore, it is possible to prevent the switching element (5) from malfunctioning due to a surge current in a light load state of the load (9), and to perform highly stable switching control even under a light load. If the load (9) is overloaded or the output is short-circuited and there is no feedback control signal (V _FB ) of the output voltage detecting means (10), the reference power supply corresponding to the limited current value of the switching element (5) is used. (25) voltage value and current detection means (11) voltage value
(V _IS ) is compared by the second comparing means (51b, 51c), and the current flowing through the switching element (5) is limited to a constant value by the comparison output signal. The current flowing through the element (5) can be limited to a constant value.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a DC power supply according to the present invention will be described below with reference to FIGS. However,
In FIG. 1, portions substantially the same as the portions shown in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 1, the DC power supply of the present embodiment includes a two-signal input type comparator 28 having a non-inverting input terminal 28a, an inverting input terminal 28b, and a comparison output terminal 28c in the DC power supply shown in FIG. 1 non-inverting input terminal 51a, second non-inverting input terminal 51b, inverting input terminal 51c, and comparison output terminal 5
Three-signal input type comparator having 1d (comparative element)
51, the connection point of the resistors 23 and 24 is connected to the second non-inverting input terminal 51b of the comparator 51, and the collector terminal of the transistor on the constant current output side (right side in the drawing) constituting the constant current circuit 22 is controlled. A capacitor 52 is connected between the ground terminal 13 e of the circuit 13 and a connection point between the collector terminal of the transistor on the right side of the constant current circuit 22 and the capacitor 52 is connected to a first non-inverting input terminal 51 a of the comparator 51.
, A transistor 53 is connected in parallel with the capacitor 52, and an inverting amplifier 54 is connected between the collector terminal of the transistor 31 and the base terminal of the transistor 53. In FIG. 1, the constant current circuit 22 and the capacitor 52 charge the capacitor 52 by changing the constant current output of the constant current circuit 22 based on the feedback control signal _VFB input to the feedback signal input terminal 13a of the control circuit 13. A reference signal generating circuit 55 for varying the charging voltage of the capacitor 52 by controlling the current is provided.
The reference power source generates a voltage corresponding to the current limit value of the OS-FET 5. Also, in the three-signal input type comparator 51, the charging voltage value of the capacitor 52 of the reference signal generating circuit 55 input to the first non-inverting input terminal 51a and the resistors 26, 27 input to the inverting input terminal 51c are provided. The first comparing means for comparing the voltage value at the connection point of the first and second resistors, the voltage value at the connection point of the resistors 23 and 24 inputted to the second non-inverting input terminal 51b and the resistance 2 inputted to the inverting input terminal 51c.
Second comparing means for comparing the voltage values at the connection points 6 and 27 is provided. Other configurations are substantially the same as those of the DC power supply device shown in FIG. The internal configuration of the output voltage detection circuit 10 shown in FIG. 1 is substantially the same as the internal configuration of the output voltage detection circuit 10 shown in FIG.

Next, the operation of the DC power supply shown in FIG. 1 will be described. Since the basic operation of the main circuit is substantially the same as the operation of the DC power supply device shown in FIG. 4 described above, detailed description will be omitted. In the circuit shown in FIG. 1, the control pulse signal V _G from the control circuit 13 to the gate terminal of the MOS-FET 5 is given, when the MOS-FET 5 starts to on-off operation, the load via the transformer 4 and the rectifier smoothing circuit 8 9 is supplied with a DC output voltage V _OUT . The DC output voltage V _OUT supplied to the load 9 is detected by the output voltage detection circuit 10 and is used as a feedback control signal V _FB by the reference signal generation circuit 55 from the photocoupler 12 via the feedback signal input terminal 13 a of the control circuit 13. It is input to the current circuit 22. The constant current circuit 22 varies the charging voltage of the capacitor 52 by controlling the charging current flowing through the capacitor 52 by changing the constant current output based on the feedback control signal _VFB . At this time, the voltage V _{C at} the connection point C between the collector terminal of the transistor 53 connected to the constant current circuit 22 and the capacitor 52
Rises at a gentle slope as shown in FIG. On the other hand, when the MOS-FET 5 is turned on, the transformer 4
Stray capacitance of each winding 4a-4c, capacitor 1 for voltage resonance
2B, a spike-shaped surge current is generated as shown in FIG. 2B by the discharge current of the rectifier diode 6 constituting the rectifier smoothing circuit 8 and the recovery current of the rectifier diode 6.
The current is superimposed on the current _ID flowing through the S-FET 5. This current I
_D is detected by the current detection resistor 11 as a voltage corresponding to the current _ID , and is used as a current detection signal V _{IS by the} control circuit 13.
Is input to the current detection signal input terminal 13b of the
_A voltage _VA shown in FIG.
A resistor 2 connected in series between the output terminal of the control circuit regulator 21 and the ground terminal 13 e of the control circuit 13.
As shown in FIG. 2A, a connection point B between
The voltage V _B generated corresponding to the limit current value of -FET5.

The voltages V _A generated at the connection points A, B, and C,
V _B and V _C are input to an inverting input terminal 51c, a second non-inverting input terminal 51b, and a first non-inverting input terminal 51a of the comparator 51, respectively. The voltage V _C input to the first non-inverting input terminal 51a and the voltage _VA input to the inverting input terminal 51c are compared by the first comparing means in the comparator 51, and the MOS- When the voltage V _a as shown on the left side (normal load) of FET5 the increased current I _D flowing through FIG 2 (a) is lower than the voltage V _C, the high level (H level from the comparator output terminal 51d of the comparator 51 ) A signal is output. This output signal causes the transistor 31
There turned on, the high level as the control pulse signal V _G applied to the gate terminal of the MOS-FET 5 via the drive circuit 30 from the oscillation circuit 29 is shown in FIG. 2 (C) (H level) from a low level ( L level). At this time, FIG.
As shown in (B), the current _ID flowing through the MOS-FET 5 becomes substantially zero. At the same time, the reference signal generating circuit 55 is connected to the collector terminal of the transistor 31 via the inverting amplifier 54.
The signal applied to the base terminal of the transistor 53 becomes high level, and the transistor 53 is turned on. At this time, the charge charged in the capacitor 52 is discharged through the transistor 53, and the charged voltage of the capacitor 52 becomes substantially 0 V. Therefore, the collector terminal of the transistor on the right side of the constant current circuit 22 of the reference signal generation circuit 55, the capacitor 52, and voltage V _C of the connection point C drops to approximately 0V as shown on the left side shown in FIG. 2 (a) of.

If the load 9 is overloaded or the load 9 is substantially short-circuited and the impedance of the load 9 becomes extremely low, the DC output voltage V _OUT supplied to the load 9 becomes substantially 0 V. 10 to Photocoupler 12
The feedback control signal V _FB input to the feedback signal input terminal 13a of the control circuit 13 via the light emitting unit 12a and the light receiving unit 12b
Becomes substantially zero. For this reason, the voltage V _{C at} the connection point C between the collector terminal of the transistor on the right side of the constant current circuit 22 of the reference signal generation circuit 55 and the capacitor 52 changes to the right side of FIG. As shown in FIG. At this time, the voltage _VA generated at the connection point A between the resistors 26 and 27 by the current _ID flowing through the MOS-FET 5 is changed by the second comparing means in the comparator 51 to the resistors 23 and 24.
It is compared with the voltage V _B corresponding to the limit current value of the MOS-FET 5 developing in a node B. Figure 2 (B) of the go current I _D flowing through the MOS-FET 5 as shown on the right side is increased, when the voltage V _A falls to a level of the voltage V _B as shown on the right side of FIG. 2 (A), the comparator A high-level signal is output from the comparison output terminal 51d of 51. Thereby, the MOS-FET 5 is supplied from the oscillation circuit 29 through the drive circuit 30.
Figure 2 the control pulse signal V _G which is granted to the gate terminal
From the high level to the low level as shown on the right side of (C),
The current _ID flowing through the MOS-FET 5 becomes substantially zero as shown on the right side of FIG.

Conversely, when the load 9 is in a light load state and the impedance of the load 9 is high, the DC output voltage V _OUT supplied to the load 9 becomes higher than usual.
From the output voltage detection circuit 10 to the light emitting portion 1 of the photocoupler 12
The voltage value of the feedback control signal V _FB input to the feedback signal input terminal 13a of the control circuit 13 via the light receiving section 12a and the light receiving section 12b becomes higher than that at the time of the normal load described above. Thereby, the constant current circuit 22 of the reference signal generation circuit 55
Since the charging current flowing through the secondary becomes higher the charging voltage of the capacitor 52 increases, the voltage V _C at the connection point C between the collector terminal and the capacitor 52 of the right transistor of the constant current circuit 22 shown in FIG. 3 (A) Rise with a steep slope. On the other hand, the surge current generated at the time of turning on the MOS-FET 5 is superimposed on the current I _D flowing through the MOS-FET 5 as shown in FIG. 3 (B), the current I _D by the current detecting resistor 11
_{Is the} control circuit 13 as the current detection signal V _IS
Is input to the current detection signal input terminal 13b. At this time, the voltage V shown in FIG.
_A is generated and input to the inverting input terminal 51c of the comparator 51. This voltage _VA is equal to the first voltage in the comparator 51.
Is compared with the voltage V _C inputted to the first non-inverting input terminal 51a by the comparing means of FIG.
When 5 to increasing the current I _D flowing through the voltage V _A as shown in FIG. 3 (A) is lower than the voltage V _C, the high level signal is outputted from the comparator output terminal 51d of the comparator 51. The transistor 31 is turned on by this output signal, and the MOS-FET 5 is turned on from the oscillation circuit 29 via the drive circuit 30.
Figure 3 control pulse signal V _G which is granted to the gate terminal
As shown in (C), the level changes from the high level to the low level earlier than during the normal load. At this time, as shown in FIG.
The current _ID flowing through the OS-FET 5 becomes substantially zero. At the same time, the transistor 53 of the reference signal generating circuit 55 is supplied from the collector terminal of the transistor 31 via the inverting amplifier 54.
The signal applied to the base terminal of the
Is turned on, and the electric charge charged in the capacitor 52 is discharged through the transistor 53. As a result, the charging voltage of the capacitor 52 becomes substantially 0 V, so that the voltage V _{C at} the connection point C between the collector terminal of the transistor on the right side of the constant current circuit 22 of the reference signal generating circuit 55 and the capacitor 52.
Drops to about 0 V as shown in FIG.

In this embodiment, the charging current to the capacitor 52 of the reference signal generating circuit 55 in the control circuit 13 is controlled based on the feedback control signal V _FB from the output voltage detecting circuit 10, that voltage V _C of the connection point C is varied. The voltage V _{C at the} connection point C is equal to the voltage V _A generated at the connection point A between the resistors 26 and 27 by the current detection signal V _IS of the current _ID flowing through the MOS-FET 5 by the first comparison means in the comparator 51. Be compared. MOS-FET
The increase in the current I _D flowing to 5, when the voltage V _A at the connection point A becomes lower than the voltage V _C of the connection point C, the comparator 51
The comparison output signal of the first comparison means output from the comparison output terminal 51d becomes high level, and the current _ID flowing through the MOS-FET 5 becomes substantially zero. With this, MOS-FET
The maximum value of the current I _D flowing to 5 is controlled, the DC output voltage V _OUT to be supplied to the load 9 is controlled to a constant value. Therefore, the MOS-F is controlled by the charging voltage of the capacitor 52 of the reference signal generating circuit 55 which is varied according to the state of the load 9.
Since the maximum value of the current _ID flowing through the ET 5 is controlled, it is possible to prevent the malfunction of the comparator 51 in the control circuit 13 due to the surge current when the load 9 is in a light load state. On / off control of the FET 5 can be performed. If the load 9 is overloaded or the load 9 is substantially short-circuited and the feedback control signal V _FB from the output voltage detection circuit 10 is substantially 0, the resistor 23 corresponding to the limited current value of the MOS-FET 5 are compared by 24 of the connecting point the second comparison means and the voltage V _a at the connection point a of the voltage V _B and the resistor 26, 27 in the comparator 51 of the B, the current I _D flowing through the MOS-FET 5 by the comparison output signal Is limited to a constant value, it is possible to limit the current _ID flowing through the MOS-FET 5 to a constant value even when overloading or when the output is short-circuited.

The embodiments of the present invention are not limited to the above embodiments, and various modifications are possible. For example, in the above embodiment, the first and second comparators 51 are provided in the three-input comparator 51.
Although the example in which the comparing means is provided has been shown, the first and second comparing means may be each configured by a normal two-input type comparator. In the above embodiment, an example in which the present invention is applied to a flyback type DC power supply device is shown. However, the present invention is also applicable to a forward type DC power supply device. Further, in the above embodiment, an example in which a MOS-FET is used as a switching element has been described. However, another switching element such as a bipolar transistor or a junction field effect transistor (J-FET) may be used.

[0018]

According to the present invention, even when the maximum value of the current flowing through the switching element is small when the load is light, the control circuit does not malfunction due to surge current or the like. In addition, highly stable switching control is always possible. Further, even when the load is overloaded or the output is short-circuited and the feedback control signal is substantially zero, the current flowing through the switching element can be limited to a constant value. Can be minimized.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram of a DC power supply device showing an embodiment of the present invention.

FIG. 2 is a waveform diagram showing the voltage and current of each part of the circuit of FIG. 1 during normal operation, overload operation, and output short-circuit operation.

FIG. 3 is a waveform diagram showing the voltage and current of each part of the circuit of FIG. 1 under a light load.

FIG. 4 is an electric circuit diagram showing a conventional DC power supply device.

5 is an electric circuit diagram showing an internal configuration of the output voltage detection circuit shown in FIG.

FIG. 6 is a waveform chart showing voltages and currents of respective parts of the circuit of FIG. 4 in a normal state.

FIG. 7 is a waveform diagram showing the voltage and current of each part of the circuit of FIG. 4 under a light load.

[Explanation of symbols]

1,2. . . 2. DC input terminal; . . 3. input smoothing capacitor; . . Transformer, 4a. . . Primary winding,
4b. . . Secondary winding, 4c. . . 4. tertiary winding; . . M
5. OS-FET (switching element); . . Rectifier diode, 7. . . 7. output smoothing capacitor; . .
8. rectifying and smoothing circuit; . . Load, 10. . . Output voltage detection circuit (output voltage detection means), 10a, 10b. . . Output voltage input terminal, 10c. . . Detection output terminal, 1
1. . . Current detection resistor (current detection means), 1
2. . . Photocoupler, 12a. . . Light emitting unit, 12
b. . . Light receiving section, 13. . . Control circuit, 13a. . .
Feedback signal input terminal, 13b. . . Current detection signal input terminal, 13c. . . Power supply terminal, 13d. . . Control signal output terminal, 13e. . . 13. ground terminal; . . 14. starting resistor; . . Rectifying diode, 16. . .
17. smoothing capacitor; . . Control power supply circuit, 1
8. . . Capacitor for voltage resonance, 21. . . Regulator for control circuit, 22. . . Constant current circuit, 23, 2
4. . . Resistance, 25. . . Reference power supply, 26, 2
7. . . Resistance, 28. . . Comparator, 28
a. . . Non-inverting input terminal, 28b. . . Inverting input terminal,
28c. . . 29. comparison output terminal, . . Oscillation circuit,
30. . . Drive circuit; 31. . . Transistors,
32, 33. . . Resistance, 34, 35. . . Diode, 36. . . Transistor, 37. . . Comparator, 38. . . Off period setting capacitor, 3
9. . . Off period setting resistors, 41, 42. . . Resistor for voltage division, 43. . . Error amplification transistor, 4
4. . . Constant voltage diode, 45. . . Resistance, 5
1. . . 52. a comparator (comparative element); . . Capacitor, 53. . . Transistor, 54. . . Inverting amplifier, 55. . . Reference signal generation circuit,

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-317641 (JP, A) JP-A 61-185291 (JP, U) JP-A 62-159189 (JP, U) 501605 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H02M 3/28 H02M 3/335

Claims (2)

(57) [Claims] 1. A DC power supply, a transformer having a plurality of windings, a primary winding and a switching element of the transformer connected in series to both ends of the DC power supply, and a rectifying and smoothing of a secondary winding of the transformer. A load connected via a circuit, an output voltage detecting means for detecting a voltage of the load to generate a feedback control signal, and a current detecting means for detecting a current flowing through the switching element as a voltage value corresponding thereto, A control circuit that inputs a feedback control signal of the output voltage detection means and a detection signal of the current detection means and outputs an on / off control signal to be applied to a control terminal of the switching element; A DC power supply device for controlling a DC output voltage supplied to the load to a constant value by controlling ON / OFF of the switching element by an OFF control signal, wherein the control circuit A reference signal generating circuit that includes a capacitor and controls a charging current to the capacitor by inputting a feedback control signal of the output voltage detecting means to vary a charging voltage of the capacitor; and First comparing means for comparing a charging voltage value of a capacitor with a voltage value of the current detecting means, a reference power supply for generating a voltage for determining a limiting current value of the switching element,
A second comparing means for comparing a voltage value of the reference power supply with a voltage value of the current detecting means, wherein when the feedback control signal is present, the switching is performed by a comparison output signal of the first comparing means. Controlling the maximum value of the current flowing through the element to control the DC output voltage supplied to the load to a constant value, and when there is no feedback control signal of the output voltage detecting means during overload or output short circuit, A DC power supply device, wherein a current flowing through the switching element is limited to a constant value by a comparison output signal of the second comparison means. 2. The DC power supply according to claim 1, wherein said first comparing means and said second comparing means are provided in the same comparing element.