JP3187775B2 - Logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit having a sleep mode that does not supply operating power to circuit elements when it is not operating.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated logic circuit, a power supply has been designed to achieve both high speed in an active mode and low power consumption in a sleep mode. A semiconductor integrated logic circuit including a power supply circuit with a cutoff function is used.

For example, in Japanese Patent Application Laid-Open No. 06-029834, a semiconductor integrated logic circuit is constituted by low threshold transistors. As a result, the logic circuit operates at a high speed in the active state even under a low power supply voltage, and power is supplied through the high threshold transistor.

Therefore, during sleep, the power supply can be cut off by cutting off the high threshold transistor, and the subthreshold leakage current can be cut off to reduce power consumption.

Further, in a semiconductor integrated logic circuit disclosed in Japanese Patent Application Laid-Open No. 05-210976, the CM
OS (Complementary-Metal Oxide Semiconducto)
r) Power is supplied via a switch element having a device parameter such that a leakage current smaller than the sum of sub-threshold currents leaking from the logic element group flows.

FIG. 6 is a connection diagram showing a configuration example of a semiconductor integrated logic circuit 100 having such a power control circuit as in the prior art. This logic circuit 100 has a C-MOS logic element group 104 composed of logic such as a NAND circuit 102 and an inverter circuit 103.

The power supply potential _VDD is connected to the real power supply line _RVD of the C-MOS logic element group 104. Also,
The pseudo power supply line _RVV of the C-MOS logic element group 104 includes:
N-MOS transistors ₁₀₅ -1 for connected control switches in parallel with each other, ₁₀₅ -2 ~105 _-n-1,
105 is a through _-n ground potential (power supply potential _{V SS)} actual power supply line _{R VS} is connected.

The mode control signal _SLP is supplied to the inverter circuit 1
01 and each n-
It is supplied to the gate electrode of the MOS transistor ₁₀₅ -1 to 105 _-n.

The above-mentioned n-MOS transistor 105
_{-1 to} 105- _n , the C-MOS logic element group 1
Than the sum of the sub-threshold current leaking from 04, the n-MOS transistor ₁₀₅ -1 to 105
Device parameters are set such that the sum of sub-threshold currents leaking from _−n becomes small.

Here, the mode control signal _SLP is "0".
(This is an active mode), n-
MOS transistor ₁₀₅ -1 to 105 _-n are turned, the ground potential is connected directly to the C-MOS logic element group 104.

Meanwhile mode control signal when _{S LP} is that a "1" (referred to as sleep mode), n-MOS transistor ₁₀₅ -1 to 105 _-n is the cut-off state,
The C-MOS logic element group 104 is cut off from the ground potential, and the sub-threshold leakage current is suppressed.
Thus, low power consumption in the sleep mode is achieved.

[0012]

In such a configuration,
Sleep mode (that is, mode control signal _SLP is "1")
In this case, the equivalent impedance of the C-MOS logic element group 104 is higher than that of the n-MOS transistors 105 _-1 to
The equivalent impedance of 105- _n is larger. Therefore, the pseudo power supply line _RVV is charged up to the power supply potential _VDD .

[0013] On the other hand, if the active mode (i.e. the mode control signal _{S LP} is "0") into the transition, n-MOS transistor ₁₀₅ -1 to 105 _-n are rendered conductive. Thus the charge of the virtual power supply line _{R VV} until the power supply potential _{V DD} is charged is discharged to near ground potential by n-MOS transistor ₁₀₅ -1 to 105 _-n.

That is, with the switching of the mode between the sleep mode and the active mode, power is required to charge the pseudo power supply line _RVV , and all the charges are wasted when discharged.

The present invention has been made in view of such a background, and provides a logic circuit capable of reducing wasteful power consumption due to accumulation of electric charge in switching between a sleep mode and an active mode. It is an object.

[0016]

According to a first aspect of the present invention, a first power supply line (R _VD ) and a second power supply line (R _VD ) having a lower voltage than the first power supply line (R _VD ) are provided. Power line (R
_VS ) and the first switches (15a ₋₁ , 15a ₋₂ ,
, 15a- _n ) and the second power supply line ( _RVS )
A first pseudo power supply line _{(R Va)} which is connected to the second switch _{(15b -1, 15b -2, ...} , 15b -n) connected to said via a first power supply line _{(R VD)} A second pseudo power supply line (R _Vb ), and the first power supply line (R _VD ).
And the first pseudo power supply line (R _Va ) to supply drive power to the gate circuit (13a _-1 , 13a).
_-2 ,...).
a), and driving power is supplied between the second pseudo power supply line (R _Vb ) and the second power supply line (R _VS ), and the gate circuits (13b ₋₁ , 13b ₋₂ , ..) and the first logic element group (14b)
And the second pseudo power supply line (R _Va ).
_Vb ) and charge transfer means (23,
32) and the first switches (15a- ₁ , 15a).
_-2, ..., _{15a -n)} and said second switch _{(15b -1, 15b -2, ...} , 15b -n) and switching control means for controlling (31), said charge transfer means (23,
32), a transfer control means (22) for controlling the switching control means (31), a mode signal generating circuit (21), the transfer control means (22), and the charge transfer means (23), and a charge recycle circuit is activated (20) based on an instruction from the mode control circuit (24), wherein
The first switches (15a- ₁ , 15a- ₂ , ..., 15a
_-N ) leaks from the first logic element group (14a).
Is smaller than the sum of the sub-threshold currents.
Switch (15a- ₁ , 15a- ₂ , ..., 15a- _n )
The sum of the sub-threshold currents leaking from
Device parameters are set such that
Switches (15b- ₁ , 15b- ₂ , ..., 15b- _n )
Is a sub leaking from the second logic element group (14b).
The second switch is more than the sum of the threshold currents.
(15b- ₁ , 15b- ₂ , ..., 15b- _n )
The sum of the sub-threshold currents
Sea urchin device parameters are set, the charge transfer means (32), said first switch _(15a -1, 15a
_-2 , ..., 15a- _n )
A transfer control signal S _EQ is input to a gate electrode of the third switch (35) set to such device parameters, and the third switch (35) has a gate electrode connected between the source electrode and the drain electrode. The first pseudo power supply line (R
_Va ) _-the second switch (15a- ₁ , 15a- ₂ , 15a- ₂ ) connected between the second pseudo power supply line ( _RVb ).
, 15a- _n ) and the second switch (15b- ₁ ,
15b- ₂ ,..., 15b- _n ), the first logic element group (14a), and the second logic element group (14b) each include a MOS transistor, and in the sleep mode, the first switch. (15a- ₁ and 15a
_-2, ..., _{15a -n)} impedance of the first higher than the impedance of the logic element group (14a) and said second switch _{(15b -1, 15b -2, ...} , 15
b− _n ) is the impedance of the second logic element group (1).
4b), the power supply potential (V _DD ) is connected to the first power supply line (R _VD ) of the first logic element group (14a), and the first pseudo power supply line (R _Va ) includes the first switches (15a ₋₁ , 15a ₋₁₎ for control switches connected in parallel with each other.
a− ₂ ,..., 15a− _n ) via the power supply potential ( _VSS ).
Is connected to the second pseudo power supply line (R _VS ) of the second logic element group (14b).
_Vb ), the second switches (15b- ₁ , 15b- ₂ ,..., 15b) for the control switches connected in parallel to each other.
b− _n ), the power supply potential (V _DD ) is connected,
The second power supply line (R _VS ) is connected to a power supply potential ( _VSS ).
And the switching control means (31) is connected to the second
Connected between the pseudo power supply line (R _Vb ) and the first switch.
H (15a- ₁ , 15a- ₂ , ..., 15a- _n )
Device parameters that leak small current
C-MOS inverter circuits (31a, 31
b, 31c), and the mode signal generation circuit (21) includes a control signal (C) of the transfer control means (22).
tl21), the first switch (15a
_-1 , 15a _-2 ,..., 15a- _n ) are output to the signal distribution line (16a) and a response signal ( _Res21 ) is _transmitted to the transfer control means (2).
2), and the transfer control means (22) returns to the first
When the logic element group (14a) and the second logic element group (14b) transition from the sleep mode to the active mode, the potential of the first pseudo power supply line (R _Va ) and the second pseudo power supply line Until the potential of (R _Vb ) becomes substantially equal to the potential between the first pseudo power supply line (R _Va ) and the second pseudo power supply line (R _Vb ) by the charge transfer means (23, 32). To transfer the electric charge, and the potential of the first pseudo power supply line ( _RVa ) and the second pseudo power supply line ( _RVb ).
, 15a- ₁ , 15a- ₂ , ..., 15a- _n and the second switches (15b- ₁ , 15b- ₂ , ..., 15)
b _−n ) to an on state, the first logic element group (14a) and the second logic element group (1
4b) at the time of transition from the active mode to the sleep mode, the first switches (15a- ₁ and 15a)
_-2, ..., _{15a -n)} and said second switch (1
5b _-1 , 15b _-2 ,..., 15b _-n ), and thereafter, the potential of the first pseudo power supply line (R _Va ) and the potential of the second pseudo power supply line (R _Vb ) are substantially equal. and transferring charge between said charge transfer means (23, 32) by the first pseudo power supply line to the same potential (R _Va) with the second pseudo power supply line (R _Vb), re the charge Use circuit
(20a) is composed of the switching control means (31) and the charge transfer means (32), and includes a mode control signal (S
_LP ) and a transfer control signal (S _EQ ), and the charge transfer circuit (23) controls the charge transfer path (17a) and the charge based on the control signal (C _tl22 ) of the transfer control means (22). Charge is transferred between the first pseudo power supply line (R _Va ) and the second pseudo power supply line (R _Vb ) via a transfer path (17b), and a response signal (R
The _Es22) reply to the transfer control means (22), wherein
The transfer control means (22) includes a mode control circuit (24)
The operation in the charge recycling circuit (20) is controlled based on the control signal (C _tl24 ) of the
The _{ES 24)} returns to the mode control circuit (24), connected between said second pseudo power supply line _{(R Vb)} wherein in
The barter circuit (31a) receives the mode control signal (S _LP ) as an input, outputs a signal to the signal distribution line (16a), and also connects the second pseudo power supply line (R _Vb ) connected in series. And an inverter circuit (31
b) and the second pseudo power supply line (R _Vb ),
The inverter circuit (31c) includes a mode control signal S _LP
, And outputs a signal to the signal distribution line (16b).

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below. FIG. 1 is a block diagram showing a configuration of a logic circuit according to one embodiment of the present invention. Logic circuit 1 shown in FIG.
0, the gate circuit _13a -1, _{13a -2,} and C-MOS logic element group 14a consisting of ... etc., the gate circuit 1
C-MOS composed of 3b- ₁ , 13b- ₂ ,...
And a logic element group 14b.

The actual power supply line R of the C-MOS logic element group 14a
_The power supply potential _VDD is connected to _VD , and the pseudo power supply line R
_Va has n- for control switches connected in parallel with each other.
MOS transistors 15a- ₁ , 15a- ₂ , ..., 15
actual power supply line _{R VS} via a _-n is the ground potential (power supply potential _{V SS)} is connected.

[0019] p for C-MOS logic element control switch connected in parallel with each other in the virtual power supply line _{R Vb} of group 14b
-MOS transistors 15b- ₁ , 15b- ₂ , ..., 1
Is connected to the power supply potential _{V DD} via 5b _-m, also actual power supply line _{R VS} is connected to a ground potential (power supply potential _{V SS).}

The charge recycling circuit 20 included in the logic circuit 10
Is composed of a mode signal generation circuit 21, a transfer control circuit 22, and a charge transfer circuit 23.
4 is started based on an instruction from the user.

The mode signal generating circuit 21 is _adapted to _generate an n-MOS based on a control signal _{Ctl21 from the} transfer control circuit 22.
A signal for controlling the conduction and interruption of the transistors 15a- _{1 to} 15a _{- n} is output to the signal distribution line 16a, and a response signal _Res21 is _returned to the transfer control circuit 22.

The charge transfer circuit 23 transfers charge between the control signal _C the virtual power supply line through the charge transfer paths 17a and 17b on the basis of the _{TL22 R Va} and the virtual power supply line _{R Vb} of the transfer control circuit 22, In addition, it _{returns a} response signal _Res22 to the transfer control circuit 22.

The transfer control circuit 22 includes a mode control circuit 24
The control in the charge recycling circuit 20 is controlled based on the control signal _Ctl24 of the above, and a response signal _Res24 is _returned to the mode control circuit 24.

The above-described n-MOS transistor 15a
_{-1 to} 15a- _n , the C-MOS logic element group 1
4a, the sum of the sub-threshold currents leaking from n-MOS transistors 15a- _{1 to} 15a
_The device parameters are set such that the sum of the sub-threshold currents leaking from _−n becomes smaller.

Similarly, p-MOS transistor 15b _-1
15b- _m , the C-MOS logic element group 14b
The device parameters are set such that the sum of the sub-threshold currents leaking from the p-MOS transistors 15b- _{1 to} 15b _{- m} is smaller than the sum of the sub-threshold currents leaking from the P-MOS transistors.

FIG . 2 is a flowchart showing the flow of a control operation when the mode is changed from the sleep mode to the active mode in the present embodiment. Here, the description will be made assuming that the present embodiment is currently in the sleep mode.

In the sleep mode, since the signal output from the mode signal generating circuit 21 via the signal distribution line 16a has a low potential, the n-MOS transistor 15a
_{-1 to} 15a- _n are all in the cutoff state.

Further, the n-MOS transistor 15a _-1 exceeds the total impedance of the C-MOS logic element group 14a.
Since the higher the total impedance to 15A _-n, the potential of the virtual power supply line _{R Va} is charged to the power supply potential _{V DD,} and has a high potential state.

On the other hand, the mode signal generating circuit 21 signals that will be outputted through the signal distribution line 16b from being turned since the high potential, and also all p-MOS transistor _15b -1 _{~15b -m} off.

Therefore, the p-MOS transistor 15b is larger than the total impedance of the C-MOS logic element group 14b.
_Since the total impedance of _{-1 to} 15b- _m is higher,
The potential of the pseudo power supply line R _Vb is discharged to the ground potential ( _VSS ) and is in a low potential state.

In this embodiment, first, the mode control circuit 2
4 outputs a control signal C _tl24 to the charge recycling circuit 20, and switches from the sleep mode to the active mode (step Sa1).

This control signal _Ctl24 is transmitted to the transfer control circuit 22 constituting the charge recycling circuit 20, whereby the charge of the power supply circuit is reused at the time of the mode transition from the sleep mode to the active mode.

Next, the transfer control circuit 22 responds to the mode switching command from the sleep mode to the active mode.
Outputs a control signal _Ctl22 to the charge transfer circuit 23, whereby charges are transferred (step Sa).
2).

That is, the charge of the pseudo power supply line _RVa charged to the power supply potential _VDD is transferred by the charge transfer circuit 23 to the pseudo power supply line _RVb via the charge transfer paths 17a and 17b. As a result, the potential of the pseudo power supply line _RVb discharged to the ground potential increases.

This charge transfer ends when the potential of the pseudo power supply line R _{Vb and} the potential of the pseudo power supply line R _Va are substantially equal. At this time, the potential of the pseudo power supply line R _Vb is changed to the power supply potential V.
_DD , and the potential of the pseudo power supply line _RVa is higher than the ground potential.

The charge transfer circuit 23 monitors the charge transfer state (step Sa3), and when the potential of the pseudo power supply line R _{Vb and} the potential of the pseudo power supply line R _Va are substantially equal, a response signal notifying that the charge transfer has been completed. _Res22 is transmitted to the transfer control circuit 22 (step Sa4).

_Upon receiving the response signal _Res22 , the transfer control circuit 22 transmits the control signal _Ctl21 to the mode signal generation circuit 21.
And the mode signal generating circuit 21 outputs a high-potential signal to the signal distribution line 16a.
A low potential signal is output to b (step Sa5).

Since the signal distribution line 16a has a high potential and the signal distribution line 16b has a low potential, all of the n-MOS transistors 15a- _{1 to} 15a _{- n} and the p-MOS transistors 15b- _{1 to} 15b _{- m} are changed. It becomes conductive.

As a result, the pseudo power supply line R _Vb is completely charged to the power supply potential V _DD , while the pseudo power supply line R _Va is completely discharged to the ground potential and transits to the active mode. The mode signal generating circuit 21 provides a response signal notifying that the transition processing to the active mode has been completed after a lapse of a predetermined time (step Sa6) since the signal distribution line 16a has become high potential and the signal distribution line 16b has become low potential. R
_es21 is transmitted to the transfer control circuit 22 (step S
a7).

The response signal R _ES21 the received transfer control circuit 22, a response signal R _{ES 24} sends to the mode control circuit 24 notifies the switching from the sleep mode to the active mode charge transfer process is completed is completed (Step Sa8). With this, the process of charge reuse of the power supply circuit related to the transition from the sleep mode to the active mode ends.

FIG . 3 is a flowchart showing a control operation flow when the mode is changed from the active mode to the sleep mode in the present embodiment. Here, the description will be made assuming that the present embodiment is currently in the active mode.

In the active mode, since the signal output from the mode signal generating circuit 21 via the signal distribution line 16a is at a high potential, the n-MOS transistor 15
a- _{1 to} 15a- _n are all in the ON state.

The n-MOS transistor 15a _{-1 is} more than the total impedance of the C-MOS logic element group 14a.
Since towards the total impedance to 15A _-n is high, the potential of the virtual power supply line _{R Va} is discharged to the ground potential _{(V SS),} and has a low potential state.

On the other hand, the mode signal generating circuit 21 signals that will be outputted through the signal distribution line 16b from being turned due to low potential, and all even p-MOS transistor _15b -1 _{~15b -m} ON state.

Therefore, the p-MOS transistor 15b exceeds the total impedance of the C-MOS logic element group 14b.
_Since the total impedance of _{-1 to} 15b- _m is higher,
The potential of the pseudo power supply line R _Vb is charged to the power supply potential V _DD and is in a high potential state.

In this embodiment, first, the mode control circuit 2
4 outputs a control signal C _tl24 to the charge recycling circuit 20, and switches from the active mode to the sleep mode (step Sb1).

The control signal _Ctl24 is transmitted to the transfer control circuit 22 constituting the charge recycling circuit 20, whereby the charge of the power supply circuit is reused at the time of the mode transition from the active mode to the sleep mode.

Next, in response to the mode switching command from the active mode to the sleep mode, the control circuit 22
The control signal C _tl21 is _sent to the mode signal generation circuit 21.

As a result, the mode signal generating circuit 21
A low-potential signal is output to the signal distribution line 16a, and a high-potential signal is output to the signal distribution line 16b (step Sb).
2).

Since the signal distribution line 16a has a low potential and the signal distribution line 16b has a high potential, all of the n-MOS transistors 15a- _{1 to} 15a _{- n} and the p-MOS transistors 15b- _{1 to} 15b _{- m} are changed. It turns off.

The mode signal generating circuit 21 includes the signal distribution line 1
After a lapse of a predetermined period of time (step Sb3) since the low potential of the signal supply line 6a and the high potential of the signal distribution line 16b have been reached, a response signal R indicating that the transition processing to the sleep mode has been completed.
_es21 is transmitted to the transfer control circuit 22 (step S
b4).

_Upon receiving the response signal _Res21 , the transfer control circuit 22 outputs a control signal _Ctl22 to the charge transfer circuit 23, whereby charges are transferred (step Sb).
5).

That is, the charge of the pseudo power supply line R _Vb charged to the power supply potential V _DD is transferred by the charge transfer circuit 23 to the pseudo power supply line R _Vb via the charge transfer paths 17a and 17b. As a result, the potential of the pseudo power supply line _RVa discharged to the ground potential increases.

This charge transfer ends when the potential of the pseudo power supply line R _{Vb and} the potential of the pseudo power supply line R _Va are substantially equal. At this time, the potential of the pseudo power supply line R _Vb is set to the power supply potential V.
_DD , and the potential of the pseudo power supply line _RVa is higher than the ground potential.

The charge transfer circuit 23 monitors the charge transfer state (step Sb6), and when the potential of the pseudo power supply line R _Vb is substantially equal to the potential of the pseudo power supply line R _Va , a response signal indicating that the charge transfer has been completed. _Res22 is transmitted to the transfer control circuit 22 (step Sb7).

_Upon receiving the response signal _Res22 , the transfer control circuit 22 sends the response signal _Res24 to the mode control circuit 24 to _notify that the charge transfer process has been completed and the switching from the active mode to the sleep mode has been completed. (Step Sb8). With this, the charge recycling process of the power supply circuit related to the transition from the active mode to the sleep mode ends.

FIG. 4 shows an application example of the logic circuit of the present invention, and is a connection diagram showing a detailed configuration example. FIG. 4
In FIG. 7, the same reference numerals are given to the portions corresponding to the respective portions shown in FIG.

The charge recycling circuit 20a includes the mode control unit 3
1 and the charge transfer circuit 32, and are controlled based on the mode control signal _SLP and the transfer control signal _SEQ . The mode control unit 31 is a C-MOS inverter set to a device parameter having a smaller leakage current.
It is composed of circuits 31a , 31b and 31c.

The inverter circuit 31a receives the mode control signal _SLP as an input and outputs a signal to the signal distribution line 16a. Further, the inverter circuit 31b and the inverter circuit 31c connected in series receive the mode control signal _SLP as an input and output a signal to the signal distribution line 16b.

The charge transfer circuit 32 is, for example, an n-MO set to a device parameter having a smaller leakage current.
It is composed of an S transistor 35 and the like. This n-M
The transfer control signal S is applied to the gate electrode of the OS transistor 35.
_EQ is input, the source electrode - drain electrode, the virtual power supply line R _{Va -} is connected between the virtual power supply line R _Vb.

FIG. 5 is a timing chart showing how signals or potentials change in each section of the configuration shown in FIG. First, a case where the power supply circuit 10a makes a transition from the sleep mode to the active mode will be described with reference to these drawings.

In the sleep mode, the mode control signal _SLP is at a high potential, a low potential signal is supplied from the mode control unit 31 to the signal distribution line 16a, and the n-MOS
The transistors 15a- _{1 to} 15a _{- n} are all in a cutoff state.

As described above, the C-MOS logic element group 1
Since the higher the total impedance of the n-MOS transistor _15a -1 to 15A _-n than the total impedance of 4a, the virtual power supply line _{R Va} has a high potential is charged to the power supply potential _{V DD.}

On the other hand, at this time, a high potential signal is supplied from the mode control unit 31 to the signal distribution line 16b, and all the p-MOS transistors 15b- _{1 to} 15b _{- m} are in a cutoff state. In this case, the p-MOS transistor 15b also exceeds the total impedance of the C-MOS logic element group 14b.
_Since the total impedance of _{-1 to} 15b- _m is higher,
The pseudo power supply line _RVb is discharged to the ground potential and becomes a low potential.

[0065] At time _{T m1} to initiate the transition to the active mode from the sleep mode, enter the transfer control signal _{S EQ} with rising width of a predetermined time _{t EQ,} intermittently conducting the n-MOS transistor 35 State.

As a result, the electric charge of the pseudo power supply line R _Va charged to the power supply potential _{VDD is} transferred to the pseudo power supply line R _Vb via the charge transfer circuit 32. At this time, the potential of the pseudo power supply line R _Vb rises from the ground potential.

The above-mentioned predetermined time t _EQ sets in advance the time required from the rising of the transfer control signal S _EQ until the potential of the pseudo power supply line R _{Va and} the potential of the pseudo power supply line R _Vb become substantially equal. .

[0068] The transfer control signal _{S EQ} falls time T _m2 is thus the potential of the virtual power supply line _{R Va} power supply potential V
_{DD, and} the potential of the pseudo power supply line _RVb is higher than the ground potential.

[0069] After thus the potential of the potential and the virtual power supply line _{R Vb} pseudo power supply line _{R Va} becomes substantially equal, the time T _m3
At the same time, the mode control signal _SLP is changed from the high potential to the low potential. Accordingly, the mode control unit 31 outputs a high-potential signal to the signal distribution line 16a and a low-potential signal to the signal distribution line 16b. here,
The potential of the pseudo power supply line R _Va drops to the ground potential, while the potential of the pseudo power supply line R _Vb rises to the power supply potential V _DD and transitions to a completely active mode.

Next, a case where the power supply circuit 10a transitions from the active mode to the sleep mode will be described. In the active mode, the mode control signal _SLP is at a low potential, and the mode control unit 31 sends the signal distribution line 1
A high-potential signal is supplied to 6a, and the n-MOS transistors 15a- _{1 to} 15a _{- n} are all conducting.

As described above, the C-MOS logic element group 1
Since the higher the total impedance of the n-MOS transistor _15a -1 to 15A _-n than the total impedance of the 4a, the virtual power supply line _{R Va} has become lower potential is discharged to the ground potential.

On the other hand, at this time, a low potential signal is supplied from the mode control unit 31 to the signal distribution line 16b, and all the p-MOS transistors 15b- _{1 to} 15b _{- m} are in a conductive state. In this case, the p-MOS transistor 15b also exceeds the total impedance of the C-MOS logic element group 14b.
_Since the total impedance of _{-1 to} 15b- _m is higher,
The pseudo power supply line R _Vb is charged to the power supply potential V _DD and has a high potential.

At time _Tm4 , to start the transition from the active mode to the sleep mode, the mode control signal _SLP is changed from the low potential to the high potential. Thus, the mode control unit 31 outputs a low-potential signal to the signal distribution line 16a and a high-potential signal to the signal distribution line 16b.

Thereafter, at time _Tm5 , a predetermined time t
_The transfer control signal S _EQ having the rising width of the _EQ is input, and the n-MOS transistor 35 is intermittently turned on. As a result, the charges of the pseudo power supply line R _Vb charged to the power supply potential V _DD are transferred to the pseudo power supply line R _Va via the charge transfer circuit 32. At this time, the pseudo power supply line R _Va
Rise from the ground potential.

The above-mentioned predetermined time t _EQ sets in advance the time required from the rising of the transfer control signal S _EQ until the potential of the pseudo power supply line R _{Va and} the potential of the pseudo power supply line R _Vb become substantially equal. .

[0076] At time T _m6 to transfer control signal _{S EQ} falls in this way, the potential of the virtual power supply line _{R Va} is higher than the ground potential, and the potential of the virtual power supply line _{R Va} power supply potential V
_The state is lower than _DD .

Thereafter, the electric charge of pseudo power supply line R _{Vb is} gradually discharged, and the potential drops to the ground potential. On the other hand, the electric charge of pseudo power supply line R _Va is gradually charged, and the electric potential becomes the power supply potential V.
_It rises to _DD and transits to a complete sleep mode.

[0078]

As described above, according to the present invention, the first power supply line, the second power supply line having a voltage lower than that of the first power supply line, and the second power supply line via the first switch. A first pseudo power supply line connected to the second power supply line, a second pseudo power supply line connected to the first power supply line via a second switch, the first pseudo power supply line, and the second pseudo power supply line. A first logic element group connected between the first logic power supply line and a driving power supply;
A second logic element group connected between the second pseudo power supply line and the second power supply line and supplied with driving power; the first pseudo power supply line and the second pseudo power supply line Charge transfer means for transferring charges between the first and second switches, switching control means for controlling the first switch and the second switch, and transfer control means for controlling the charge transfer means and the switching control means. In the logic circuit, the transfer control means includes:
When the first logic element group and the second logic element group transition from the sleep mode to the active mode, the potential of the first pseudo power supply line and the potential of the second pseudo power supply line are substantially equal. The electric charge is transferred between the first pseudo power supply line and the second pseudo power supply line by the charge transfer means until the potential of the first pseudo power supply line and the potential of the second pseudo power supply line become higher. Turning on the first switch and the second switch after the potential and the potential become substantially the same potential,
On the other hand, at the time of transition from the active mode to the sleep mode of the first logic element group and the second logic element group, after turning off the first switch and the second switch, the first pseudo The electric charge transfer means transfers electric charges between the first pseudo power supply line and the second pseudo power supply line until the electric potential of the power supply line and the electric potential of the second pseudo power supply line become substantially equal. . The present invention has been made under such a background, and has an effect that it is possible to realize a logic circuit that can reduce wastefully consumed power due to accumulation of electric charges in switching between a sleep mode and an active mode. Is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a logic circuit according to one embodiment of the present invention.

FIG. 2 is a flowchart showing a flow of a control operation when the mode is changed from a sleep mode to an active mode in the embodiment.

FIG. 3 is a flowchart showing a flow of a control operation when the mode is shifted from an active mode to a sleep mode in the embodiment.

FIG. 4 is a connection diagram showing an application example of the logic circuit of the present invention and showing a detailed configuration example.

FIG. 5 is a timing chart showing a state of a change in a signal or a potential in each unit having the configuration shown in FIG. 4;

FIG. 6 is a connection diagram illustrating a configuration example of a semiconductor integrated logic circuit including a power control circuit according to the related art.

[Explanation of symbols]

10 logic circuit 10a power supply circuit 13a- ₁ , 13a- ₂ , ..., 13a- _n gate circuit 13b- ₁ , 13b- ₂ , ..., 13b- _m gate circuit 14a C-MOS logic element group (first logic element group ) 14b C-MOS logic element group (second logic element group) 15a- ₁ , 15a- ₂ , ..., 15a- _nn -MOS
Transistors (first switches) 15b- ₁ , 15b- ₂ , ..., 15b _{- mp} -MOS
Transistors (second switches) 16a , 16b Signal distribution lines 17a , 17b Charge transfer paths 20 Charge recycling circuits 21 Mode signal generation circuits 22 Transfer control circuits (transfer control means) 23 , 32 Charge transfer circuits (charge transfer means) 24 Mode control circuit 31 Mode control section (switch control means) 31a , 31b , 31c Inverter circuit 35 n-MOS transistor (third switch) 100 Logic circuit 101 Inverter circuit 102 NAND circuit 103 Inverter circuit 104 C-MOS logic element group 105 _{-1, 105 -2, ..., 105} -n n-MOS
Transistor _Ctl21 , _Ctl22 , _Ctl24 Control signal _Res21 , _Res22 , _Res24 response signal R _Va pseudo power supply line (first pseudo power supply line) R _Vb pseudo power supply line (second pseudo power supply line) R _VD real Power supply line (first power supply line) R _VS actual power supply line (second power supply line) R _VV pseudo power supply line S _LP mode control signal V _DD power supply potential

Claims (1)

(57) [Claims] 1. A first power supply line (R _VD ), a second power supply line (R _VS ) having a lower voltage than the first power supply line (R _VD ), and a first switch (15a ₋₁ , 15a- ₂ , ..., 15a
_-N ), a first pseudo power supply line (R _Va ) connected to the second power supply line (R _VS ), and a second switch (15b- ₁ , 15b- ₂ , ..., 15b).
Via said _-n) first power supply line _(second pseudo power supply line connected to the _{R VD)} and _{(R Vb),} said first power supply line _{(R VD)} and said first pseudo power supply line (R _Va ), a driving power is supplied thereto, and a first logic element group (14a) including gate circuits (13a- ₁ , 13a- ₂ ,...); _Are connected between the pseudo power supply line (R _Vb ) and the second power supply line (R _VS ) to supply drive power, and include gate circuits (13b- ₁ , 13b- ₂ ,...). A second logic element group (14b), and charge transfer means (23, 32) for transferring charges between the first pseudo power supply line (R _Va ) and the second pseudo power supply line (R _Vb ). ) And the first switch (15a- ₁ , 15a- ₂ ,..., 1)
5a _−n ) and the second switch (15b ₋₁ ,
15b ₋₂ ,..., 15b _−n ); transfer control means (22) for controlling the charge transfer means (23, 32) and the switch control means (31); A mode signal generating circuit (21) and the transfer control means (2);
2) a charge recycling circuit (20) which is constituted by the charge transfer means (23) and is activated based on an instruction from a mode control circuit (24); and the first switch (15a- ₁₎ , 15a- ₂ , ..., 1
5a- _n ) leaks from the first logic element group (14a).
Than the sum of the sub-threshold currents leaking,
Switches (15a- ₁ , 15a- ₂ , ..., 15)
a _−n ) of the sum of the sub-threshold currents leaking from
The device parameters are set such that the second switch (15b ₋₁ , 15b ₋₂ ,..., 1)
5b- _n ) leaks from the second logic element group (14b).
Than the sum of the sub-threshold currents leaking,
Switches (15b- ₁ , 15b- ₂ , ..., 15)
b− _n ) of the sum of the sub-threshold currents leaking from
The device parameters are set so that the first switch (1 ) is smaller than the first switch (1).
5a- ₁ , 15a- ₂ , ..., 15a- _n )
A third switch (35) set to a device parameter that leaks a large current, a transfer control signal S _EQ is input to a gate electrode of the third switch (35), and a source electrode-drain The electrodes are connected between the first pseudo power supply line ( _RVa ) and the second pseudo power supply line ( _RVb ), and the first switches (15a- ₁ , 15a- ₂ ,..., 1)
5a- _n ) and the second switches (15b- ₁ , 15b- ₁₎ .
_-2, ..., _{15b -n),} the first logic element group (14
a) and the second logic element group (14b) are each M
In the sleep mode, the first switches (15a- ₁ , 15a- ₂ , 15a- ₂ ,
, 15a- _n ) are higher than the impedance of the first logic element group (14a) and the second
Switches (15b- ₁ , 15b- ₂ , ..., 15)
b− _n ) is the impedance of the second logic element group (1).
4b), the power supply potential (V _DD ) is connected to the first power supply line (R _VD ) of the first logic element group (14a), and the first pseudo power supply line (R _Va ) has the first switch (15) for the control switch connected in parallel with each other.
a- ₁ , 15a _-2 ,..., 15a- _n ), the second power supply line (R _VS ), which is the power supply potential ( _VSS ), is connected to the second logic element group (14b). The second pseudo power supply line (R _Vb ) is connected to the second switches (15b ₋₁ , 15b ₋₂ , 15b ₋₂ , 15b ₋₂ ,
, 15b- _n ) are connected to the power supply potential (V _DD ), and the second power supply line (R _VS ) is connected to the power supply potential (R _VS ).
( _VSS ) , and the switching control means (31) is connected to the second pseudo power supply line.
(R _Vb ) and the first switch (15a
_{-1, 15a -2, ..., 15a} -n) and equally small Sana electrostatic
C set to a device parameter that leaks flow
-MOS inverter circuits (31a, 31b, 31c)
The mode signal generation circuit (21) is configured to control the first switches (15a- ₁ , 15a- ₂ ,..., 15a) based on a control signal (Ctl21) of the transfer control means (22).
_-N ) is transmitted to the signal distribution line (16).
a) and _returns a response signal ( _Res21 ) to the transfer control means (22). The transfer control means (22) transmits the first logic element group (14a) and the second logic When the element group (14b) transitions from the sleep mode to the active mode, the potential of the first pseudo power supply line (R _Va ) and the potential of the second
The first pseudo power supply line (R _Va ) and the second pseudo power supply line (R _Vb ) by the charge transfer means (23, 32) until the potential of the pseudo power supply line (R _Vb ) becomes substantially the same as the potential of the pseudo power supply line (R _Vb). )
And the first switch is switched after the potential of the first pseudo power supply line (R _Va ) and the potential of the second pseudo power supply line (R _Vb ) become substantially equal. (1
5a- ₁ , 15a- ₂ , ..., 15a- _n ) and the second switch (15b- ₁ , 15b- ₂ , ..., 15b).
_-N ) to an on state, and the first logic element group (14a) and the second logic element group (14a).
In the transition from the active mode to the sleep mode in b), the first switches (15a _-1 , 15a)
_{a -2,} ..., _{15a -n)} and said second switch _{(15b -1, 15b -2, ...} , after the _{15b -n)} off, the potential of the first pseudo power supply line _{(R Va)} The first pseudo power supply line (R _Va ) and the second pseudo power supply by the charge transfer means (23, 32) until the potential of the second pseudo power supply line (R _Vb ) becomes substantially the same as the potential of the second pseudo power supply line (R _Vb ). Line (R
To transfer charge between the _Vb), said charge recycle circuit (20a), said consist switching control means (31) and said charge transfer means (32), the mode control signal _{(S LP)} and transfer control Signal (S
_EQ ), and the charge transfer circuit (23) controls the transfer control means (2).
2) Based on the control signal (C _tl22 ), the first pseudo power supply line (R _Va ) and the second pseudo power supply line (R _Va ) via the charge transfer path (17a) and the charge transfer path (17b).
_Vb ) and the response signal (R
_es22 ) is returned to the transfer control means (22), and the transfer control means (22)
4) controlling the operation in the charge recycling circuit (20) based on the control signal (C _tl24 ), and _returning a response signal ( _Res24 ) to the mode control circuit (24); The above-mentioned a connected between the pseudo power supply lines (R _Vb ).
The inverter circuit (31a) receives the mode control signal (S
_LP ) as an input and outputs a signal to the signal distribution line (16a), and is connected between the second pseudo power supply lines (R _Vb ) connected in series to form an inverter circuit (31b).
And the second pseudo power supply line (R _Vb ), and the inverter circuit (31c) receives a mode control signal S _LP as an input and outputs a signal to the signal distribution line (16b). Logic circuit.