JP3186905B2 - Dual-endian firmware system for computer boot - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to computer systems, and more particularly to different byte orders (b).
This is related to the technology for constructing computer systems in yte order.

[0002]

2. Description of the Related Art Computer systems can be divided into two types of byte order: big-endian and little-endian. The big-endian machine expresses a numerical value in the order of the 0th to 3rd bytes in one word (32 bits) (and in the case of a 64-bit one word, in the order of the 0th to 7th bytes), Has a sign bit and a most significant bit. Half a word (16
), The big endian machine represents the numerical value with the 0th and 1st bytes, and the 0th byte has a sign bit and the most significant bit. In a little endian machine, one word represents a numerical value in the order of the third to zeroth bytes. The third byte has a sign bit and a most significant bit. Half a word (1
(6 bits), the little endian machine represents a numerical value with the 0th and 1st bytes, and the 1st byte has a sign bit and the most significant bit. Computer system CP
The byte order (endianness) of the U, firmware and I / O (input / output) systems dictates the type of operating system or binary code (binary code) that can execute the system.

[0003] Computer systems are usually manufactured in a specific byte order that cannot be changed by the end user. Although manufacturers have designed components such as CPUs and I / O controllers to be configurable to operate in either byte ordering scheme, firmware is usually one or the other. Thus, components that can be adapted in both byte order are usually statically fixed by the manufacturer to operate in the same byte order as the computer firmware.

[0004]

Unfortunately, some manufacturers' standard operating systems are big-endian and others are little-endian. In general, it is possible to recompile or rewrite software to change the byte order, but the firmware is fixed in the ROM in a specific byte order. Thus, despite the compatibility of the hardware components, Microsoft NT operating system (little endian) and MIPS RIS
Users who want to run programs under the C / OS operating system (big endian)
You have to make physical adjustments to the hardware if you can, or sometimes buy two machines.

[0005]

SUMMARY OF THE INVENTION The present invention, in summary, relates to a computer firmware byte order that allows an end user to install software created in big endian or little endian byte order under software control. . The system allows users to update firmware and change byte order at boot time without having to make physical adjustments to the hardware.

In short, a system embodying the present invention includes a first non-volatile memory that stores a program called base firmware, which is located at a start address. The base firmware is created in the first byte order (little endian in the embodiment). When the power is turned on, the CPU and the I / O system are set by default in the first byte order, and the CPU executes the base firmware. The system according to the invention also includes a second non-volatile (but preferably writable) memory storing a program called boot firmware which can be in either byte order. The second memory also stores a signature identifying the byte order of the boot firmware.

[0007] The system also includes reconfigurable circuitry operable to change the byte order configuration of the hardware as required by the boot firmware in response to instructions in the base firmware. However, such a change is only possible with a subsequent reset. In particular, if necessary, the circuitry configures the CPU byte order and relocates the memory.
As a result, the CPU resets the boot firmware
Assuming the byte order specified by the hardware signature
The CPU starts executing the boot firmware. Operation
In operation, the base firmware controls the reconfigurable electronics and then resets the system. I / O
The byte order of the system is similar to the byte order of the CPU.
Either configuration, or it is so configured under program control by the boot firmware after the reset
Can also .

In a preferred embodiment, the second memory is writable (eg, a flash EEPROM) and upon power up, the base firmware informs the user of the C
The PU can be instructed to select firmware to be written to the second memory before instructing the reconfiguration electronics. In this way, a user trying to boot up a particular operating system can be identified as such from the keyboard, leaving the confidence that the hardware, firmware and software will go on the same track. Can be.

The nature and advantages of the present invention may be better understood with reference to the following description and drawings of the specification.

[0010]

FIG. 1 is a block diagram of a computer system 10 embodying the present invention. The system is 3
It is believed to include two main components: a CPU subsystem, a memory subsystem, and an I / O subsystem. Memory control / DMA (direct memory acc)
ess) The chipset 12 controls the data paths and addressing between subsystems and includes the following (not specifically shown): processor interface memory interface, video interface, I / O translation table And cache,
It includes an EISA bus interface, an i486 compatible master / slave interface, and eight slave DMA channels.

The CPU subsystem is a MIP in the embodiment.
CPU15 which is SR4000 RISC processor
And writable read only memories (PROMs) 17 and 18 in first and second serial configurations. Each serial PROM stores system interface device configuration information including byte order information that can communicate with the CPU at the start. Serial PROM 17 provides device configuration information for the big endian system, while serial PR
The OM 18 provides device configuration information for the little endian system. The specified relationship between big endian and little endian is for describing the embodiment. At any time at the start, only one series PR
The OM is allowed to exchange information with the CPU. When the power is turned on, the default is the serial PR because the processor is initially configured in little endian mode.
This is the selection of OM18.

The memory subsystem is a system memory 20.
And a video memory 22, which are standard as far as the present invention is concerned. The I / O subsystem, which is located on the memory, includes a group of standard and unspecified peripheral controllers and peripherals 25. However, the pair of PROM devices 30 and 32 and the reset control circuitry 35 and PROM control circuitry 37 are relevant to the present invention and are described below.

The PROM devices 30 and 32 contain system firmware for booting the operating system. In the prior art, a single device,
Typically, there was only a 128 kilobit or 256 kilobit system PROM that dictated most of the low-level interaction with the hardware. In accordance with the present invention, as described below, the boot process takes place in two stages, referred to as Phase 0 and Phase 1, and PROM 30 stores what is referred to as base firmware or Phase 0 firmware. The PROM 32 stores what is called boot firmware or phase 1 firmware. In the embodiment, the PROM 30 is a 64 kilobit EPRO whose contents cannot be rewritten during operation.
The PROM 32 is an instantaneous erase rewritable memory (flash EEPROM) that can be rewritten by another firmware selection instruction. An additional step, called Phase 2, refers to the state in which the operating system has been once loaded (reading the program from the input / output medium or the auxiliary storage into the internal storage) and has started executing.

FIG. 2 shows the writing of the flash EEPROM, the byte order after reset, the base PROM and the boot P.
FIG. 4 is an enlarged block diagram illustrating a group of registers used to control ROM mapping, memory / DMA byte order, and forced reset of the system. The actual execution support logic is PLA (programmable logic arrays).

The serial PROM control circuit 40 has a CPU EB
And CPU It includes a pair of registers called EL, which control a multiplexer 42 to select data from either of the serial PROMs 17 and 18 (both are enabled).

CPU The EB register is set to 0 regardless of whether it is little endian or big endian.
It is located at the double word address of x8000D100.
When something is written to this register, this register is set to 1 and the big endian serial PROM 17
Select CPU EB register is CPU It is cleared (set to 0) by writing to the address of the EL register, and is set to 0 by a power-on reset. It is not affected by any other reset.

CPU The EL register is set to 0 regardless of whether it is little endian or big endian.
It is located at the double word address of x8000D200.
When something is written to this register, this register is set to 1 and the little endian serial PROM 18
Select This register is set to 1 immediately upon a power-on reset, and it is not affected by any other reset.

The reset control circuit 35 is endian. Re
Includes a set register, which is a forced reset register.
It is a star. When writing any value to this register, CP
U EB register and CPU Depending on the value of the EL register, C
Have the PU read one of the two serial PROMs. Endy
Ann The reset register clears itself during reset.
A. This register is little-endian or
Double-word address, regardless of endianness
0x8000D000.

The PROM control circuit 37 includes PROMs 30 and 3
64 and MAP2 for controlling the mapping of
56 registers and PGM for controlling programming of PROM 32 Contains the ENABLE register.

PGM The ENABLE register is a read / write register and is 0x8 in little endian mode.
00D500, 0x80 in big endian system
00D507 is accessed. It is used by the base firmware to erase or write the flash EEPROM boot firmware. Setting bit 0 to 1 in this register supplies 12 volts to the flash EPROM. No other bits are defined. This bit must be turned on and off by software according to special specifications for flash EPROM devices (eg, AM28F020).

The MAP64 register controls the PROM mapping method, and the address of the double word is 0x8 regardless of whether it is little endian or big endian.
000D300. Writing any value to this register causes endian By writing to the reset register, the 64-kilobit PROM becomes 0x1FC0
0000 (start address), 256Kbit bootflash EEPROM is 0xFC40000
Is mapped to The MAP64 register is cleared by writing to MAP256. This register is set to 1 on a power-on reset and is not affected by any other reset.

The MAP256 register is also a PROM
Control the wrapping method, and
Doubleword address, regardless of endianness
It has 0x8000D400. Any value in this register
And endian Write to reset register
256 Kbit Flash EE
PROM is copied to 0x1FC00000 (start address)
Imaged. MAP256 register is written to MAP64
Cleared by being left. This register is powered
Set to 0 upon a power-on reset, to any other reset
Therefore, it is not affected.

MCT The EB bit register is arranged in the memory and DMA control circuit 12. When data is written to the register, the register is set in the big endian system. This register is reset to little endian by power-on and forced reset.

FIGS. 3A and 3B show the relationship between hardware, firmware, and software in a prior art system that boots up the big endian MIPS RISC / OS operating system or the little endian Microsoft NT operating system. Is schematically shown.
In both cases, the hardware and the boot PROM are in a standard relationship, and the existence of a group of software is at an upper layer.

Referring to FIG. 3 (a), a stand-alone shell (SASH) interfaces with the boot PROM and hardware and includes routines to assist the routines in the boot PROM to assist in loading the operating system. . MIPS R
The ISC / OS operating system is a device driver (devic) that is linked so that part of the operating system appears to interact directly with the hardware.
e driver). At the top layer of the operating system is typically an application program that does not directly interface with the hardware.

The Microsoft NT shown in FIG.
For the operating system, the hierarchy is slightly different. Hardware abstraction
Layer (HAL) and device driver are boot PRO
Provides an interface to both M and hardware. And the NT operating system itself does not directly interface with the hardware. Furthermore, an application program interfaces to the operating system according to known means.

FIG. 4 is a diagram corresponding to FIG. 3 according to the present invention. The fundamental difference at this level is booting.
ng) is performed in two stages by the base firmware stored in the base PROM 30 and the boot firmware stored in the boot PROM 32. The base firmware and the boot firmware have a direct interface with the hardware.
Subsequent portions of the interface to the software firmware and hardware are described above.

The booting of the system is performed in the phases of phase 0 or “device configuration phase” and phase 1 or “boot phase”. Phase 0 firmware is located in the PROM 30 and phase 1 firmware is located in the flash EEPROM 32. FIG. 5A is a partial memory map for phase 0. The system is powered on during phase 0, during which phase the CPU and I / O subsystem are configured to operate in little endian. Phase 0, PROM
30 is given the capability and the starting address (0x in the example)
IFC00000). Flash EEPRO
M32 is an address offset from the start address (0x
IFC40000). PROM3
0 for all software routines (phase 0
Firmware) is compiled or assembled to operate in little endian fashion. Phase 0
Firmware handles exceptions, loads and executes programs from floppy disks,
Contains the code needed to control the / O byte order register and reset the entire system through software commands.

FIG. 5B is a partial memory map for Phase 1. As described below, the flash EEPROM is mapped to a start address so that exceptions and interruptions are directed to the original routine in Phase 0 and Phase 1.

FIG. 6 is a flowchart of the phase 0 firmware. Phase 0 firmware initializes the hardware, performs basic system diagnostics such as memory tests, and checks for the presence of an "installation diskette" in the floppy drive at power up. If no such diskette is found, the phase 0 firmware determines the byte order of the flash EEPROM by reading the signature. Then the system CPU resets the flash EEPROM after reset.
Verify that it is configured in the same byte order as specified by the OM signature. This means that if big endian is specified, the appropriate serial PRO
CPU to select M Writing to the EB register. The phase 0 firmware interacts with the reset circuit and sets the CP in the appropriate byte order.
U generates a reset sequence that pushes the system into the boot phase.

If "Instrument Floppy Disk" is found in the disk drive, Phase 0
The firmware will attempt to read and execute a little-endian "boot control" program on a floppy disk. An interactive "boot control" program instructs the user at installation to determine which operating system is installed. The program then reads the appropriate firmware file from the installation diskette (or network) according to the specified operating system byte order, byte swaps the firmware, erases and updates the flash EEPROM.

At this point, the program is executed starting from the point where the installation floppy disk is not present in the drive. After the reset is set to reconfigure the CPU to operate in the byte order specified by the sign if necessary, the memory mapping circuit is set to reset the flash EEPROM 32 to the start address. . This is accomplished by writing to the MAP256 register. Of the system reset program is to then start the boot phase Shea
Start the sequence . Upon reset, the CPU receives configuration information from the selected serial PROM and
The execution of the PROM boot firmware is started. This EEPROM has a standard firmware function used to boot an operating system. Then, once the control is transferred to the operating system in which the boot firmware is loaded, the operation phase starts.

The flow diagram shows that after the CPU is set to big endian, the next reset is followed by the step of setting the I / O to big endian (in parentheses). This is the preferred technique for setting the I / O byte order. However, in the embodiment described above, the MCT The EB bit is set to little endian on either reset. Therefore, setting this bit to big endian is performed after a reset by the boot firmware, if necessary.

[0034]

In summary, it can be seen that the present invention provides an elegant solution to the problem of byte order incompatibility. The stepwise boot approach to swap byte order provides a mechanism for changing the byte order of computer firmware through software control without powering on and off. The technology can be summarized as adapting the underlying byte order of the CPU, firmware and I / O system from the operating system through automatic reconfiguration of the CPU, firmware and I / O. In this way, the computer can execute software generated in either byte order.

While the above is a complete description of the preferred embodiment of the present invention, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be used as limiting the scope of the invention, which is defined by the claims.

[Brief description of the drawings]

FIG. 1 is a block diagram of a computer system embodying the present invention.

FIG. 2 is an enlarged block diagram showing a control register used in the present invention.

FIGS. 3 (a) and (b) show the relationship between hardware, software and firmware in the prior art for two operating systems.

FIG. 4 is a diagram showing a relationship among hardware, software, and firmware according to the present invention.

5 (a) and 5 (b) are memory maps showing remapping between phase 0 and phase 1 in a boot process according to the present invention.

FIG. 6 is a flowchart illustrating phase 0 firmware according to the present invention.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Robert Rodriguez, Inventor, California 95132 San Jose Mint Court 3546 (56) References JP-A-2-23437 (JP, A) JP-A-2-184530 (JP, A) JP-A-62-271113 (JP, A) JP-A-58-3015 (JP, A) JP-A-2-230440 (JP, A) JP-A-1-213717 (JP, A) (58) Int.Cl. ⁷ , DB name) G06F 9/06 G06F 13/14 G06F 9/445

Claims (8)

(57) [Claims] (1)Big Endian and Little Endian
In two byte ordering schemes,First and second bytes
Means for specifying one of the
SiteorderSpecified means power onTimeFeatures the first byte order method
Byte order specifying means having a default condition for defining, and first and second byte order methods in response to the byte order specifying means.
Characterized by a CPU configurable for operation in either of the formulas, and a first byte order containing the first program.
A first nonvolatile memory storing a first set of information
Mori and the program that characterizes the second program and the second set of information
Show orderforA second set of information, including data items,
The stored second nonvolatile memory;A first nonvolatile memory and a second nonvolatile memory
fromFirst and second addressesToIn the mapping
LaChoose oneThe first and / or the first operable to provide.
And an address map connected to the second nonvolatile memory
And the first and second byte order schemes comprising
In an operational computer system,From the first non-volatile memory First addressToMappi
The first set of information to a predetermined start address.
In theCan access and start,The second
A set of informationA predetermined location different from the start address
Can be accessed at the address  The second addressToMapping uses the second set of information
Predefined start addressAccess from
And can  The first program isAt least the following actions,Sand
ChiDetermine which byte ordering scheme is indicated
Said second information Set If the data item indicates a second byte ordering scheme,
Only the byte orderspecificSecond reset only by resetting the means
To specify the byte ordering method, and the byte ordering method indicated by the data itemRegardless,
Only when reset, the address mapping circuitSecond ad
To map Let  Of the CPUActivate the reset,Do that,  This resets the CPUWhen, The second
A set of informationOf the second addressTo start addressmapping
Is, The byte orderSpecific meansIs the data item
It operates in the byte order system shown in FIG.
The second set of information matches the byte order of the second set of information.
Computer characterized by the start of the second program
System. 2. The method according to claim 1, wherein said byte order specifying means is readable by said CPU and has first and second configuration information respectively corresponding to first and second byte orders.
2. A configuration memory, comprising: a register settable by the CPU; and a data selector responsive to a state of the register, operable in conjunction with a selected one of the configuration memories for the CPU. A computer system according to claim 1. 3. The computer system according to claim 1, wherein said first nonvolatile memory is a read only memory, and said second nonvolatile memory is a read / write memory. 4. The flash memory according to claim 2, wherein said second nonvolatile memory is a flash memory.
4. The computer system according to claim 3, wherein the computer system is an EPROM. 5. An I / O system configurable to operate in either a first or second byte order scheme, and means for configuring the I / O system in a first scheme upon power up; 2. The computer system according to claim 1, wherein said I / O system is configured in the byte order indicated by said data item when said second program is executed. 6. Before reading the data item, it is determined whether a storage medium having a third program and capable of being installed by a user is installed, and only when such a storage medium is provided. Instructing the user to specify whether the third program should be replaced with the second program, and only allow the third program to be replaced by the second program if the user specifies such replacement.
2. The computer system according to claim 1, wherein the first program causes an additional operation of overwriting the first program. 7. The computer system according to claim 6, wherein the recording medium that can be inserted by the user is a floppy disk. 8.Selected one of two byte ordering schemes
Booting a computer system with  Either the first or second byte orderByte orderIn the scheme
A first program characterized by a first byte order, comprising a CPU configurable for operation;
Ready to boot operating system
The first program is provided when the power is turned on.Byte ordermethodTo work withC
Configure the PU,Next, a first program is executed, and the first program is executed.
Works Determine the byte order of the second program,
Resetting U,Said resetBy the first programDecision
Configures the CPU in the specified byte order, and
Step to start runningIs characterized by consisting of
How to boot a computer system.