JP3186485B2 - Ferroelectric memory device and operation control method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device using a ferroelectric and an operation control method thereof.

[0002]

2. Description of the Related Art In recent years, a non-volatile memory having a function of retaining data even when the power is turned off has been realized by using a ferroelectric material having hysteresis characteristics such as lead zircon titanate (PZT) for a memory cell. I have. As an example of such a memory device, see JP-A-63-201998,
International Conference on Solid State Circuits in February 1988 (Internat
ionical Solid-State Circuit
s Conference, ISSCC) Proceedings 130
Pages from page 131 to page 131 and pages 268 to 269 of the proceedings of the International Conference on Solid State Circuits in February 1994.

Based on these reports, the circuit configuration and operation of a conventional nonvolatile ferroelectric memory device will be described.

FIG. 20 shows a type in which one memory cell is constituted by two transistors and two capacitors (hereinafter, referred to as JP-A-63-201998).
FIG. 1 shows a circuit of a ferroelectric memory cell (referred to as 2T / 2C type). 20, reference numeral 11 denotes a memory cell selection signal line (hereinafter simply referred to as a selection signal line), 13 denotes a plate line, 12, and 12 denote data signal lines, 101 denotes a memory cell, and 102 and 103 denote memory cell switching. The transistors 104 and 105 are ferroelectric capacitors.

In such a 2T / 2C type memory cell, data is written in the ferroelectric capacitors 104 and 105 so as to always have opposite polarization directions.
By reading the charges from the capacitors having the opposite polarizations onto the data signal lines 12 and / 12, respectively, a difference voltage is generated in the data signal line pair, and the difference voltage is generated by a sense amplifier which is a differential amplifier circuit. Amplify.

FIG. 21 shows a ferroelectric capacitor 104,
10 shows a hysteresis characteristic model 105. The relation of the spontaneous polarization charge Q with respect to the voltage V between both electrodes of the ferroelectric capacitor is shown. In particular, the polarization charge at a voltage of 0 is referred to as a residual polarization charge Qr. For example, ferroelectric capacitor 10
When the polarizations of 4,105 are in the states of A and B, respectively, the data is made to correspond to data "1", and when the polarization is reversed, to the data of "0". At this time, when a voltage of Ve is applied between both electrodes of the ferroelectric capacitor, in the case of data “1”, the charge of Q ₁ is discharged from the capacitor 104 and the capacitor 105 is discharged.
Charge of Q ₀ from, respectively the corresponding data signal line 1
2, / 12, and this charge causes the difference voltage of the data signal line pair as described above. In addition,
Ideally, the charge Qr and the charges Q ₀ and Q ₁ have a relationship of 2 × Qr = | Q ₁ −Q ₀ | (1).

In such a memory device using a ferroelectric capacitor, even when an external voltage applied between both electrodes of the ferroelectric capacitor becomes zero, the spontaneous polarization generated inside the ferroelectric becomes Since data is retained, a so-called non-volatile storage operation that retains data even when the power is turned off is realized.

FIG. 22 shows an example of a partial circuit of a memory cell array of a ferroelectric memory device using a memory cell of the type shown in FIG. In FIG. 22, 11a to 11c are selection signal lines,
12a, b, / 12a, b are data signal lines, 13a to 13c
Is a plate line, 14 is a data signal line precharge control signal line, 15 is a data signal line precharge power supply line, and 16 is a sense amplifier control signal line. 101a-f are memory cells, 102a and 103a are switching transistors of memory cells, 104a and 105a are ferroelectric capacitors, 106a and b are data signal line precharge circuits,
07a and b are sense amplifiers.

FIG. 23 shows an example of an operation timing chart of the memory device of FIG. Hereinafter, the read operation and the write operation of the ferroelectric memory device in the case where attention is paid to the memory cell 101a will be described with reference to FIGS. Note that, in FIG. 23 and subsequent figures, in the operation timing chart described in this specification, unless otherwise specified.
The level corresponding to the high level “H” is either a power supply voltage supplied from outside the memory device or a voltage generated by a voltage generating circuit provided inside the memory device, and is a level corresponding to the low level “L”. Is the ground voltage. The values of these voltages can take various values, such as 5 V and 3 V, as the case may be. For reference, when reading data "1", the ferroelectric capacitors 104a and 104a at the end of each of the periods (1) to (6) in FIG.
The polarization state of 5a is shown below the timing chart.

In FIG. 23, periods (1) to (3) are operations for reading data from a memory cell. First, in the period (1), the data signal line precharge control signal 14 is set to a low level to release the data signal line precharge state. Here, the data signal line precharge level is a ground voltage. Next, in a period (2), the selection signal line 11a and the plate line 13a are each raised to a high level, and data is output from the memory cell 101a to the data signal lines 12a and / 12a. The data signal output at this time is determined according to the polarization state inside the ferroelectric capacitor, and FIG. 23 shows a state in which data “1” is being read, as described above. Thereafter, in the period (3), the sense amplifier control signal line 16
Is activated, and the difference voltage between the data signal line pair 12a and / 12a is sense-amplified.

The subsequent periods (4) to (6) are operations in which the read data is written back into the memory cells. At the time of the period (2), the read data of the memory cell has been destroyed, and thus the rewriting operation is necessary. When writing data input from outside the memory device to the memory cell, a voltage corresponding to desired data is set on the data signal line pair 12a, / 12a during the period (3). The operation after the next period (4) is performed.

In a period (4), the plate line 13a is set to a low level. In the next period (5), the sense amplifier control signal line 16 is set to the low level to deactivate the sense amplifier, the precharge control signal line 14 is set to the high level, and the data signal line level is set to the ground voltage. By doing so, the polarization of the memory capacitor can be returned to the state (1) before data reading. Finally, in the period (6), the select signal line 11a is lowered to the low level, the memory cell transistor is turned off, and the access operation to the memory cell is completed.

When data "0" is stored in memory cell 101a, the polarization states of capacitors 104a and 105a are reversed from those in FIG.

Here, the relationship between the above circuit operation and the characteristics of the ferroelectric capacitor will be described. For example, FIG.
In the period (3) (2), the state where the selection signal line 11a is at the high level, the switching transistors 102a and 103a are turned on, and the plate line 13a is raised to the high level is shown in FIG. (The direction from the plate line to the data signal line is the positive direction of the voltage). In this case, the charge for Q ₁ or Q ₀ is outputted to the data signal line 12a. By the way, in this state, “1”,
Regardless of which “0” is stored, the polarization state of the ferroelectric capacitor is at point h shown in FIG.
"1" or "0" cannot be distinguished. Therefore, an operation of writing back data by applying + Ve, 0 voltage to the ferroelectric capacitor in accordance with the read “1”, “0” data is required. This corresponds to the operations (4) and (5) in FIG.

As described above, in order to realize a nonvolatile memory operation using a ferroelectric memory cell, it is necessary to apply a voltage in both positive and negative directions between both electrodes of a ferroelectric capacitor. .

In order to further increase the memory storage capacity, there is a type in which a memory cell is constituted by one transistor and one ferroelectric capacitor (hereinafter referred to as a 1T / 1C type). As an example of a memory device, see the 26th International Conference on Solid State Circuits, February 1994.
Some are reported from pages 8 to 269.

FIG. 24 shows a 1T / 1C type ferroelectric memory cell circuit. 11 is a selection signal line, 12 is a data signal line, 13 is a plate line, 101 is a ferroelectric memory cell,
102 is a memory cell switching transistor, 104
Is a ferroelectric capacitor. Hereinafter, the components corresponding to the circuit elements used in the drawings described above are denoted by the same reference numerals, and description thereof is omitted.

FIG. 25 shows a hysteresis characteristic model of the ferroelectric capacitor 104 of FIG. In the 1T / 1C type memory cell, unlike the 2T / 2C type memory cell, two stable states “A” / “B” of the ferroelectric are respectively associated with data “1” / “0”.

FIG. 26 shows a partial circuit example of a memory cell array using the 1T / 1C type memory cells shown in FIG.
In this case, the signal voltage from the memory cell is, for example, the data signal line 1 when the memory cell 101a is selected.
Appears only on 2a. As described above, when the 1T / 1C type memory cell is used, unlike the case of the 2T / 2C type,
It is necessary to generate a reference level for performing the sense amplification operation on the paired data signal line / 12a by providing a special means. In FIG. 26, the circuits 108a to 108d for generating the reference level and the control signal line 1
7a to 7b are added. A specific method of generating the reference level is described in, for example, the above-mentioned document, page 268 of the preliminary manuscript collection of International Conference on Solid-State Circuits in February, 1994. The point of the reference level generation method is that the voltage between the data signal line voltage when the signal corresponding to "1" is read from the memory cell and the data signal line voltage when the signal corresponding to "0" is read from the memory cell is the intermediate voltage. Is to occur.

FIG. 27 shows an example of an operation timing chart when attention is paid to the memory cell 101a in the circuit of FIG. When data "1" is read, FIG.
The polarization state of the ferroelectric capacitor 104a at the end of each of the periods (1) to (6) is shown below the timing chart.

When a signal is read out to the data signal line 12a, the reference level generating circuit 1 generates a reference level on the paired data signal line / 12a.
08b is added, and the reference level generated from the circuit 108b is read onto the data signal line / 12a. Except for this point, the operation is the same as that of the 2T / 2C type memory cell shown in FIG.

An example of realizing a nonvolatile memory device by combining a flip-flop of a type used for a static random access memory (SRAM) and a ferroelectric capacitor (hereinafter, referred to as an SRAM + ferroelectric memory cell) is described. , Feb. 1988, Proceedings of International Conference on Solid State Circuits, pages 130 to 131.

FIG. 28 shows an SRAM + ferroelectric type ferroelectric memory cell circuit. In the figure, reference numeral 18 denotes a selection signal line for the SRAM section, reference numerals 19 and 19 denote data signal lines for the SRAM section, and reference numerals 20 and 21 denote flip-flop power supply lines. Reference numeral 109 denotes a flip-flop, and 110 and 1
Reference numeral 11 denotes an N-channel transistor forming a flip-flop, 112 and 113 denote P-channel transistors forming a flip-flop, and 114 and 115 denote memory cell selection transistors.

A memory device using a memory cell of this type mainly transfers data from a ferroelectric capacitor to a flip-flop after power is turned on.
Used as AM. When turning off the power, the SRAM
Has the function of retaining data even after the power is turned off by transferring data from the device to the ferroelectric capacitor.

In this example, if each element in FIG. 28 is associated with FIG. 20 or FIG.
The memory cell selection signal line and the data signal line as the SRAM + ferroelectric type memory device are 18, 1
9/19, the memory cell selection signal line and the data signal line in the operation as a ferroelectric memory are 11, 12, and 12 shown in the figure, respectively. Transfer gates 102 and 103 for exchanging data with the lines are provided. That is, in FIG. 28, based on the operation as the ferroelectric memory device, the numbers of the respective constituent elements in FIG.
Note that it is associated with 4 and so on.

FIG. 29 shows ferroelectric capacitors 104, 1
05 when writing data to the capacitor 10
4 shows an example of an operation timing chart at the time of reading data from the flip-flops 4 and 105 to the flip-flop 109. It is assumed that the correspondence between the polarization states of the capacitors 104 and 105 and the data “0” and “1” is the same as in FIG. At this time, in the case of writing and reading of data “1”, (1)
The polarization states of the ferroelectric capacitors 104 and 105 at the end of each of the periods (10) to (10) are shown below the timing chart.

First, data is written from the flip-flop 109 to the ferroelectric capacitors 104 and 105 while the flip-flop 109 holds data (in the figure, the data signal line 12 is "H", and the data signal line / 12). Is “L”) during the period (1), the selection signal line 11 is set to the high level. Next, during the periods (2) and (3), the plate line 13 is driven from the low level to the high level and from the high level to the low level. afterwards,
By setting the flip-flop power supply line 21 to the low level during the period (4), the power supply of the flip-flop 109 is turned off, and finally, the selection signal line 11 is set to the low level during the period (5). In this way, the polarization state corresponding to the data stored in the flip-flop 109 is set in the capacitors 104 and 105, and the storage can be maintained even after the power supply of the memory device is turned off.

The data read from the capacitors 104 and 105 to the flip-flop 109 is performed first in a period (6).
Then, the selection signal line 11 is set to the high level, and then the plate line 13 is driven from the low level to the high level in the period (7) to apply a voltage between both electrodes of the capacitors 104 and 105 to correspond to the polarization state. The charges are read onto the data signal lines 12 and / 12. Then, period (8)
Then, the flip-flop power supply line 21 is raised to a high level to activate the flip-flop 109, and amplify the signal voltage read in the period (7). Next, the plate line 13 is returned to the low level in the period (9), and the selection signal line 11 is returned to the low level in the period (10), thereby completing the data read operation. Thereafter, the memory operation can be performed as a normal SRAM.

In FIG. 29, at the end of the period (1), the polarization state of the capacitor 105 is indefinite, but at the end of the period (5), the polarization state is determined. At the end of the period (10), a voltage is applied between the two electrodes of the capacitor 104, and the polarization state is not at the point corresponding to the voltage 0. There is no problem because the polarization state is determined. Data “0” is the flip-flop 10
9, the capacitors 104 and 10
The polarization state of No. 5 is opposite to that of FIG.

In this embodiment, a passive element such as a resistor can be used instead of the P-channel transistors 112 and 113 shown in FIG.

In the above example, all the plate lines 13
Is driven from a low level to a high level to apply a voltage in both positive and negative directions between both electrodes of the ferroelectric capacitor, thereby reading data. On the other hand,
By setting the plate line to a certain intermediate voltage, a voltage can be applied in both positive and negative directions between both electrodes of the ferroelectric capacitor to read data. FIG. 30 shows an example of a partial circuit of a memory cell array of such a memory device. 30, 116a and 116b are data signal line precharge / balance control circuits, 22 is a data signal line balance control signal line, and others are the same as those in FIG.

FIG. 31 is an example of the operation timing chart of FIG. Note that the plate line 13 is fixed at an intermediate voltage between the high level voltage and the low level voltage. Referring to FIG. 30 and FIG. 31, the memory cell 101a
The read operation and the write operation when attention is paid to FIG. For reference, the polarization state of the ferroelectric capacitor 104a at the end of each of the periods (1) to (7) is also shown below the operation timing chart.

First, in the period (1), the data signal line precharge state is released by setting the data signal line precharge control signal 14 to a low level. Here, the data signal line precharge level is also set to the ground voltage.
Next, in the period (2), the selection signal line 11a is raised to a high level, and the data signal line 12a is shifted from the memory cell 101a.
Output the data on a. Here, the difference from the operation of FIG. 25 is that the plate line 13 is not driven.
Since the data signal line precharge level is the ground voltage and the plate line is the intermediate voltage (Vm), when the memory cell transistor 102a is turned on in the period (2), both electrodes of the ferroelectric capacitor 104a are turned on. Between them, a voltage of approximately -Vm is applied with the direction from the plate line to the data signal line being the positive direction of the voltage. Then, a signal voltage corresponding to the polarization state is output from the ferroelectric capacitor 104a,
The data is read onto the data signal line 12a. At the same time, a reference level is generated on the paired data signal line / 12a by the circuit 108b. In the subsequent period (3), the sense amplifier control signal line 16 is activated to sense-amplify the difference voltage between the data signal line pair 12a and / 12a.

When writing data input from outside the memory device to the memory cell, a voltage corresponding to desired data is applied to the data signal line pair 12a, / 1 in the period (4).
Set to 2a.

In the period (5), the sense amplifier is deactivated by setting the sense amplifier control signal line 16 to low level, and the data signal line balance control signal line 2
2 is set to the high level, and the data signal line level is set to the same intermediate voltage Vm as the plate line. By doing so, the polarization of the memory cell capacitor is changed before data reading (1).
State can be returned.

After the selection signal line 11a is lowered to the low level in the period (6) to turn off the memory cell transistor,
In the period (7), the data signal line pair 12a, / 12a is precharged to the ground voltage, and one cycle of the access operation to the memory cell is completed.

The signal voltage read from the ferroelectric capacitor depends on the voltage applied between both electrodes of the ferroelectric capacitor. Generally, the larger the voltage applied between both electrodes, the greater the signal voltage. In the operation of the ferroelectric memory device as described above, the voltage applied between both electrodes of the ferroelectric capacitor is related to the plate line setting voltage and the voltage amplitude of the data signal line. Therefore, the plate line setting voltage and the voltage amplitude of the data signal line may be set to any value as long as the signal voltage read from the ferroelectric is a value that enables the sense amplifier to sense and amplify data normally. For example, there is a method in which the set voltage of the plate line is set to の of the power supply voltage, and the amplitude of the data signal line is set between the ground voltage and the power supply voltage. The power supply voltage may be supplied from outside the memory device, or may be a voltage generated by a voltage generation circuit inside the memory device.

FIG. 32 shows a specific circuit of the data signal line precharge / balance control circuits 116a and 116b. The data signal line precharge transistors 117 and 118 are the same as those in FIGS. 22 and 26, and additionally, a data signal line balance transistor 119 is provided.
When the transistor 119 is turned on from a state where the data signal line pair 12, / 12 is at the power supply voltage and the ground voltage, respectively, the data signal line pair 12, / 12 has substantially the same parasitic capacitance value. The line voltage is の of the power supply voltage. Plate line setting voltage is 1/2 of power supply voltage
In such a case, such a circuit is effective.

Although FIGS. 30 and 31 have been described using 1T / 1C type memory cells, a ferroelectric memory device operated without driving a plate line does not depend on the type of memory cells.

The 2T / 2C type shown in FIG. 22 and the SRA shown in FIG.
The M + ferroelectric type can also perform the same operation by driving and controlling the corresponding signal lines in the same manner as in FIG.

In the examples shown in FIGS. 23, 27, 29, and 31, the precharge level of the data signal line is set to the ground voltage. However, this voltage is set when the select signal line 11a is set to the high level. Any value may be used so long as a non-zero voltage is applied between both electrodes of the ferroelectric capacitor, and the voltage is not limited to the ground voltage.

[0042]

However, in the conventional ferroelectric memory device, when reading data from the memory cell, a sufficient voltage is applied between both electrodes of the ferroelectric capacitor due to the following circumstances. There was a problem that it did not take.

When data is read from a memory cell in a ferroelectric memory device of the type that operates by driving a plate line (hereinafter referred to as a plate driving type) as described with reference to FIGS. , The bit line is floating. Therefore, when the plate line is driven from the low level to the high level, the data signal line voltage fluctuates due to the coupling of the memory cell through the ferroelectric capacitor, and the coercive electric field EC is generated between both electrodes of the ferroelectric capacitor. A voltage higher than the coercive voltage VC converted into a voltage by multiplying the film thickness of the ferroelectric substance may not be applied, and the polarization inversion of the ferroelectric substance may not occur.

This will be described in more detail with reference to FIG.

The parasitic capacitance value of the data signal line is CD, and the capacitance value of the paraelectric component of the ferroelectric capacitor is CS.

When the memory cell switching transistor 102 is turned off, that is, when the memory cell 1
01 is not selected, the transistor 10
2 is set to a state in which a voltage VBOOT for conducting 2 is applied to the selection signal line 11. Then, when the plate line 13 is driven from the voltage VPL0 in the initial state to the voltage VPL in the final state,
The initial voltage of the data signal line 12 is VDL0, and the final voltage is VDL.
DL, transistor 102 and ferroelectric capacitor 104
Is the initial voltage of the node 23 to which the transistor 102 is connected, and the final voltage is VDL because the transistor 102 is conducting, and the total charge Qi of the system of FIG.
Qi = CS × (VS0−VPL0) + CD × VDL0 (2) The total charge Qf of the system in the final state is: Qf = CS × (VDL−VPL) + CD × VDL (3) If Qi = Qf When the absolute value | VPL−VDL | of the voltage applied between both electrodes of the ferroelectric capacitor in the final state is obtained from the condition that

[0047]

(Equation 5)

Is as follows. On the other hand, | VPL-VDL |
Must be greater than the coercive voltage of the ferroelectric capacitor, | VPL−VDL | ≧ VC (5) Here, the data signal line is precharged to the ground voltage GND,
That is, if VDL0 = 0, and both VS0 and VPL0 are GND, the equations (4) and (5) are as follows.

[0049]

(Equation 6)

Assuming that VC = 1.5 V, VPL = 3.3 V
Then, equation (6) becomes CD ≧ 0.833... × CS (7).

Equation (7) shows that the parasitic capacitance value C of the data signal line is
D has a lower limit, and unless CD is equal to or greater than the lower limit, it indicates that a voltage of VC or more is not applied between both electrodes of the ferroelectric capacitor. As described above, since the voltage of the data signal line fluctuates due to the coupling via the ferroelectric capacitor by driving the plate line, the conditions shown in equations (4) and (5) are not generally satisfied. Then, a sufficient read signal voltage cannot be obtained from the memory cell.

On the other hand, in the ferroelectric memory device of the type which operates without driving the plate line (hereinafter referred to as plate non-drive type) as described with reference to FIG. 31, the mechanism is the same as that of the plate drive type. Although different, a similar problem occurs.

In a plate non-drive type ferroelectric memory device, when a memory cell is not accessed,
In order not to destroy stored data, it is necessary to keep the voltage applied between both electrodes of the ferroelectric capacitor to zero. That is, when the plate line is set to the intermediate voltage, the node at the counter electrode of the ferroelectric capacitor, that is, the node connecting the memory cell switching transistor and the ferroelectric capacitor also has the same intermediate voltage. From this state, when the selection signal line is raised to a high level in order to read data from the memory cell, first, the electric charge stored at the connection node between the ferroelectric capacitor and the switching transistor of the memory cell on the data signal line. Is output on the data signal line, so that the data signal line voltage fluctuates from its precharge level. For this reason, a voltage higher than the coercive voltage VC is not applied between the two electrodes of the ferroelectric capacitor, and there may be a case where the polarization inversion of the ferroelectric does not occur.

This problem will be described in detail with reference to FIG. 34, similarly to FIG. FIG. 34 differs from FIG. 33 in that the voltage of the plate line 13 is a constant value VPLC.

Here, the selection signal line 11 is supplied with a voltage VBOOT at which the transistor 102 becomes conductive from the initial state in which the memory cell switching transistor 102 is non-conductive, that is, the memory cell 101 is not selected. Let's consider the case of moving to the final state. Using the same symbols as in FIG. 33 except for the voltage VPLC of the plate line, the total charge Qi of the system in FIG. 34 in the initial state is as follows: Qi = CS × (VS0−VPLC) + CD × VDL0 (8) The total charge Qf of the system is: Qf = CS × (VDL−VPLC) + CD × VDL (9) From the condition that Qi = Qf, the voltage applied between both electrodes of the ferroelectric capacitor in the final state When the absolute value | VPLC-VDL | is obtained,

[0056]

(Equation 7)

Is as follows. As in the case of the plate drive type, this | VPLC-VDL | must be larger than the coercive voltage of the ferroelectric capacitor, so | VPLC-VDL | ≧ VC (11) Here, the data signal line is grounded again. Assuming that voltage GND precharge, that is, VDL0 = 0, and both VS0 and VPLC are 電源 of power supply voltage VCC, (1
Equations (0) and (11) are as follows.

[0058]

(Equation 8)

Assuming that VC = 1.5 V, VCC = 3.3 V
Then, the expression (12) becomes CD ≧ 10 × CS (13).

Equation (13) also indicates that the parasitic capacitance CD of the data signal line has a lower limit, as in equation (7).
As described above, even in the ferroelectric memory device of the plate line non-driving type, a sufficient read signal voltage cannot be obtained from the memory cell unless the conditions shown in the expressions (10) and (11) are generally satisfied. I understand.

The above is a discussion on the lower limit value of the parasitic capacitance value CD of the data signal line. By the way, in the case of a reading method in which a signal charge read from a memory cell is output on a data signal line to be a signal voltage, first,
When a 2T / 2C type memory cell is used, the signal voltage VSI
G is calculated using charges Q ₀ and Q ₁ or charge Qr in FIG.

[0062]

(Equation 9)

Is obtained. Here, the relational expression (1) is used.

In the case of a reading method using a 1T / 1C type memory cell and generating a reference level by a reference level generating circuit, the charges Q ₀ and Q ₁ or the charges Qr in FIG. 25 are used. Using equation (1),

[0065]

(Equation 10)

Is obtained. The factor と き at this time is that the reference level is set to a voltage exactly intermediate between the voltage of the data signal line when data “0” is read and the voltage of the data signal line when data “1” is read. Means When the reference level deviates from an intermediate value depending on the method of the reference level generating circuit, the reference level is not a factor ２, but a value larger than 0 and smaller than 1.

VSIG in (14) or (15) is the minimum voltage VSE at which the sense amplifier can normally amplify data.
VSIG ≧ VSE (16) That is, when the parasitic capacitance CD exceeds a certain level, VSIG becomes too small, and the minimum voltage at which the sense amplifier can normally amplify data is obtained. It means that it is below the value and cannot be operated. This indicates that the parasitic capacitance value CD also has an upper limit.

As described above, generally, in the ferroelectric memory device, the relationship between the parasitic capacitance value CD and the capacitance value CS has a relationship as shown in FIG. In FIG. 35, the dashed line indicates the lower limit value of the parasitic capacitance value CD in the plate drive type ferroelectric memory device, and the dotted line indicates the parasitic capacitance value C in the plate non-drive type ferroelectric memory device.
The lower limit of D is shown, and the solid line shows the upper limit of the parasitic capacitance CD required to obtain from the memory cell a read signal voltage that enables the sense amplifier to normally perform data amplification. The hatched part is the plate drive type and non-drive type operation mode,
It is within the operable range.

As described above, in the ferroelectric memory device, when data is read from a memory cell, the data signal line voltage fluctuates although the mechanism may differ depending on the operation method. Under the conditions, there is a problem that a coercive voltage, which is a voltage at which the polarization is inverted, is not applied between both electrodes of the ferroelectric capacitor, and a normal data read operation is not performed.

An object of the present invention is to solve the above problems and to provide a ferroelectric memory device capable of performing a stable operation and a method of controlling the operation thereof.

[0071]

A ferroelectric memory device according to the present invention is selected in accordance with a ferroelectric capacitor using a ferroelectric material, a data signal line for inputting / outputting data, and an address signal. A selection signal line, switching means provided between the ferroelectric capacitor and the data signal line and selectively controlled by the selection signal line, wherein the polarization state of the ferroelectric capacitor corresponds to storage data. Then, when a first non-zero voltage is applied between both electrodes of the ferroelectric capacitor, a current flowing between the ferroelectric capacitor and the data signal line changes the polarization state of the ferroelectric capacitor. Detecting the difference of the current due to the stored data, or detecting the difference of the voltage appearing on the data signal line due to the difference of the current. A memory cell for reading stored data, the data signal line to which the plurality of memory cells are connected, and a current type sense amplifier or a circuit for detecting a difference in current due to the stored data. A unit memory cell array input to a voltage type sense amplifier which is a circuit for detecting a voltage difference, a memory cell array in which a plurality of the unit memory cell arrays are arranged, and the selection signal line is set to a second state in which the memory cells are selected. When reading data from the memory cell onto a data signal line, the data signal line voltage is controlled by a factor other than a current due to polarization of the ferroelectric capacitor. Means for temporarily controlling a parasitic capacitance value of the data signal line during a read operation. .

Further, according to the present invention, in the operation control method of the ferroelectric memory device, when reading data stored in the memory cell, the voltage of the data signal line is set to a third voltage, Is driven from the fourth voltage which is the voltage before the data read operation to the fifth voltage different from the third voltage, and the voltage of the selection signal line is changed to the second voltage at which the memory cell is in the selected state. Setting a voltage difference between the first and second terminals of the ferroelectric capacitor to output a signal corresponding to the data stored in the memory cell on the data signal line. Features.

[0073]

According to the present invention, when data is read from a memory cell, voltage fluctuation of a data signal line is suppressed, and a voltage higher than a coercive voltage is reliably applied between both electrodes of a ferroelectric capacitor. The provision of the means for temporarily setting the parasitic capacitance value to the optimum value allows the ferroelectric memory device to operate stably.

[0074]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a partial circuit of a memory cell array portion of a ferroelectric memory device according to a first embodiment of the present invention. FIG. 1 shows an example in which the present invention is applied to a ferroelectric memory device using a 1T / 1C type memory cell shown in FIGS.

As described in the section of "Problems to be Solved by the Invention", in the ferroelectric memory device, when data is read, the expressions (4) and (5) are used in the case of the plate drive type operation method. Or derived from them (6),
Equation (7) must be satisfied. For this condition, for example, the parasitic capacitance value CS is 200 fF, the parasitic capacitance of the data signal line portion per memory cell is 5 fF, the number of memory cells per data signal line is n, the sense amplifier and the precharge circuit, etc. Assuming a ferroelectric memory device in which the parasitic capacitance of the data signal line excluding the memory cell portion is 50 fF, and applying the expression (7) (the conditions such as the operating voltage are the same as those of the expression (7)) 50fF + 5fF × n ≧ 0.833... × 200fF (17).

As shown in FIG. 1, a data signal line capacitance adjusting circuit 121a comprising a data signal line capacitance adjusting transistor 122a and a data signal line capacitance adjusting capacitor 123a having a capacitance CC is connected to a data signal line capacitance adjusting circuit 121a. Connect to line 12a. The gate terminal of the transistor 122a is connected to the data signal line capacitance adjusting circuit control signal line 27a, the drain terminal is connected to the data signal line 12a, and the source terminal is connected to one of the data signal line capacitance adjusting capacitors 123a. The other terminal of 123a is connected to the data signal line capacitance value adjusting circuit internal capacitor terminal line 28a. Data signal line capacitance adjustment circuit 121
Similarly, connections b to d are made as shown in the figure.

Thus, the relational expression (7) that must be satisfied when the memory cell array reads data from the memory cell is changed as follows.

50fF + 5fF × n + CC ≧ 0.833... × 200fF (18) On the other hand, simultaneously with the expression (18), the condition that the read signal voltage from the memory cell exceeds the minimum voltage at which the sense amplifier can normally amplify data. Equation (16) must also be satisfied.

The conditions are as follows: the data signal line parasitic capacitance per sense amplifier unit and one memory cell;
The S value is the same as that used for deriving the above equation (18), and the minimum voltage value at which the sense amplifier can normally amplify data is 100 mV, 1T / 1C type memory cell, and (Q
_{When the} expressions (15) and (16) are applied to a ferroelectric memory device in which ₁₋ Q ₀ ) is 1000 fC, the following expression is obtained.

(1/2) × 1000 fC / (50 fF + 5 fF × n + CC + 200 fF) ≧ 100 mV (19) In the case of a 2T / 2C type memory cell, (Q ₁ −
Assuming that Q ₀ ) is 1000 fC, (1
By applying the expressions (4) and (16), the expression becomes the expression in which the first factor (1/2) on the left side of the expression (19) is eliminated.

1000 fC / (50 fF + 5 fF × n + CC + 200 fF) ≧ 100 mV (20) In the above, the data line parasitic capacitance value of the sense amplifier section
By adjusting the value of CC to an appropriate value irrespective of parameters such as the data signal line parasitic capacitance value and CS of the memory cell portion, the expression (18) and the expression (19) or (20) can be satisfied. It is possible to

FIG. 2 shows an operation timing chart of the ferroelectric memory device of FIG. The operation when focusing on the memory cell 101a will be described.

First, when data is read from the memory cell 101a, the data signal line capacitance value control circuit control line 27a rises almost simultaneously with the rise of the selection signal line 11a and the plate line 13a, and the capacitance CC is applied to the data signal line 12a. Has been added. Since the entire parasitic capacitance of the data signal line 12a is set so as to satisfy the equations (18) and (19) by adding CC, a sufficient voltage is applied between both electrodes of the capacitor 104a, and It is guaranteed that a read signal voltage sufficient for normal operation is obtained. The rising timing of the control signal line 27a is determined by the selection signal line 11
a, may be before the plate line 13a. Further, the fall timing is before activation of the sense amplifier, during the sense amplification operation or after the end of the sense amplification operation, that is, between the fall timing indicated by the solid line and the fall timing indicated by the one-dot chain line in FIG. Anywhere. In particular, before performing sense amplification (in the figure, control signal line 27
control signal line 27a at the falling timing of the solid line
When the voltage is lowered, the capacitance CC is not attached to the data signal line at the time of sense amplification, so that there is no need to charge / discharge an extra capacitance, and the operation speed and power consumption are reduced, which is effective. Other operations are the same as those of the conventional example.

As described above, according to the present invention, the component of the data line parasitic capacitance value excluding CC can be freely set by design, so that the read signal voltage from the memory cell can be secured. In addition, after reading data from the memory cell and before performing the sense amplification operation, the adjusting circuit 1
By deactivating the capacitor 21a and disconnecting the capacitance value CC from the data signal line, it is possible to increase the sense amplification operation at the time of reading.
It can be faster . When writing data input from outside the memory device to the memory cell,
Since it is not necessary to satisfy the expressions (4) and (5), the unnecessary parasitic capacitance CC can be obtained by inactivating the adjustment circuit 121a in advance.
It is not necessary to charge and discharge for a minute, and the operation speed and power consumption can be reduced here. An example of an operation timing chart at the time of such writing is shown in FIG. 3 as a second embodiment of the present invention. By inactivating the control signal line 27a at the low level and setting the voltage corresponding to the data to be written in the period (3) to the data signal line 12a, data writing to the ferroelectric memory cell 101a is realized. In FIG. 3, first, the data read operation from the ferroelectric memory cell 101a is performed in the period (2). In this case, the equations (4) and (5) are satisfied with respect to the parasitic capacitance of the data signal line. Since there is a possibility that the data is not read, the data to be read may not match the data stored in the memory cells. further,
If the data to be written is known from the beginning, a voltage corresponding to the data to be written may be set in advance on the data signal line 12a as shown in FIG. 4 as a third embodiment of the present invention. . Also in FIG. 4, the control signal line 27a is at a low level.

Data signal line capacitance adjusting capacitor 12
3a, a ferroelectric capacitor of a memory cell is used, and data signal line capacitance value adjusting circuits 121a to 121d are used.
Alternatively, the memory cell itself can be used. In some cases, a plurality of adjustment circuits 121a can be connected to one data signal line.

In the adjusting circuit 121a of FIG. 1, a node 29a where the data signal line capacitance adjusting transistor 122a and the data signal line capacitance adjusting capacitor 123a are connected is connected to the node 29a when the control signal line 27a is at a low level. It is ting. To avoid this,
As a fourth embodiment of the present invention, there is a method using the circuit shown in FIG. This is obtained by adding a transistor 125 having a drain terminal connected to a node 29, a signal line 31 connected to a source terminal, and a control line 30 connected to a gate terminal.
FIG. 6 shows an example of an operation timing chart when the adjustment circuit 121 of FIG. 5 is applied to the memory cell array partial circuit of FIG.
Shown in When the control signal line 27 in FIG. 5 is not activated, the data signal line capacitance adjusting circuit precharge control signal line 30 is set to the high level, and the voltage of the node 29 in the data signal line capacitance adjusting circuit is changed to the data signal line capacitance. The voltage supplied from the value adjusting circuit precharge power supply line 31 is compensated to prevent an unspecified charge from flowing out from the node 29 onto the data signal line 12 when the control signal line 27 is set to a high level. The fall timing of the control signal line 30 is controlled by the control signal line 2
7 may be before the high level, and the control signal line 30
May be performed after the control signal line 27 becomes low level. It is of course possible to adopt the write operation method shown in FIGS. 3 and 4 using the circuit of FIG.

FIG. 7 shows a partial circuit of a memory cell array portion of a ferroelectric memory device according to a fifth embodiment of the present invention. FIG. 7 shows an example in which the present invention is applied to the ferroelectric memory device using the 1T / 1C type memory cell shown in FIGS. 30 and 31 and adopting a plate non-drive type data reading method.

In the case of the plate non-drive type operation system, (1
0), (11) or derived from them (1
Equations (2) and (13) must be satisfied. Capacity value C
S, the parasitic capacitance of the data signal line portion per memory cell, the number of memory cells attached to one data signal line, the parasitic capacitance of the data signal line portion excluding the memory cell portion such as a sense amplifier and a precharge cycle, etc. Assuming that the same ferroelectric memory device as that of the above-mentioned plate drive type is used as the device parameter condition, the expression (13) is applied (accordingly, the condition such as the operating voltage follows the assumption of the expression (13). Must be satisfied), 50fF + 50fF × n ≧ 10 × 200fF (21)

In the case of FIG. 7, a circuit 121a including a transistor 122a having the same configuration as that of FIG.
2a. At this time, the relational expression (21) is changed as follows.

50fF + 50fF × n + CC ≧ 10 × 200fF (22) On the other hand, the conditional expression that must be satisfied from the viewpoint of the minimum voltage at which the sense amplifier can normally amplify data is the minimum voltage value at which the sense amplifier can normally amplify data. If the values of (Q ₁ -Q ₀ ) are the same as in the case of the plate drive type, similarly, for a 1T / 1C type memory cell, the equation (19) is used, and for a 2T / 2C type memory cell, 20)
It becomes an expression.

In the above description, even in the case of the plate non-drive type operation method, the value of CC is adjusted to an appropriate value so that the expression (22) and the expression (19) or (20) are satisfied. Is possible.

FIG. 8 is an operation timing chart of FIG. The operations of the data signal line capacitance adjusting circuit control signal line 27a and the data signal line capacitance adjusting circuit internal capacitor terminal line 28b of the data signal line capacitance adjusting circuit 121a are the same as those in FIG. The operation is the same as in FIG. Further, for a ferroelectric memory device employing this plate non-drive type operation method,
The operation method of data writing shown in FIGS. 3 and 4 can be similarly applied, and the circuits and operation methods shown in FIGS. 5 and 6 can also be applied.

FIG. 9 shows a transfer gate 124 for connecting a data signal line to a plate drive type ferroelectric memory device.
A diagram showing a sixth embodiment of the present invention in which a plurality of data signal lines are connected to each other by adding a to h to control a data signal line parasitic capacitance value CD at the time of data reading. It is. In the embodiments described so far,
The capacitance value CD was adjusted by adding a circuit including a transistor and a capacitor to the data signal line, but the viewpoint was changed, and several data signal lines were combined,
By connecting the data signal lines to each other via a transfer gate and controlling the conduction / non-conduction of the transfer gate by a signal, the capacitance value CD at the time of data reading is adjusted.

FIG. 10 shows an example of the operation timing chart. Control signal line 3 of transfer gates 124a to 124h
2a and 2b control the connection state between the data signal lines. As a control method of the control signal lines 32a and 32b, as shown by a solid line in FIG.
When the value of the capacitance value CD at the time of data reading is (4), (5)
There is a method in which the control signal lines 32a and 32b are set to a high level so that several data signal lines are connected as a group so as to satisfy the formula. Alternatively, as indicated by the dotted line in the figure, the transfer gate 124 is at a high level during standby.
There is also a method in which the signal lines 32a and 32b corresponding to the data signal lines to be disconnected are changed to a low level from the state where all of a to h are conducting. In FIG. 10, the memory cell 101a
Is selected as an example, and the control signal line 32a
Is at a high level from the data reading of the memory cell 101a to the completion of the sense amplification, the control signal line 32b is at a high level when the data of the memory cell 101a is read, and at a low level before the sense amplification. The timing of the fall of the control signal line 27b may be delayed until the timing indicated by the one-dot chain line in the figure after the end of the sense amplification. Memory cell 101
When c and f are selected, the control signal lines 32a and 32
The control operation of b is reversed. Here, the case where two data signal lines are paired and the connection is controlled by the transfer gates 124a to 124h is taken as an example, but three or more data signal lines can of course be paired. .

FIGS. 11 and 12 show a sixth embodiment.
32 is a circuit and operation timing chart of a seventh embodiment of the present invention applied to the plate non-drive type ferroelectric memory device shown in FIGS. 30 and 31. The control method of the transfer gate control signal lines 32a and 32b is the same as that of FIG.
The operation of other signals is the same as in FIG.

An example in which the present invention is applied to a ferroelectric memory device using an SRAM + ferroelectric memory cell will be described. FIG. 13 shows an SRAM + ferroelectric memory cell circuit according to an eighth embodiment of the present invention. A circuit 121 including transistors 122a and 122b and capacitors 123a and 123b having a capacitance CC is added to the conventional SRAM + ferroelectric memory cell circuit shown in FIG. The transistors 122a and 122b are controlled by the data signal line capacitance adjusting circuit control signal line 25. One terminal of each of the capacitors 123a and 123b is connected to the internal capacitor terminal line 26 of the data signal line capacitance adjusting circuit.
Is connected. Data signal line capacitance adjustment circuit 121
May be connected as shown in FIG. 14, which is the ninth embodiment of the present invention.

FIG. 15 shows an example of an operation timing chart of the circuit shown in FIG. 13 or FIG. Flip-flop 1
The data write operation from 09 to the ferroelectric capacitors 104 and 105 can be performed in the same manner as (1) to (5) in FIG. In the read operations (6) to (10) from the capacitors 104 and 105 to the flip-flop 109, the data signal line capacitance adjusting circuit control signal line 25 is set to a high level before or simultaneously with the selection signal line 11 being set to a high level. , The capacity CC is added to the data signal lines 12 and / 12. For CC, relational expressions (4),
It is assumed that necessary ones among (5), (10), (11), and (16) are satisfied. Thereafter, between the fall timing of the solid line of the control signal line 25 and the fall timing of the alternate long and short dash line, that is, before or after the data is amplified by the flip-flop 109 by setting the flip-flop power supply line 21 to the high level, or during or after the data amplification. The control signal line 25 is set to low level.

Instead of connecting the data signal line capacitance value adjusting circuit 121 to each memory cell as shown in FIGS. 13 and 14, the tenth embodiment of the present invention, as shown in FIG. The present invention can also be implemented by driving a signal. In FIG. 16, as shown in the operation timing chart of FIG.
9, / 19, the relational expressions (4), (5), (10), (1
1) and (16), when the required parasitic capacitance CC is provided, the memory cell selection signal line 18 for the SRAM is controlled by the data signal line capacitance value adjusting circuit control circuit shown in FIGS. The present invention is implemented by driving in the same manner as the signal line 25. Capacity CC
May be a parasitic capacitance of wiring or a capacitance intentionally added.

As shown in FIG. 18 as an eleventh embodiment of the present invention, the capacitance in FIG. 16 is replaced by transistors 122a and 122b and a capacitor 12 having a capacitance value CC.
Data signal line capacitance value adjusting circuit 1 composed of 3a and 3b
21a and 21b can be added. In this case, FIG.
As shown in the operation timing chart, it is necessary to control the data signal line capacitance adjusting circuit control signal line 25 of the transistors 122a and 122b. The control signal line 25 may control rising and falling at substantially the same timing as the selection signal line 18.

In the embodiments of the present invention described above, 1T / 1C type, 2T / 2C type, SRAM
Although the + ferroelectric type has been taken as an example, the application of the present invention is not limited to those memory cells. When a voltage is applied between both electrodes of a ferroelectric capacitor when reading data, all ferroelectric memory devices that operate in such a manner that voltage fluctuations at nodes connected to both electrodes of the ferroelectric capacitor are problematic The present invention can be applied in the same manner as in the above embodiment. Further, it is also possible to realize the memory device of the present invention by combining the respective embodiments described above.

[0102]

By using the ferroelectric memory device of the present invention, a voltage higher than the coercive voltage is not applied between both electrodes of the ferroelectric capacitor due to the voltage fluctuation of the data signal line at the time of data reading. A situation in which a sufficient read signal voltage cannot be obtained can be avoided, and stable ferroelectric memory device operation can be performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a ferroelectric memory device according to a first embodiment of the present invention, which adjusts a parasitic capacitance value of a data signal line by providing a circuit including a transistor and a capacitor.

FIG. 2 is an operation timing chart of FIG.

FIG. 3 is an operation timing chart at the time of data writing according to a second embodiment of the present invention.

FIG. 4 is an operation timing chart at the time of data writing according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a circuit according to a fourth embodiment of the present invention, in which a precharge transistor is connected to a circuit including a transistor and a capacitor.

FIG. 6 is an operation timing chart when the circuit of FIG. 5 is applied to the circuit of FIG. 1;

FIG. 7 is a circuit diagram of a ferroelectric memory device according to a fifth embodiment of the present invention, which adjusts a parasitic capacitance value of a data signal line by providing a circuit including a transistor and a capacitor.

FIG. 8 is an operation timing chart of FIG. 7;

FIG. 9 is a circuit diagram of a ferroelectric memory device according to a sixth embodiment of the present invention, in which a plurality of data signal lines are connected to adjust a data signal line parasitic capacitance value.

FIG. 10 is an operation timing chart of FIG.

FIG. 11 is a circuit diagram of a ferroelectric memory device according to a seventh embodiment of the present invention, in which a plurality of data signal lines are connected to adjust a data signal line parasitic capacitance value.

FIG. 12 is an operation timing chart of FIG.

FIG. 13 is a circuit diagram of an SRAM + ferroelectric memory device according to an eighth embodiment of the present invention.

FIG. 14 is a circuit diagram of an SRAM + ferroelectric memory device according to a ninth embodiment of the present invention.

FIG. 15 is an operation timing chart of FIG. 13 or FIG.

FIG. 16 shows an SRAM + according to a tenth embodiment of the present invention.
FIG. 3 is a circuit diagram of a ferroelectric memory device.

FIG. 17 is an operation timing chart of FIG.

FIG. 18 shows an SRAM + according to an eleventh embodiment of the present invention.
FIG. 3 is a circuit diagram of a ferroelectric memory device.

19 is an operation timing chart of FIG.

FIG. 20 is a diagram showing an example of a memory cell circuit including two transistors and two ferroelectric capacitors.

21 is a diagram showing a relationship between a voltage V applied between both electrodes of the ferroelectric capacitor of FIG. 20 and a spontaneous polarization charge Q. FIG.

FIG. 22 is a diagram showing a memory cell array circuit example of a ferroelectric memory device using the memory cells of FIG. 20;

FIG. 23 is an operation timing chart of FIG. 22.

FIG. 24 is a diagram showing an example of a memory cell circuit including one transistor and one ferroelectric capacitor.

25 is a diagram showing a relationship between a voltage V applied between both electrodes of the ferroelectric capacitor of FIG. 24 and a spontaneous polarization charge Q.

26 is a diagram showing an example of a memory cell array circuit of a ferroelectric memory device using the memory cells of FIG.

FIG. 27 is an operation timing chart of FIG. 26;

FIG. 28 is a circuit diagram of an SRAM + ferroelectric memory device.

FIG. 29 is an operation timing chart of FIG. 28.

FIG. 30 is a diagram showing a memory cell array circuit of a plate non-drive type ferroelectric memory device.

FIG. 31 is an operation timing chart of FIG. 30.

FIG. 32 is a diagram showing an example of a data signal line precharge / balance control circuit.

FIG. 33 is a diagram showing a voltage change of a data signal line when reading data from a memory cell in a plate drive type ferroelectric memory device.

FIG. 34 is a diagram showing a voltage fluctuation of a data signal line when reading data from a memory cell in a plate non-drive type ferroelectric memory device.

FIG. 35 is a diagram showing a relationship between a data signal line parasitic capacitance value and a paraelectric component capacitance value of a ferroelectric capacitor, and an operable range of the ferroelectric memory device.

[Explanation of symbols]

11, 11a, 11b, 11c Selection signal line 12, 12a, 12b, / 12, / 12a, / 12b
Data signal line 13, 13a, 13b, 13c Plate line 14 Data signal line Precharge control signal line 15 Data signal line Precharge power supply line 16 Sense amplifier control signal line 17a, 17b Reference level generation circuit control signal line 18 SRAM + ferroelectric type In the memory device, the SR
Select signal line for AM section 19, / 19 In SRAM + ferroelectric memory device, data signal line for SRAM section 20, 21 Flip-flop power supply line 22 Data signal line balance control signal line 23 Memory cell internal node 25 Data signal line capacitance value Adjustment circuit control signal line 26 data signal line capacitance value adjustment circuit internal capacitor terminal line 27, 27a, 27b data signal line capacitance value adjustment circuit control signal line 28, 28a, 28b data signal line capacitance value adjustment circuit internal capacitor terminal line 29, 29a Data signal line capacitance adjustment circuit internal node 30 Data signal line capacitance adjustment circuit precharge control signal line 31 Data signal line capacitance adjustment circuit precharge power supply line 32a, 32b Transfer gate control signal line 101, 101a, 101b, 101c , 101d, 1
01e, 101f Ferroelectric memory cells 102, 102a, 103, 103a Memory cell switching transistors 104, 104a, 105, 105a Ferroelectric capacitors 106a, 106b Data signal line precharge circuits 107a, 107b Sense amplifier circuits 108a, 108b, 108c , 108d Reference level generating circuit 109 Flip-flop 110, 111 N-channel transistor 112, 113 P-channel transistor 114, 115 Memory cell selection transistor 116, 116a, 116b Data signal line precharge Balance control circuit 117, 118 Transistor for precharging data signal line 119 Transistor for data signal line balance 21,121a, 121b, 121c, 121d the data signal line capacitance adjusting circuit 122,122a data signal line capacitance adjusting transistor 123,123a data signal line capacitance adjusting capacitor 124a, 124b, 124c, 124d, 124e,
124f, 124g, 124h Transfer gate for data signal line connection 125 Precharge transistor for data signal line capacitance value adjustment circuit Q Ferroelectric polarization charge V Voltage Ve Voltage applied between electrodes of ferroelectric capacitor Q ₀ , Q ₁ Ferroelectric Charge output from the body capacitor Qr Residual polarization charge of ferroelectric VDL0 Data signal line voltage initial value VDL Data signal line voltage final value VS0 Memory cell internal node voltage initial value VPL0 Plate line voltage initial value (plate drive type) VPL Plate line voltage final value (plate drive type) VPLC Plate line voltage value (plate non-drive type) Qi Initial total charge of memory cell array system Qf Final total charge of memory cell array system EC Coercive electric field of ferroelectric VC Ferroelectric Coercive voltage Vm Plate line intermediate voltage set value VSIG memory VSE Minimum signal voltage value at which sense amplifier can normally amplify data CD Data signal line parasitic capacitance value CS Paraelectric component capacitance value of ferroelectric capacitor CC Additional data signal line capacitance value adjustment Capacitance value VCC Power supply voltage VBOOT Power supply voltage GND Ground voltage n Number of memory cells connected per data signal line

Claims (34)

(57) [Claims] 1. A ferroelectric capacitor using a ferroelectric material, a data signal line for inputting / outputting data, a selection signal line selected according to an address signal, the ferroelectric capacitor and the data signal line And switch means selectively controlled by the selection signal line, the polarization state of the ferroelectric capacitor corresponding to the stored data, and a non-zero value between both electrodes of the ferroelectric capacitor. Utilizing that the current flowing between the ferroelectric capacitor and the data signal line when the first voltage is applied differs depending on the polarization state of the ferroelectric capacitor,
A memory cell for reading stored data by detecting a difference due to the stored data of the current, or by detecting a difference in voltage appearing on the data signal line due to the difference in the current, the plurality of memory cells A unit memory that inputs the data signal line connected thereto to a current type sense amplifier which is a circuit for detecting a current difference due to the stored data or a voltage type sense amplifier which is a circuit for detecting the voltage difference. A cell array, a memory cell array in which a plurality of the unit memory cell arrays are arranged, the selection signal line is set to a second voltage at which the memory cell is selected, and data is read from the memory cell onto a data signal line. The voltage variation of the data signal line due to factors other than the current caused by the polarization of the ferroelectric capacitor. To, to read data from the memory cell, before selecting the memory cell,
Or means for simultaneously selecting and temporarily changing the parasitic capacitance value of the data signal line to which the data of the memory cell is output, and thereafter, the data from the memory cell is read onto the data signal line. Means for restoring the parasitic capacitance value of the data signal line to the initial value. 2. The memory cell according to claim 1, wherein the memory cell comprises one ferroelectric capacitor.
It is characterized by comprising a transistor and one transistor
The ferroelectric memory device according to claim 1. 3. The memory cell according to claim 2, wherein the memory cell comprises two ferroelectric capacitors.
A contractor comprising a sita and two transistors
The ferroelectric memory device according to claim 1. 4. The memory cell comprises one ferroelectric capacitor and one transistor, and connects first and second terminals of the ferroelectric capacitor to a source terminal and a plate line of the transistor, respectively. Connecting the drain terminal of the transistor to a data signal line;
3. The ferroelectric memory device according to claim 2, wherein a gate terminal of said transistor is connected to a selection signal line. 5. The memory cell comprises two ferroelectric capacitors and two transistors, wherein the first and second terminals of the first ferroelectric capacitor are respectively connected to a source terminal of the first transistor and a first terminal of the first transistor. Connect to the plate wire,
A drain terminal of the first transistor is connected to a first data signal line, and a gate terminal is connected to a selection signal line;
The first and second terminals of the second ferroelectric capacitor are:
4. The semiconductor device according to claim 3, wherein a source terminal and a plate line of the second transistor are respectively connected, a drain terminal of the second transistor is connected to a second data signal line, and a gate terminal is connected to a selection signal line. The ferroelectric memory device according to claim 1. 6. The memory cell according to claim 1, wherein said memory cell comprises a flip-flop circuit comprising a plurality of transistors or a combination of a plurality of transistors and passive elements, and one or more ferroelectric capacitors. The ferroelectric memory device according to claim 1. 7. The memory cell includes a flip-flop circuit including a plurality of transistors or a combination of a plurality of transistors and a passive element, and two ferroelectric capacitors, and has two terminals of the flip-flop circuit. A data signal line is connected to a signal line pair connected to the current type sense amplifier or the voltage type sense amplifier via first and second transfer gates, respectively, and the data signal line is connected to a third and fourth transfer gate, respectively. And a first terminal of each of the two ferroelectric capacitors, a gate control signal terminal of each of the first and second transfer gates connected to a selection signal line, A gate control signal terminal of the transfer gate is connected to a control signal line, and a second terminal of each of the two ferroelectric capacitors is connected. The ferroelectric memory device according to claim 6, characterized in that connected to the plate line. 8. A method for controlling the operation of a ferroelectric memory device according to claim 1, wherein when reading data stored in said memory cell, a voltage of a data signal line is read. Is set to the third voltage, the voltage of the plate line is driven from the fourth voltage, which is the voltage before the data read operation, to a fifth voltage different from the third voltage, and the voltage of the selection signal line is stored in the memory. The memory cell is stored on the data signal line by setting a second voltage at which the cell is selected and causing a voltage difference between the first and second terminals of the ferroelectric capacitor. And outputting a signal corresponding to the stored data. 9. The method for controlling the operation of a ferroelectric memory device according to claim 2, wherein when reading data stored in the memory cell, the voltage of the data signal line is changed to a third voltage. And the voltage of the plate line is driven from the fourth voltage, which is the voltage before the data read operation, to a fifth voltage different from the third voltage, and the voltage of the selection signal line is changed to the state where the memory cell is in the selected state. By setting a second voltage to generate a voltage difference between the first and second terminals of the ferroelectric capacitor, the data signal line corresponds to the data stored in the memory cell. A method for controlling operation of a ferroelectric memory device, characterized by outputting a signal. 10. A method for controlling the operation of a ferroelectric memory device according to claim 3, wherein when reading data stored in the memory cell, the voltage of a data signal line is changed to a third voltage. Voltage and set the plate wire voltage to
The fourth voltage which is the voltage before the data read operation is driven to a fifth voltage different from the third voltage, and the voltage of the selection signal line is set to the second voltage at which the memory cell is in a selected state, A voltage difference is generated between the first and second terminals of the ferroelectric capacitor to output a signal corresponding to data stored in the memory cell on the data signal line. An operation control method for a dielectric memory device. 11. The data signal line has a parasitic capacitance of CD,
Let the capacitance value of the paraelectric component of the ferroelectric capacitor be C
S, the coercive voltage, which is a value obtained by multiplying the coercive electric field of the ferroelectric capacitor by the film thickness of the ferroelectric, is VC, the fourth voltage is VPL0, the fifth voltage is VPL, and the third voltage is VPL. Assuming that the voltage is VDL0 and the voltage before the data read operation at the node connecting the switch means in the memory cell and the ferroelectric capacitor is VS0, By setting the parasitic capacitance value CD of the data signal line so that the following relationship is established, the data signal line voltage fluctuation due to driving the plate line at the time of data reading is suppressed, and the second capacitance of the ferroelectric capacitor is reduced. 9. An electric field greater than a coercive electric field is applied between the first and second electrodes.
11. The operation control method for a ferroelectric memory device according to any one of claims 1 to 10. 12. A method for controlling the operation of a ferroelectric memory device according to claim 1, wherein:
When reading data stored in the memory cell, the voltage of the data signal line is set to a third voltage, and the voltage of the plate line is set to a constant voltage and a sixth voltage different from the third voltage. The voltage of the selection signal line is set to a second voltage at which the memory cell is selected, and a voltage difference is generated between the first and second terminals of the ferroelectric capacitor, whereby the data signal is set. An operation control method for a ferroelectric memory device, characterized by outputting a signal corresponding to data stored in the memory cell on a line. 13. A method for controlling the operation of a ferroelectric memory device according to claim 2, wherein when reading data stored in said memory cells, a voltage of a data signal line is read. 3, the voltage of the plate line is set to a sixth voltage that is constant and different from the third voltage, and the voltage of the selection signal line is set to a second voltage at which the memory cell is selected. Setting a voltage difference between the first and second terminals of the ferroelectric capacitor to output a signal corresponding to the data stored in the memory cell on the data signal line. An operation control method for a ferroelectric memory device, characterized by: 14. A method for controlling the operation of a ferroelectric memory device according to claim 3, wherein when reading data stored in said memory cell, a voltage of a data signal line is changed to a second voltage. 3, the voltage of the plate line is set to a sixth voltage that is constant and different from the third voltage, and the voltage of the selection signal line is set to a second voltage at which the memory cell is selected. Setting a voltage difference between the first and second terminals of the ferroelectric capacitor to output a signal corresponding to the data stored in the memory cell on the data signal line. An operation control method for a ferroelectric memory device, characterized by: 15. The data signal line having a parasitic capacitance of CD,
Let the capacitance value of the paraelectric component of the ferroelectric capacitor be C
S, the coercive voltage, which is a value obtained by multiplying the coercive electric field of the ferroelectric capacitor by the film thickness of the ferroelectric, is VC, the sixth voltage is VPLC, the third voltage is VDL0, and the When the voltage before the data read operation at the node connecting the switch means and the ferroelectric capacitor is VS0, between the respective amounts: By setting the parasitic capacitance value CD of the data signal line so that the following relationship is established, the data signal line voltage fluctuation at the time of data reading is suppressed, and the first and second electrodes of the ferroelectric capacitor are set. 15. The operation control method for a ferroelectric memory device according to claim 12, wherein an electric field greater than a coercive electric field is applied therebetween. 16. A signal voltage value read from the memory cell is VSIG, and a voltage resolution which is a minimum signal voltage at which the voltage type sense amplifier can normally amplify data is VS.
15. The operation control method for a ferroelectric memory device according to claim 8, wherein when E is set, a relationship of VSIG ≧ VSE is established between the respective amounts. 17. The data signal line having a parasitic capacitance CD,
Let the capacitance value of the paraelectric component of the ferroelectric capacitor be C
S, when the remanent polarization charge of the ferroelectric capacitor is Qr, and the voltage resolution, which is the minimum signal voltage at which the voltage-type sense amplifier can normally amplify data, is VSE, 14. The operation control method for a ferroelectric memory device according to claim 9, wherein the parasitic capacitance value CD of the data signal line is set such that the following relationship is established. 18. The data signal line having a parasitic capacitance of CD,
Let the capacitance value of the paraelectric component of the ferroelectric capacitor be C
S, when the remanent polarization charge of the ferroelectric capacitor is Qr, and the voltage resolution, which is the minimum signal voltage at which the voltage-type sense amplifier can normally amplify data, is VSE, The parasitic capacitance value CD of the data signal line is set so that the following relationship is established.
4. The operation control method for a ferroelectric memory device according to item 1. 19. A ferroelectric memory device according to claim 11, wherein said select signal line is set to a voltage at which a memory cell is selected, and data is read from said memory cell to a data signal line. Data signal line parasitic capacitance value CD
13. A ferroelectric memory device comprising: means for setting the relational expression to satisfy the relational expression according to claim 11. 20. A ferroelectric memory device according to claim 15, wherein said select signal line is set to a voltage at which a memory cell is selected, and data is read from said memory cell to a data signal line. Data signal line parasitic capacitance value CD
17. A ferroelectric memory device comprising: means for setting the relationship as described in claim 15. 21. The ferroelectric memory device according to claim 17, wherein said selection signal line is set to a voltage at which a memory cell is selected, and data is read from said memory cell to a data signal line. Data signal line parasitic capacitance value CD
18. A ferroelectric memory device comprising: means for setting the relationship so as to satisfy the relational expression according to claim 17. 22. The ferroelectric memory device according to claim 18, wherein said selection signal line is set to a voltage at which a memory cell is selected, and data is read from said memory cell to a data signal line. Data signal line parasitic capacitance value CD
19. A ferroelectric memory device comprising: means for setting the relational expression to satisfy the relational expression according to claim 18. 23. As a means for setting a parasitic capacitance value CD of said data signal line, a circuit comprising switch means and a capacitor selectively controlled by a control signal is connected to said data signal line, and said switch is used when data is read. 12. The data signal line parasitic capacitance CD is set so as to satisfy the relational expression according to claim 11, by connecting the data signal line and the capacitor with the means in a selected state. 20. The ferroelectric memory device according to item 19. 24. As a means for setting a parasitic capacitance value CD of said data signal line, a circuit comprising switch means and a capacitor selectively controlled by a control signal is connected to said data signal line, and said switch is used when data is read. 16. The data signal line parasitic capacitance value CD is set so as to satisfy the relational expression according to claim 15 by connecting the data signal line and the capacitor with the means in a selected state. 21. The ferroelectric memory device according to 20. 25. As a means for setting a parasitic capacitance value CD of said data signal line, a circuit comprising switch means and a capacitor selectively controlled by a control signal is connected to said data signal line, and said switch is used when data is read. The data signal line parasitic capacitance value CD is set so as to satisfy the relational expression according to claim 17, by connecting the data signal line and the capacitor with the means in a selected state. 22. The ferroelectric memory device according to 21. 26. As a means for setting a parasitic capacitance value CD of said data signal line, a circuit comprising switch means and a capacitor selectively controlled by a control signal is connected to said data signal line, and said switch is used when data is read. 19. The data signal line parasitic capacitance value CD is set so as to satisfy the relational expression according to claim 18, by connecting the data signal line and the capacitor with the means in a selected state. 23. The ferroelectric memory device according to 22. 27. A ferroelectric memory device according to claim 23, wherein one or a plurality of memory cells are used as a circuit comprising said switch means and a capacitor. 28. The operation control method for a ferroelectric memory device according to claim 23, wherein after reading data from a selected memory cell, said current type sense amplifier or voltage type sense amplifier is read. Activating the switch means to deselect the switch means before performing the amplification operation of the read data, during the amplification operation, or after completion of the amplification operation, and disconnecting the capacitor from the data signal line. An operation control method for a ferroelectric memory device. 29. The operation control method for a ferroelectric memory device according to claim 23, wherein data input from outside the ferroelectric memory device is written to a selected memory cell. In this case, the operation control method of the ferroelectric memory device is characterized in that the switch means is in a non-selected state and the capacitor and the data signal line are in a non-connected state. 30. As means for setting the parasitic capacitance value CD of the data signal line, a plurality of data signal lines are connected via switch means selectively controlled by a control signal, and the switch means is selected when data is read. 20. As a state, by connecting the adjacent data signal lines to each other, a data signal line parasitic capacitance value CD is set so as to satisfy the relational expression described in claim 11.
The ferroelectric memory device according to claim 1. 31. As a means for setting a parasitic capacitance value CD of the data signal line, a plurality of data signal lines are connected via switch means selectively controlled by a control signal, and the switch means is selected when data is read. 21. The data signal line parasitic capacitance value CD is set so as to satisfy the relational expression described in claim 15 by connecting the adjacent data signal lines to each other as a state.
The ferroelectric memory device according to claim 1. 32. As a means for setting the parasitic capacitance value CD of the data signal line, a plurality of data signal lines are connected via switch means selectively controlled by a control signal, and the switch means is selected when data is read. 22. The ferroelectric material according to claim 21, wherein the adjacent data signal lines are connected to each other to set a data signal line parasitic capacitance value CD so as to satisfy the relational expression described in claim 17. Memory device. 33. As a means for setting the parasitic capacitance value CD of the data signal line, a plurality of data signal lines are connected via switch means selectively controlled by a control signal, and the switch means is selected when data is read. 23. The ferroelectric material according to claim 22, wherein the data signal line parasitic capacitance value CD is set so as to satisfy the relational expression according to claim 18 by connecting the adjacent data signal lines to each other as a state. Memory device. 34. The operation control method for a ferroelectric memory device according to claim 30, wherein after reading data from a selected memory cell, said current type sense amplifier or voltage type sense amplifier is read. Activating, before performing the amplification operation of the read data, during the amplification operation, or after the completion of the amplification operation, the switch unit is set to the non-selection state, and the plurality of data signal lines are set to the non-connection state. An operation control method for a ferroelectric memory device, comprising: