JP3186075B2 - Macrocell separation test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a macro cell separation test method for verifying and evaluating a core microcomputer type ASIC in which a macro cell is incorporated in a library, and more particularly to a separation test of a macro cell incorporated as a hardware macro.

[0002]

2. Description of the Related Art Conventionally, this type of macro cell separation test method is designed manually as a part of a user-defined random logic, or a test circuit and a dedicated test terminal are prepared in a macro cell in advance. Has been dealt with.

[0003]

In the conventional isolation test method described above, when the isolation test circuit and the terminal are included in the macro cell, the development of the macro cell becomes complicated, and it takes time to make a library. From the standpoint of the user, the appearance and specifications of the familiar standard product are significantly different, and in particular, the bidirectional pins are separated and the design of the peripheral circuit must be changed, causing errors in the design. Also, the macro cell is equivalent to a standard product, and the separation circuit is designed manually, but it needs to be considered outside the original user-defined random logic area, and the validity of the separation circuit must be verified by simulation etc. There are drawbacks.

[0004] It is an object of the present invention to solve these problems,
It is an object of the present invention to provide a macro cell separation test method in which a separation test can be automatically and reliably performed by tracing a connection relationship with an external terminal from a macro cell pin side.

[0005]

Configuration of the present invention According to an aspect of the leave a library excised large scale integrated circuit products as a macrocell, in that take the ASIC into a single chip in combination with a user-specific random logic, the macrocell in macro cell separation testing method for testing by separating the Ma circuit connection information inputted from the external terminal
In a format where connection information up to the cross-cell pin can be traced
Graph-structured data consisting of elements, pins, and nets
Data into a plurality of macro cells to be converted into one chip .
Define and insert a decoder that can be individually handled
And use previously confirmed individual macrocell patterns.
It is determined whether the connected node is bidirectional, input or output by referring to the pin information of a macro cell defined as a library so that it can be used. the to switch the output of the external terminal, the interactive node into a formed circuit input and output buffers, and this is when the input or output node, external only when the test mode to the output node Decoding from terminal
Insert the separation test circuit for validating the output of the de macrocell, a constant input macrocell to said input node
Circuit selector circuit insert were automatically insert these steps in the final one-chip circuitry executed for all the macro cell for the separation test switching to define, minutes
External terminal information and macros assigned for remote test
Outputs of the decoding information as a list, verification by individually simulating each macrocell in the one-chip 及
And device evaluation on a device tester can be executed .

[0006]

FIG. 1 is a flow chart for explaining an embodiment of the present invention. FIG. 2 is a block diagram showing a circuit configuration for explaining the present embodiment, FIG. 3 is a block diagram when the test mode of FIG. 2 is set, and FIG. 4 is a circuit diagram specifically explaining FIG.

First, in step S1, circuit connection information for which verification at the one-chip level has been completed is input. In this case, in a circuit as shown in FIG.
The configuration of C10 is shown, and M1 to M3 macro cells (M1 to M3) are shown.
M3) 11 and user-defined random logic 12 are included. Here, the circuit connection information is changed to internal data having a graph structure that can trace the connection relations as input.

Next, in step S2, a test mode is set, macro cells 11 are searched from internal data, a test mode is set according to the number of used macro cells, and a circuit is reconfigured so that individual macro cells can be separated and tested. FIG. 3 shows a block diagram after this reconfiguration. Here, the decoder 21 is configured to separate the macro cells (M1 to M3) 11 individually, and the chip select (CS) is selected by the selector 22 by the selector 22 according to the state of the test terminal 31 for setting the separation test mode. Set from the side or from the separation test mode side.

Next, in step S3, a separation node is extracted. That is, a net for tracing from the pin on the macrocell 11 side to the branch is extracted from the internal data.

In the next step S4, a conditional branch is made to determine whether the attribute of the pin to be traced is bidirectional. If this is bidirectional, the process proceeds to step S5, where the external test terminal is connected to the bidirectional external terminal and only when the input / output switching control uses the input / output switching control signal (DC) 34 of the macro cell. This is checked because it can be used as the terminal 31. On the other hand, if the condition is not satisfied, a new external terminal for separation test 31 is added in step S7 as shown in FIG. A bidirectional separation buffer 33 is inserted between the macrocell 11 and the external terminal or the user-defined random logic 12 so as to insert a test separation circuit.
And separate it into input and output nodes.

Next, in step S7, input / output external terminals are set. That is, it is checked whether or not the input / output pins of the macrocell 11 are directly connected to the buffer for the external terminal. If not, the external terminal and the buffer for the isolation test are added. Since the bidirectional node is separated into input and output by the above procedure, the step S
In the setting of the output node test circuit of No. 8, buffer 3 is used so as not to affect the internal user-defined random logic.
2 is added, and in the next step S9, an input node test circuit is set. Here, a selector 22 for switching the signal 12 from the internal user-defined random logic and the signal from the separation test external terminal 23 is added to reconfigure the circuit. I do.

From the extraction of the separation node in step S3 to the setting of the input node test circuit in step S9, the circuit configuration for separation test of each macro cell in one chip is defined by repeating the macro cell several times in step S12. Furthermore, the block added during the processing by the insertion block and the output of the terminal list in step S10,
A list of changed nodes and added / changed external terminals is output, and finally, a macro cell separation test circuit reconfigured by the output of the circuit connection information in step S11 is stored.

If the library is prepared so that the macro cell 11 does not have a bidirectional pin, the procedure of bidirectional separation in step S4, setting of bidirectional external terminals in step S5, and insertion of the bidirectional separation buffer in step S6 are performed. The flow is excluded, and the setting of the isolation test circuit of the macro cell can be performed more easily.

[0014]

As described above, according to the present invention, a macro cell separation test is uniformly performed by searching for a branch from the pin side of a macro cell in a library and tracing the connection relationship with an external terminal. ASIC developers use macro cells equivalent to the use of standard products, design and verify the user-defined random logic part, and perform one-chip system verification without affecting the user-defined random logic side. This alone has the effect that the operation of the macrocell can be evaluated and guaranteed by the defined isolation test circuit.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an embodiment of the present invention.

FIG. 2 is a block diagram showing a basic structure of a core microcomputer type ASIC.

FIG. 3 is a block diagram showing an image when a test mode is set.

FIG. 4 is a circuit diagram showing a macro cell separation test circuit.

[Explanation of symbols]

 S1 to S12 Processing procedure 11 Macro cell 12 User-defined random logic 21 Decoder 22 Selector 23 Separation test external input / output terminal 31 Separation test external terminal 32 Buffer 33 Bidirectional separation buffer 34 Macro cell input / output switching control signal terminal

Claims (1)

(57) [Claims] 1. A large-scale integrated circuit product is cut out as a macro cell, made into a library, and combined with a user-specific random logic to be made into one chip to form an ASIC.
In the macro cell separation test method of performing a test by separating the macro cell when performing the connection, the input circuit connection information, elements, pins, and the like of the connection information from the external terminal to the macro cell pin can be traced and converted into data constituted graph structure net, is the one chip
Decoders that are individually adaptable from multiple macro cells are defined and inserted, and individual macros already identified
The pattern of the macrocell as a library so that it can be used
By referring to the defined macro cell pin information
Thus connected nodes to determine whether two-way or input or output, which is when the bidirectional switching the output of said external terminals
In order to switch, the bidirectional node is converted into a circuit composed of input and output buffers, and when this is an input or output node, the output node is in a test mode.
Check macro cell output decoded from external terminal
Insert the isolation test circuit to
For separation test switching to define macro cell input
Insert the selector circuit, these steps in the execution finally 1-chip circuitry for all the macrocell
The automatically inserted circuit, the external terminal information allocated for the isolation test, and the decode information of each macro are output as a list, and each macro cell in the one chip is individually simulated.
Macrocell separation testing method being characterized in that so as to enable perform device <br/> evaluation on verification及beauty device tester by Shon.