JP3183731B2 - Bus system and bus bridge system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus system and a bus bridge system having a hierarchical structure, and more particularly, to a mutual bus link system.

[0002]

2. Description of the Related Art As a technique for interconnecting buses, for example, IEEE Std P1014.1 / Draft0.6 June 27,1991, p.
p. Futurebus + / VME64 Bridge described in 25-29
Is known. Here, two buses (Futurebus + and VME6
It describes how to connect 4) with a bus bridge. The configuration of the bus bridge consists of a Futurebus + interface, a VME64 interface, and a bus transaction transfer.

An important function here is a bus transaction transfer, whose main logical configuration is (1) Futurebus + to VME64 data channel (2) VME64 to Futurebus + data channel (3) Futurebus + to VME64 event channel (4 ) It consists of VME64 to Futurebus + event channel.

[0004] Futurebus + to VME64 (VME64 to Futurebus
+) The data channel is a channel for accessing resources on VME64 (Futurebus +) from modules on Futurebus + (VME64). Futurebus + to VME64 (VME64
to Futurebus +) event channel is Futurebus + (VM
Events from modules on E64) are sent to VME64 (Futurebu
s +) to the above module. This allows, for example,
The interrupt from VME64 is converted into a transaction to Futurebus + on the VME64 to Futurebus + event channel and transmitted to Futurebus +. Also, for example, data from VME64 is
It is converted to the data format to urebus + and transmitted to Futurebus +.

[0005]

By using the above-mentioned prior art, data can be exchanged between two different types of buses. However, in a system in which a plurality of branch buses are connected via a trunk bus. Does not consider transmitting and receiving data between branch buses via a trunk bus.

That is, in a bus system in which a plurality of branch buses to which modules are connected are connected via a high-speed bus, continuous long data transmitted from a source module is transmitted by a bus converter interconnecting the buses. However, in order to correspond to a high-speed bus, the data is divided into a plurality of short block data and relayed through the high-speed bus. On the other hand, since the short block data received from the high-speed bus in the bus conversion unit of the receiving module is relayed to the branch bus of the destination as it is, the receiving module receives the short block data and receives the original short block data. Long data units are not saved. Further, the receiving-side bus converter mixes a large number of different short block data received from a large number of transmission sources and relays the data to the branch bus, so that the receiving-side module converts the various block data in correspondence with the transmission source. Must be reassembled. Therefore, there is a problem that processing becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem, and in a system employing a hierarchical bus system, a data format is transparently transmitted between modules connected to buses at distant positions without being aware of an intervening high-speed bus. It is an object of the present invention to provide a bus system and a bus bridge system in which a bus protocol is stored and data can be exchanged mutually.

[0008]

In order to achieve the above object, the present invention comprises a trunk bus and a plurality of branch buses,
A bus connection circuit for connecting the branch bus and the trunk bus;
Instead, the two branch buses are connected between the two bus connection circuits.
In a linking bus system, the bus connection circuit includes:
Data from the branch bus connected to the bus connection circuit
Status of other branch buses that are transfer destinations for transfer requests
Check that the other branch buses are not busy.
The bus for transferring data to the other branch bus.
Permit the connection of the bus to the baseline bus and all other buses.
Notify the bus connection circuit and report from other bus connection circuits
Therefore, it was confirmed that the other branch bus was busy
Until the bus is released.
Means for prohibiting the connection to the bus connection, and the bus connection
The branch bus connected to the circuit is connected to another bus connection circuit.
When it is the destination of data transfer by the following branch bus,
A second means for permitting connection of the trunk bus to the branch bus;
And a step.

The present invention also provides a trunk bus and a plurality of branch buses.
Bus connecting the branch bus and the trunk bus.
Connection circuit between the two bus connection circuits.
Bus bridge method of bus system linking branch buses
Connecting the branch bus and the trunk bus,
One module connected to the branch bus and the other branch
Data to and from the other module connected to the
When transmitting and receiving, one of the bus connection circuits is connected to one of the bus connection circuits.
Checks the bus acquisition request of one of the branch buses by the module.
Stop, and transmit the arbitration result to the other corresponding bus connection circuit.
Reaches one of the modules on behalf of the other module.
Data from the main bus and convert it to the data format of the trunk bus.
To the main bus, and the other bus connection circuit
Sent from the bus connection circuit via the trunk bus
Receives data and converts it to the data format of the other branch bus
On behalf of one of the modules to the other branch bus
To transfer.

Further, the present invention provides a trunk bus and a plurality of branch lines.
A bus and connects the branch bus and the trunk bus.
A bus connection circuit between the two bus connection circuits;
Bus bridge of the bus system linking the two branch buses
One bus connection circuit and the other bus connection circuit
When data is exchanged with the connection circuit,
And the other bus connection circuit
The transmission and reception of data with the road is prohibited.

[0011]

[Function] A plurality of branch buses are connected via a trunk bus.
The two branch buses are transparently linked as one branch bus. The link between the branch buses is performed as follows by a bus connection circuit that connects the branch bus and the trunk bus.

One bus connection circuit operates on behalf of one branch bus on the other branch side, and the other bus connection circuit substitutes one branch side on the other branch bus. Operate. And during the data transfer period,
Bus occupied between one branch side and the other branch side
So that this other branch from the other branch side
It is possible to avoid data transfer to the side. Immediately
That is, one branch line side is the other
This is a style that occupies the branch line side.
Data is transferred from other branch lines other than
Can be prevented.

[0013]

[0014]

Embodiments of the present invention will be described below with reference to the drawings. First, an example of the bus system will be described.

The purpose of this embodiment is to provide a hierarchical bus architecture in which a plurality of low-speed buses are connected via a high-speed bus. (Many-to-many) connection and transparently imitate and connect to one low-speed bus without disturbing the low-speed bus protocol. The term "transparent" as used herein means that when a module on one branch bus is viewed from a module on the other branch bus, this module appears to be on the same branch bus, and there is an interposition. The main bus becomes invisible between modules.

First, a bus system composed of a low-speed bus,
A method for increasing the scale of a hierarchical bus system including a high-speed bus and a low-speed bus will be described.

FIG. 2 shows a system in which a plurality of modules MD are connected to one low-speed bus 2. Also,
FIG. 3 shows a module M in the system having such a configuration.
4 schematically shows a state in which data transfer is being performed between Ds.

As shown in FIG. 3, the module MD
When data transfer is being performed between # 0 and the module MD # 2, the low-speed bus 2 is occupied by these and the other modules MD cannot transfer data. For this reason, the module MD that cannot transfer data is in a transfer waiting state. However, if the transfer waiting time is long, there is a problem that the data buffer overflows. In addition, when viewed over a long time, the low-speed bus 2 can be shared by two or more pairs. Naturally, however, the total transfer throughput as viewed from the entire system has the bus throughput of one low-speed bus 2. Will be.

In such a bus system, the reason why the module MD connected to the low-speed bus 2 is diverted as it is to improve the transfer throughput of the entire system is as shown in FIG.
As shown in (1), it is conceivable to adopt a configuration in which the low-speed bus 2 is divided and connected to the high-speed bus 1 via the bus converter BC. This simply means that the capacity can be increased to the capacity of the low-speed bus 2 times the number of divisions, and the high-speed bus 1 accommodates this capacity.

It is needless to say that the high-speed bus 1 is positioned as a trunk bus and the low-speed bus 2 is positioned as a branch bus. Therefore, in the following, a high-speed bus,
The description will proceed with the term low speed bus.

In the embodiment described below, one module MD is connected to each low-speed bus 2 for the sake of simplicity, but a plurality of modules MD are connected. It is the same even if it is.

In the following, a description will be given of a problem which occurs when data is transferred between modules in a bus system having a hierarchical structure as shown in FIG. 4, and then an embodiment of the present invention which has solved the problem will be described. .

Normally, a module MD without a CPU
Examples of a device that is effective by performing data transfer between them include a communication device that connects networks to each other. Each module MD has a communication port,
In the case where data received from one communication port is relayed to the other communication port, if data is directly transferred between the modules MD without going through the CPU, the relay performance will be improved. As a method of further improving the relay performance, there is a method of sending data without exchanging buffer information between modules MD. in this case,
The data is transmitted in packet units, which are communication data units. This is because buffer management is usually performed on a packet-by-packet basis, and if a packet is divided, buffer processing becomes complicated. Therefore, the management of the packet buffer is performed by the receiving module.

In such an apparatus, according to this embodiment, the transfer source module does not care about the buffer address in the destination module, but simply transfers data to the destination module, and transfers the data to the destination module (reception side). In response to this, the module takes a transfer method of storing the data at the corresponding buffer address while managing the buffer, thereby reducing the overhead by transmitting and receiving the mutual buffer management information and improving the performance. In the communication device, the buffer management is usually performed on a packet basis, so that if the transfer data unit described above is performed on a packet basis, the processing is simplified.

As described above, in this embodiment, the format of the transfer data is burst data that is long and continuous according to the communication packet.

Next, a method of applying the above-described basic transfer method to a hierarchical bus configuration as a measure for increasing the transfer capacity as described above will be described.

First, FIG. 5 shows a problem that occurs when data is transferred between modules MD by a normal bus connection method.

Now, the module MD # 0 on the low-speed bus 2
However, as described above, the destination is set to, for example, the module MD # 2, and data is transmitted in packet length units. At the same time, the modules MD # 1 and MD # 5 also transfer the same module MD # 2. It is assumed that data is transferred as a destination.

Since the same amount of data can be transferred in a short time on the high-speed bus 1, the source module MD #
Bus conversion units BC # corresponding to 0, # 1, MD # 5, respectively.
At 0, BC # 1, and BC # 5, continuous data received from the low-speed bus 2 is divided into short block data lengths and transmitted onto the high-speed bus 1. Therefore, on the high-speed bus 1, short block data from each of the bus converters BC # 0, BC # 1, and BC # 5 is mixed. Here, on the high-speed bus 1, it is possible to carry the traffic of a plurality of branch buses 11 by the bus capacity, thereby improving the system throughput. However, there are the following problems.

That is, the bus conversion unit BC # 2 on the receiving side
Transmits data received from the high-speed bus 1 to the low-speed bus 2 (# 2)
To the receiving module MD # 2 in this case.
Receives mixed short block data. Therefore, if a packet is divided and transferred, packets from many sources will arrive at the same destination in a mixed manner, and therefore, the receiving side will buffer many source modules at once. , And reassembly of the packet is required, which complicates the processing and increases the hardware amount of the transfer control unit.

Therefore, in order to solve such a problem, in one embodiment of the present invention, during a packet transfer period,
The bus is occupied between the mutual modules MD. As a result, data transfer from another module MD to the same transfer destination can be avoided. That is, as described above with reference to FIG. 4, if a mode is adopted in which the low-speed bus 2 is exclusively used between the modules MD, the other modules M
Data can be prevented from being transferred from D.

Further, an embodiment of the present invention will be described with reference to FIG. 1 so that data transfer between a plurality of pairs of modules can be performed simultaneously in parallel.

Now, the same destination module M as in FIG.
A plurality of modules MD # 0, MD # 1,
It is assumed that MD # 5 is making a data transfer request. In this case, if the module MD # 0 acquires the transfer right first, the low-speed buses 2 (# 0) and (# 2) are occupied.

From the viewpoint of the bus link configuration, the transmission source low-speed bus # 0 and the transfer destination low-speed bus # 2 are connected to the high-speed bus 1
This is made possible by transparently connecting as a single low-speed bus via the. That is, from the viewpoint of the transmission source module MD # 0, the destination module MD # 2 has its own low-speed bus 2
(# 0), while the transmission source module MD # 0 appears to be connected to its own low-speed 2 bus (# 2) from the viewpoint of the receiving (destination) module MD # 2. Looks like.

In this case, the modules MD # 1 and MD # 5
Is the same as issuing a bus request and waiting for bus acquisition.

On the other hand, separately from this, another low-speed bus 2 (#
3) The (module MD # 3) and the low-speed bus 2 (# 4) (module MD # 4) may be transparently connected to one. In such a state, two sets of transparent low-speed buses 2 are bundled by one high-speed bus 1. The bus capacity of the system is equal to the bus capacity of the linked transparent low-speed bus x the number of links as long as the capacity of the high-speed bus 1 permits. Therefore, as compared with the data transfer between a pair of module MDs as shown in FIG. 4, the data transfer between a plurality of pairs of modules MD becomes possible, the bus capacity increases, the bus waiting time decreases, and the throughput decreases. Be faster. Further, the problem that continuous data is divided as described with reference to FIG. 5 can be solved.

Next, a specific method for realizing the above-mentioned link will be described. Here, for example, the modules MD # 0 and MD # 1 in FIG.
It is assumed that the module MD # 0 has obtained the priority, and the procedure will be described for each step with reference to FIG.

1) Module MD # 0 is connected to low-speed bus 2 (#
Assert the request BR to 0). 2) The bus bridge BB # 0 performs the arbiter function of the low-speed bus 2 (# 0) and returns the bus grant BG. 3) Since the module MD # 0 has acquired the low-speed bus 2 (# 0), it sends out the address ADR. 4) The bus bridge BB # 0 determines the destination module MD # 2 based on the address ADR, and determines the destination low-speed bus 2 based on the state information on all low-speed buses owned by itself.
Check that (# 2) is not busy. 5) Bus bridge BB # 0 broadcasts # 0 / # 2 connection to all bus bridges BB. That is, the low-speed bus 2
The state of (# 0) is encapsulated by data on the high-speed bus 1 and transmitted. 6) The bus bridge BB # 0 performs a slave function for the low-speed bus 2 (# 0), and the module MD # 0
While taking a handshake with the bus bridge BB # 0,
The packet data DATA is transmitted to the low-speed bus 2 (# 0). 7) The bus bridge BB # 0 converts the data DATA into the data format of the high-speed bus 1, and
Transfer to B # 2. That is, continuous data on the low-speed bus 2 (# 0) is encapsulated with data on the high-speed bus 1 and transmitted. 8) The bus bridge BB # 2 asserts a bus busy to the low speed bus 2 (# 2). 9) The bus bridge BB # 2 converts the data DATA received from the high-speed bus 1 into a low-speed bus data format. 10) The bus bridge BB # 2 sends the data DATA to the low-speed bus 2 (# 2) in place of the low-speed bus master function. 11) Module MD # 2 receives this. 12) The module MD # 0 releases the low-speed bus 2 (# 0) after the transfer of the data DATA is completed. 13) Bus bridge BB # 0 broadcasts # 0 / # 2 disconnection to all bus bridges BB. That is, the low-speed bus 2
This means that the state of (# 0) is encapsulated by the data on the high-speed bus 1 and transmitted. 14) The bus bridge BB # 2 negates the bus busy.

On the other hand, the module MD # 1 is also the module M
A bus request similar to the above steps 1) to 3) is made after the delay of D # 0, but at this time, the low-speed bus 2 (#
It is known from the above step 4) that 2) is occupied by the bus bridge BB # 0. Therefore, A) The bus bridge BB # 1 has a destination of the module MD #
After judging 2, the bus clear is asserted to the module MD # 1 to prompt the bus to be released. B) The module MD # 1 negates the bus request and releases the bus. C) The bus bridge BB # 1 does not permit the bus request from the module MD # 1 until step 13) described above. D) When the bus bridge BB # 2 is released in step 13), the bus bridge BB # 1 negates the bus busy. Subsequent steps are the same as above.

Next, the bus bridge BB in FIG. 1 for connecting the low-speed bus 2 and the high-speed bus 1 and realizing the low-speed bus link will be described with reference to FIG. FIG. 7 is a configuration diagram showing a logical function of the bus bridge BB.

In the figure, a bus bridge BB mainly converts an interface (H-BUSIF) with the high-speed bus 1, an interface (L-BUS IF) with the low-speed bus 2, and converts a data format from the low-speed bus 2 to the high-speed bus 1. A data channel (Data Ch) for converting a data format from the high speed bus 1 to the low speed bus 2; an event channel (Event Ch L => H) for converting an event from the low speed bus 2 to the high speed bus 1; Event channel that converts events to event 2 (Event Ch H =>
L) and registers (REGs) for storing bus bridge information.

The interface (L-BUS IF) includes bus arbitration (step 2 above), destination determination (step 4), slave substitution (step 6), and master substitution (step 10). ) Etc.

The event channel (Event Ch L => H) is a function for converting a low-speed bus event (signal line) into a high-speed bus event (transaction), a bus connection notification (step 5 described above), and a bus release notification. (Step 1 above
3)) and interrupt notification functions.

The event channel (Event Ch H => L) is a function for converting a high-speed bus event (transaction) into a low-speed bus event (signal line), and includes a bus busy signal assertion (step 8 described above) and a bus busy signal negation. (Step 14 described above).

The data channel (Data Ch) divides the low-speed bus data (continuous data; packet length) into a plurality of high-speed bus data (short block data; for example, 32 bytes) (step 7 described above) or continuously. It has a function of linking a plurality of high-speed bus data received by the low-speed bus data format (step 9 described above).

The registers (REGs) hold the interconnection state of all the low-speed buses (steps 4), 5), 13)).

[0047]

As described above, according to the present invention,
The following effects can be obtained.

The information processing device composed of a low-speed bus is divided into a plurality of low-speed buses to distribute the load, and these are bundled by the high-speed bus, so that the information processing device can be expanded to an information processing device having a large-capacity bus.

Since data can be transferred between a plurality of pairs of modules at the same time, transfer throughput is improved and transfer wait time can be reduced.

By linking branch buses separated from each other via a main bus transparently as a single branch bus,
There is no need to be aware of the main bus between distant modules.

And, even if the module
Even if a number of other modules request data transfer,
Are they transferred one by one in order of priority
Data of the bus connection circuit on the branch bus to which data is transferred.
Data processing can be simplified.

[0052]

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a bus system and a bus bridge system according to the present invention.

FIG. 2 is a diagram illustrating a bus system including a low-speed bus.

FIG. 3 is a diagram showing data transfer in the system shown in FIG. 2;

FIG. 4 is a diagram showing a bus system including a low-speed bus and a high-speed bus.

FIG. 5 is a diagram for explaining a problem in data transfer without a CPU in the system shown in FIG. 4;

FIG. 6 is a diagram showing an inter-bus connection sequence in the embodiment shown in FIG. 1;

FIG. 7 is a diagram showing a specific example of a functional configuration of a bus bridge in FIG. 1;

[Explanation of symbols]

 1 high speed bus 2 low speed bus BB bus bridge MD module

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroshi Sato 1st Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside Hitachi, Ltd.Kanagawa Plant (72) Inventor Toshiaki Koyama 1st Horiyamashita, Hadano-shi, Kanagawa Hitachi, Ltd.Kanagawa Plant (72) Inventor, Sadao Sawada 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa-ken, Japan Microelectronics Equipment Development Laboratory, Hitachi, Ltd. (56) References JP-A-2-92130 (JP, A) JP-A-2-2 58447 (JP, A) JP-A-62-193341 (JP, A) JP-A-4-135337 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28

Claims (3)

(57) [Claims] 1. A bus comprising a trunk bus and a plurality of branch buses,
A bus connection circuit for connecting the branch bus and the trunk bus;
Instead, the two branch buses are connected between the two bus connection circuits.
In a bus system for linking, the bus connection circuit is configured to transmit data from the branch bus connected to the bus connection circuit.
Status of other branch buses that are transfer destinations for transfer requests
Make sure, said other branch bus is sure a busy
The bus for transferring data to the other branch bus.
As well as allow the connection to the bus of the base line bus, all other
Notify the bus connection circuit and report from other bus connection circuits
Therefore, it was confirmed that the other branch bus was busy
Until the bus is released.
A first means for inhibiting allow connections to scan, the branch bus connected to the bus connection circuit other bus contact
The destination of data transfer by the branch bus connected to the connection circuit
The connection of the trunk bus to the branch bus is permitted.
And a second means . 2. A bus comprising a trunk bus and a plurality of branch buses.
A bus connection circuit for connecting the branch bus and the trunk bus;
Instead, the two branch buses are connected between the two bus connection circuits.
In the linking bus system, the branch bus and the trunk bus are connected, and one of the branch buses is connected.
Connected to one of the modules connected to
Exchange data with the other connected module.
In this case, one of the bus connection circuits is connected to one of the modules by one of the modules.
Arbitrates the bus acquisition request of the other branch bus, and arbitrates the arbitration result.
The signal is transmitted to the other corresponding bus connection circuit, and the other
Module on behalf of the module
To the trunk bus data format and transfer to the trunk bus.
The other bus connection circuit from one bus connection circuit.
Receiving data sent via the main bus, the other
Converted to branch bus data format,
Transfer to the other branch bus on behalf of
Bus bridge scheme. 3. A bus comprising a trunk bus and a plurality of branch buses,
A bus connection circuit for connecting the branch bus and the trunk bus;
Instead, the two branch buses are connected between the two bus connection circuits.
In a linking bus system, one bus connection circuit and the other bus connection circuit
When data transfer is performed, one and the other bus connections
The connection circuit is connected to other bus connection circuits.
Bus bridge characterized by prohibiting the transfer of data
formula.