JP3181159B2 - Error correction control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction control method, and more particularly to, for example, a mobile FM multiplex broadcast in which one frame is constituted by a plurality of interleaved blocks and product-coded data contained in one frame is received. The present invention relates to an error correction control method used for a receiver.

[0002]

2. Description of the Related Art Referring to FIG. 13, a frame structure of a mobile FM multiplex broadcast includes 272 block identification codes (hereinafter, simply referred to as "BIC") and (272, 190) shortened difference set cyclic codes. It is divided into product encoded packets. The BIC is composed of 16 bits and is used for synchronization between packets and between frames.
72, 190) 2 encoded with the shortened difference set cyclic code
A 72-bit packet follows.

In mobile FM multiplex broadcasting, (272, 19
0) Since the shortened difference set cyclic code is used after being product-coded, a packet included in one frame includes 190
82 for the data packet in which the information symbols (original data) are encoded and the 190 data packets in the vertical direction.
Parity packets. The data packet has 190 bits of data and 82 bits for the immediately preceding data.
And (parity) of the bits. The parity packet includes a (vertical) parity for 190-bit data in the vertical direction, and an 82-bit parity (vertical and horizontal) applied in the horizontal and vertical directions. Parity packets are interleaved between a plurality of data packets to prevent error rate degradation due to burst errors.

In the case of the (272, 190) shortened difference set cyclic code, error correction can be performed when the number of error bits at the time of reception is equal to or smaller than a specified value (8 when no variable threshold determination is used).
Error correction of bits or less can be performed). As a decoding circuit of a mobile FM multiplex broadcasting receiver that receives data having such a frame structure, a method of performing error correction control via an MPU according to Japanese Patent Application Laid-Open No. 4-64473 of the present applicant is the same as the present invention. Japanese Patent Laying-Open No. 5-115862 of the applicant proposes a system for performing error correction control without an MPU.

[0005]

However, these techniques have limitations in error correction. Hence,
A main object of the present invention is to provide an error correction control method that further improves error correction capability.

[0006]

The present invention divides data into a plurality of blocks each including block identification information, and generates an error correcting code having a property that information symbols appear as they are.
To encode each of the blocks using
Apply directional error correction coding and apply
In an error correction control method in a data transmission apparatus that transmits data by performing vertical error correction coding for straddling , (a) error correction failed in the first horizontal error correction Estimating first block identification information to be included in a block based on second block identification information included in a block that has been successfully corrected in the same horizontal error correction ; and (b) first horizontal error correction. Failed
First block identification information estimated for the selected block
The second error correction control method is characterized in that the second horizontal error correction is executed using

[0007]

For example, in a mobile FM multiplex broadcast, when the horizontal error correction of a data packet fails, the first block identification information to be included in the block is replaced by the first block identification information included in the block in which the horizontal error correction was successful. 2 based on the block identification information. Using the estimated first block identification information, the horizontal error correction of the block in which the horizontal error correction has failed is performed again. As an estimation method, the second block identification information is stored, and when error correction fails, information obtained by adding a predetermined value to the second block identification information is estimated as the first block identification information. In some cases, the first block identification information is estimated by substituting the included block identification information and the stored second block identification information into a predetermined arithmetic expression. Also, when the horizontal error correction after the vertical error correction fails, the block identification information is estimated in the same manner as described above, taking into account the result of the horizontal error correction performed earlier. The horizontal error correction is performed again using the block identification information.

The reason why the horizontal error correction can be performed again using the prefix thus estimated is as follows. That is, since the CRC is performed in the horizontal error correction, even if the prefix estimation is erroneous, the probability of the erroneous correction is extremely low.

[0009]

According to the present invention, the error correction capability of the horizontal error correction is improved, and the packet error rate is improved. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The data structure of a mobile FM multiplex broadcast is such that a prefix is assigned to each packet as shown in FIG. 3 so that retransmitted data can be replaced in packet units in consideration of extremely poor reception conditions. I have. In mobile FM multiplex broadcasting, a situation in which one data group is divided into a plurality of continuous blocks and sent is considered (hereinafter, simply referred to as “situation 1”). In this case, the information included in the prefix of the block has a high correlation with that of the prefix of the block before and after being transmitted. That is, the data structure of the mobile FM multiplex broadcast is designed so that the prefix between consecutive blocks has extremely high redundancy for operational convenience.

Here, the prefix (32 bits) used in the character / graphic / traffic information coding system will be described. As shown in FIG. 3, the prefix is 4-bit service identification data, 1-bit decoding identification flag,
1-bit information end flag, 2-bit update flag, 1
It is composed of a total of 32 bits of a 4-bit data group number and a 10-bit data packet number, and is used by the software of the receiver when storing and displaying data.

The function, operation and redundancy of such a prefix will be specifically described. (1) Service identification data [b1 to b4: 4 bits] Function: The service identification data is composed of 4 bits b1 to b4, and the type of the program contents (character / graphic / traffic information, additional information, auxiliary signal, operation signal) And the binary value of the transmission mode, and together specify the data packet configuration.

During operation: Each data group is assigned unique service identification data. Redundancy: In situation 1, the same value is entered in each data block b1 to b4 as long as the data group does not change. (2) Decoding identification flag [b5: 1 bit] Function: The decoding identification flag is composed of one bit of b5, and is set to "1" when the error correction circuit immediately outputs data by decoding only in the horizontal direction. "0" to output after decryption
And

During operation: fixedly assigned to each data group. Redundancy: In situation 1, each data block contains the same value unless the data group changes. (3) Information end flag [b6: 1 bit] At the time of function & operation: The information end flag is made up of one bit of b6, and is set to "1" when the data group to be transmitted with a certain data group number ends, and other In this case, it is set to “0”.

Redundancy: In situation 1, b6 in most data blocks included in the data group is "0". (4) Update flag [b7, b8: 2 bits] At the time of function & operation: The update flag is composed of 2 bits b7 and b8, and when a data group transmitted with a certain data group number is updated, increment by one. If it has been transmitted and has not been updated, it is transmitted with the same flag as the previously transmitted update flag.

Redundancy: In situation 1, they take the same value in the same data group. (5) Data group number [b9 to b22: 14 bits] Function & operation: Data group number is 1 of b9 to b22
It consists of 4 bits and indicates the data group number assigned when the data group is transmitted. However, when transmitting data groups linked to each other, consecutive data group numbers are assigned in ascending order. Identify which data group packets belong to.

Redundancy: In situation 1, they take the same value in the same data group. (6) Data packet number [b23 to b32: 10 bits] Function & operation: The data packet number is composed of 10 bits b23 to b32, and indicates the data packet number to be transmitted for each data group number. The position of the data packet within the data group is known. Data packet numbers are assigned in ascending order from "0".

Redundancy: In the same data group, the next data packet number increases by one. As described above, in mobile FM multiplex broadcasting, a situation is considered in which one data group is divided into a plurality of continuous data groups and transmitted, but in this case, the prefix portion becomes redundant when viewed from the preceding and following data blocks. Part occurs. On the other hand, the (272, 190) shortened difference set cyclic code inherits the property of the cyclic code as the name implies, and has a feature that an information symbol appears as it is in the first 190 bits of 272 bits. Therefore, the prefix portion having redundancy between the preceding and succeeding data blocks can use the redundancy at both the stage of reception and after decoding.

Therefore, the error correction control method of the present invention effectively utilizes the originally available redundant portion. FIG. 1 shows an FM multiplex broadcast receiver 10 for realizing the error correction control method of the present invention. FM multiplex broadcast receiver 10 includes terminals 12 and 14. The FM multiplexed data signal a received from the terminal 12 and demodulated into digital data is input to the reception memory 16 and the synchronous reproduction circuit 18. The clock signal b input from the terminal 14 and synchronized with the FM multiplex data signal a is input to the synchronous reproduction circuit 18. The block synchronization and the frame synchronization are reproduced by the synchronous reproduction circuit 18, and the received data a
8 is written on the reception memory 16 based on the synchronization information output from the reception memory 8. The reception memory 16 has a flag area 16a.
The flag area 16a stores flag data t (described later) that stores the success or failure of decoding of each packet (the success or failure of horizontal error correction).

First, horizontal error correction is performed on all packets. That is, the corresponding data c is uploaded from the reception memory 16 to the shift register 22 included in the error correction circuit 20, and error correction is performed.
The shift register 22 is also used to temporarily store the data c. The error correction circuit 20 includes a shift register 22 of 272 bits, a syndrome register of 82 bits, a majority logic circuit (not shown), and the like.
Perform error correction. The error correction result signal d is input to the error correction control circuit 24. Here, the result signal d goes to a high level when the error correction is successful, and goes to a low level when the error correction fails.

Further, the error correction circuit 20 sends the CRC circuit 2
The data e after error correction is input to 6, and error detection of the correction result by the CRC code is performed. The CRC result signal f is input to the error correction control circuit 24. At this time, the result signal f goes high when no error is detected in the correction result, and goes low when an error is detected. The error correction control circuit 24 receives the error correction result signal d and the CRC result signal f, and outputs the signal g only when it is determined that there is no error (successful decoding), that is, when both are high level. Thus, the 272-bit data h of the error correction result is downloaded to the reception memory 16.

At this time, the error correction control circuit 24 determines that there is no error in the error correction and CRC, and if the packet is a data packet, adds the clock pulse signal i instructing the loading of the prefix in the shift register 22 to the prefix. By sending it to the estimation circuit 28,
Only the prefix of the packet h after error correction being downloaded from the shift register 22 to the reception memory 16 is
Shift register 30 in prefix estimation circuit 28
(Fig. 2). Load signal j to 10-bit counter 32 in prefix estimation circuit 28
Becomes high level immediately after the 32nd clock pulse i ends, and sends the data packet number of the prefix composed of the register values k from the first stage (first stage) to the tenth stage of the shift register 30 to the counter 32. Load (see FIG. 4). Therefore, the count value of the counter 32 (FIG. 6) indicates the data packet number.

The prefix is estimated on the basis of the downloaded prefix. That is, when the error correction control circuit 24 determines that decoding of the data packet has failed (the error correction result output d and the CRC result output f are received and at least 1
If they are incorrect, it is determined that error correction, that is, decoding has failed. ), The error correction control circuit 24
(See FIG. 6). Note that a portion having a common prefix component between data packets, such as a data group number, is stored in the eleventh stage to the 32nd stage of the shift register 30.

Error correction by prefix estimation when data packet decoding fails is performed by the following operation of replacing the prefix value stored in the prefix estimating circuit 28 with the prefix of the data packet whose decoding has failed. . That is, the error correction control circuit 24 outputs a load signal n for loading the register values k of the 11th to 32nd stages of the shift register 30 and the count value m from the counter 32 into the P / S conversion circuit 34. , P / S conversion circuit 34. Thereafter, the P / S conversion circuit 34 outputs the serial data o one bit at a time in synchronization with the timing of uploading the failed data packet from the reception memory 16 to the shift register 30, so that the error correction control circuit 24 The pulse p is output to the / S conversion circuit 34. P / S receiving this
The conversion circuit 34 outputs the estimated prefix serial data o to the selector 36. The error correction control circuit 24 switches the serial signal (estimated value) o from the prefix estimating circuit 28 between bits 1 to 32 and the data c from the receiving memory 16 between bits 33 to 272. q is output to the selector 36 (see FIG. 5).

Thereafter, the data loaded into the error correction circuit 20 is subjected to error correction. If the error correction by the prefix estimation is successful, the data h is downloaded from the shift register 22 to the reception memory 16. At this time, the prefix included in the data h is also downloaded to the shift register 30 as in the case where the error correction is successful without relying on the prefix estimation. However, when the error correction based on the prefix estimation fails, the error correction control is performed. The circuit 24 does not output the count-up signal 1 for counting up the counter 32. When the error correction has failed, the error correction control circuit 24 stores the flag data t of “1” indicating the decoding failure in the flag area 16 a in the reception memory 16. If the decoding is successful, the flag data t indicates “0”.

In such a horizontal error correction, when even one of the data packets in the frame fails to correct the error, the vertical error correction is executed as follows. When the synchronous reproduction circuit 18 detects that the first packet of the next frame has been reached, vertical error correction is performed. The data c read in the vertical direction is supplied to the selector 36.
, And is input to the error correction circuit 20, and error correction is performed in the same manner as in the horizontal direction. During vertical error correction, the selector 36 is fixed so as to always select the data c.
After the correction, the error correction result signal d is input to the error correction control circuit 24. The data r after the vertical error correction
Is input to the coincidence detection circuit 38. Also, the match detection circuit 3
8, the data after the horizontal error correction stored in the reception memory 16 is read out in the vertical direction (this data is
The flag data t (indicating the success or failure of the horizontal error correction) of the data packet to which each data s belongs is read out from the flag area 16a and supplied.

In the coincidence detection circuit 38, the error correction circuit 20
Is determined based on the flag data t. That is, the coincidence detection circuit 38 determines whether or not the data r that has succeeded in the horizontal error correction previously performed in the data s is all the same as the data r, and outputs the coincidence detection signal u to the error correction control circuit 24. I do. If they all match, the match detection signal u goes high, otherwise it goes low. The error correction control circuit 24 determines whether the vertical error correction has been correctly performed by taking the logical sum of the vertical error correction result signal d and the coincidence detection signal u. The error correction control circuit 24 outputs a high-level signal g only when the error is correctly corrected, and downloads the error-corrected data h to the reception memory 16.

The horizontal error correction after the vertical error correction is basically performed on a data packet in which the first horizontal error correction has failed. That is, the error correction is performed on the data packet for which the horizontal error correction has failed, while looking at the flag data t stored in the reception memory 16. In this case, the prefix estimation by the prefix estimating circuit 28 determines the prefix of the data packet that exists immediately before the data packet for which error correction has failed in the first horizontal error correction and has been successfully corrected, in the reception memory 1.
6 may be directly loaded into the prefix estimating circuit 28, but in this case, an additional circuit must be added. Therefore, in consideration of the fact that the transmission rate of the mobile FM multiplex broadcast is much longer than the error correction processing time, in this embodiment, the data is temporarily stored in the error correction shift register 22 as in the case of the normal horizontal error correction. This is realized by inputting the prefix included in the data h to the estimation circuit 28 after uploading c and performing error correction. Thus, the circuit scale is reduced.

The reason why the processing can be performed in this way is that the error correction of the data packet existing immediately before the data packet for which the horizontal error correction has failed and for which the error correction has succeeded always succeeds. The estimation circuit 28 always outputs the data h from the shift register 22.
Load pulse i for loading the prefix inside
And the load signal j.

In FIG. 6, (B)
IC) with a "dash"(') indicates a prefix estimated. The data packet identification in the second row indicates whether the packet is a data packet or a parity packet. When it is at a high level, it indicates a data packet, and when it is at a low level, it indicates a parity packet. Also, the counter 32 outputs the load pulse i or the count-up signal l
Count up according to.

In this way, the horizontal error correction after the vertical error correction can be executed in the same manner as the first horizontal error correction. In the FM multiplex broadcast receiver 10 shown in FIG. 1, since the CRC is performed by horizontal error correction, the probability of erroneous correction is extremely low even if the prefix estimation is erroneous. Directional error correction becomes possible.

According to such an error correction control method, the error correction capability in the horizontal direction is improved. For example, (272,
190) The error correction capability of the shortened difference set cyclic code is 272.
100% can be corrected for errors of t bits or less in bits,
If it is assumed that the correction fails for (t + 1) bits or more, the probability Pe (t, m, P) that can be corrected by applying the horizontal error correction to a packet including m errors and including a p-bit prefix is assumed. p) is represented by Equation 1.

[0033]

(Equation 1)

Equation 1 is the probability when the prefix can be estimated. Assuming that t = 8 and p = 32, the specific calculation is as follows: Pe (8, 9, 32) = 0.68 Pe (8, 10, 32) = 0.33 Pe (8, 11, 32) = 0.12 Pe (8,12,32) = 0.03.

Assuming that t = 11 and p = 32, the specific calculation is as follows: Pe (11,12,32) = 0.78 Pe (11,13,32) = 0.47 Pe (11, 14, 32) = 0.22 Pe (11, 15, 32) = 0.08. Thus, the error correction capability in the horizontal direction is improved.

If the prefix estimating circuit 28 is replaced with a microcomputer, more sophisticated prefix estimating becomes possible. The embodiment shown in FIG. 1 is a circuit configured assuming the situation 1. On the other hand, situation 2 described later
Is assumed, the prefix estimation circuit 28 is used only when the transmission standard specifies that the transmission intervals of packets belonging to the same data group are almost equal.
Are parallelized by a number corresponding to the transmission interval, and the above-described processing for each prefix estimation circuit 28 is performed for each transmission interval.

The above-described embodiment of FIG. 1 is a case in which dedicated hardware is configured. FM multiplexing enables the microcomputer to directly access the reception memory 16 and to receive the hardware reception status signal and error correction status signal. The same effects as in the embodiment of FIG. 1 can be obtained in the broadcast receiver. FIG. 7 shows the FM multiplex broadcast receiver 10 '. Such an FM multiplex broadcast receiver 10 'can be configured for the following reasons.

That is, since the transmission rate of mobile FM multiplex broadcasting is 16 Kbps, the time that can be devoted to tasks such as decoding one packet and taking in data is 18 ms and 25 ms, respectively. Considering the time required for decoding control, it can be considered that the time available for data packet capture, prefix inference and replacement is 20 milliseconds. This is because, given the current processing speed of the microcomputer, a sufficient time is given.

An FM multiplex broadcast receiver 10 'in which error correction is controlled by a microcomputer will be described. As shown in FIG. 7, FM multiplex broadcast receiver 10 'includes terminals 12 and 14. The reception data a 'received from the terminal 12 is transmitted to the reception memory 16 and the synchronous reproduction circuit 18
Is input to The clock signal b 'received from the terminal 14 and synchronized with the received data a' is output from the synchronous reproduction circuit 1
8 is input. The block synchronization and the frame synchronization are reproduced by the synchronous reproduction circuit 18. Received data a '
Is written into the memory 16 based on the synchronization information and the block number output from the synchronous reproduction circuit 18. The decoding of the packet stored in the reception memory 16 is performed based on the control of the CPU 42 included in the microcomputer 40.

The CPU 42 judges the presence or absence of the decoding process by looking at the status data d 'indicating the current status of the packet whose error is to be corrected. The status data d 'includes frame synchronization information and block synchronization information at the time of the first horizontal error correction, frame synchronization information at the time of vertical error correction, and the first horizontal error correction result at the time of horizontal error correction after the vertical error correction. Including. When it is determined that decoding is to be performed, the decoding circuit 46 specifies the packet number to be corrected between the horizontal error correction and the vertical error correction and the data e ′ indicating the vertical column in the frame or the packet e to be corrected. .

The decoding circuit 46 reads the designated data f 'from the reception memory 16 and executes a decoding process (ie, error correction and CRC check). If the decoding in the horizontal direction is successful, the decoded data g 'is overwritten on the data before decoding on the receiving memory 16 and a signal h' indicating that the error correction was successful is flagged on the receiving memory 16. The packet is written in the status information storage area for the packet provided in the area 16a. On the other hand, if the decoding in the horizontal direction has failed, the decoded data g 'is not written in the reception memory 16, but the data h' indicating that the error correction has failed is stored in the status information storage area for the packet. Write.

The CPU 42 checks the flag h 'indicating the success or failure of the decoding stored in the status information storage area and the prefix portion (not shown) on the reception memory 16 while checking the flag h'.
Perform prefix estimation. That is, when the CPU 42 detects that the decoding of the packet in the horizontal direction has failed by looking at the status information storage area on the reception memory 16 after the decoding process, the prefix of the packet for which the correction has failed is temporarily added to the work attached to the CPU 42. After being saved in the memory 44 (indicated by j '), the prefix of the packet whose correction has failed is replaced with the estimated prefix according to the prefix estimation algorithm described below.

After such an operation, error correction is executed again. If the decoding is successful, the decoded data g 'is overwritten on the data before decoding on the receiving memory 16 and the flag h' indicating that the error correction was successful is set on the receiving memory 16 for the packet corresponding to the status. Write to the information storage area. When the decoding fails, the decoded data is not written into the reception memory 16, but the flag h 'indicating that the error correction has failed is written in the status information storage area for the packet, and the CPU
The previous prefix saved in the work memory 44 attached to 42 is written in the corresponding prefix section of the reception memory 16. The work memory 44 stores an estimated value calculation table and a variable x described later.

The operation of the FM multiplex broadcast receiver 10 'will be described with reference to FIGS. Here, the method of estimating the prefix using the prefix estimation algorithm and correcting the error is performed for a data packet in which the first horizontal error correction has failed and a data packet in which the horizontal error correction has failed after the vertical error correction. Applied.

As a method of estimating a prefix, there is forward estimation for estimating a prefix from a data packet which has been transmitted before and has been successfully decoded. There is also backward estimation, which estimates the prefix of a previously transmitted data packet that failed to decode, starting from the data packet that succeeded in decoding at the current time. Error correction associated with forward estimation is performed when decoding at the current time has failed, and error correction associated with backward estimation is performed when decoding at the current time has succeeded. It should be noted that there is no problem if the prefix estimation uses only forward estimation or only backward estimation.

In this embodiment, prefix estimation based on forward estimation is applied. First, the prefix estimation will be described. In the error correction with prefix estimation, the error correction capability largely depends on the prefix estimation capability. Therefore, in a distorted transmission mode such as a case where a packet belonging to the data group 1 and a packet belonging to the data group 2 are alternately transmitted (Situation 2), the packet belonging to any data group is transmitted. You have to analogize exactly what will come.

In the prefix estimation for estimating a prefix from a data packet for which error correction was successful in the past, a data packet number (hereinafter, simply referred to as “dpn”) and a dpn of a data group number and the like for the packet for which error correction has been successfully completed last. And a data packet position number (hereinafter simply referred to as “frp”) and a transmission interval (hereinafter simply referred to as “inc”: packet unit) of the same data group. By performing the calculation, the current prefix is estimated. frp indicates the position of the data packet in the same frame, and indicates 1 to 190.

Here, inc is obtained as follows. For example, assuming that dpn = dpn _A2 , frp = frp _A2 of a packet of dps = A for which error correction has succeeded at the present time,
Assuming that dpn = dpn _A1 and frp = frp _{A1 of a} packet of dps = A for which error correction has succeeded earlier, inc _A, which is an inc of a packet of dps = A, can be obtained by the following equation.

[0049]

(Equation 2)

In a system having a transmission protocol in which inc is determined, only a predetermined value is used as inc, and therefore, calculation of inc as in Expression 2 is not necessary. The actual prefix estimation is performed using an estimated value calculation table such as Table 1 obtained by the above-described operation for each dps. For example, in the situation 2, the estimation is performed in the following procedure.

[0051]

[Table 1]

First, to perform prefix estimation on the data packet of the data packet position number frp _X for which the horizontal error correction has failed, the data packet position number fr
whether the data packets of p _X belongs to dps of any line of the estimate calculation table, selected by using a number 3 to the estimated value calculation table.

[0053]

[Number 3] _{(frp x -frp i) mod inc} i = 0
(I = A, B, ... ) dp rows with frp _i and inc _i satisfies Equation 3
s is the desired dps. When dps is determined, the dpn and frp of the selected row (dps) of the estimated value calculation table are applied to Equation 4 to obtain the dpn of an erroneous packet.
_X is determined.

[0054]

(Equation 4)

After replacing the dps _X estimated in this manner with the correction of the erroneous packet prefix,
Error correction is performed again. Next, updating of the estimated value calculation table shown in Table 1 will be described. In order to increase the accuracy of the prefix estimation, it is necessary to always maintain the accuracy of the estimation value calculation table. Therefore, it is necessary to update the estimation value calculation table every time data packet error correction is performed.

The update of the estimated value calculation table is performed by
Is included. Deletion of Rows in Table When error correction is successful for a certain data packet and the information end flag (b6) of the packet is set to “1”, a row of the estimated value calculation table having the same dps as the packet is deleted. Need to be removed. At this time, the other dps inc included in the estimated value calculation table is updated to a value obtained by subtracting “−1” from the current inc. However, when the error correction is successful and the information end flag of the packet is set to “1”, unless the same dps is present in the estimated value calculation table, data relating to the packet is not registered in the estimated value calculation table. .

Row Insertion in Table If the information end flag (b 6) is “0” and the dps of the packet for which error correction was successful is not registered in the estimated value calculation table, this dps is registered in the table. . At this time, the other d included in the estimated value calculation table
The inc of ps is updated to a value obtained by adding “+1” to the current inc. Also, in for newly registered dps
For c, a value determined in the system, that is, a system default is used.

If the row update information end flag (b6) in the table is “0” and the dps of the packet for which error correction has been successful is registered in the estimated value calculation table, the dps is registered in the estimated value calculation table. A new inc is calculated by substituting the dps data and the data of the packet for which the error correction has been successful into Equation 2. Then, while updating inc in the estimated value calculation table to the calculated inc, dpn and frp are updated.
Are updated to the dpn and frp of the packet for which the error correction was successful, respectively. It is needless to say that the maximum value of frp is 190 in this embodiment.

Decrement of frp term Ensuring continuity of frp between consecutive frames is performed by repeating each frp in the table every time one frame decoding operation is completed.
This can be realized by subtracting 190 from the value. In particular, this is necessary when the area where the data group exists extends over two or more frames.

Removal of Negative frp Terms In systems where decoding operations cannot return between frames, it is desirable to remove the negative frp before performing. Next, the operation of the FM multiplex broadcast receiver 10 'will be described. First, in step S1 shown in FIG. 8, after turning on the power, the estimated value calculation table is cleared and initialized. Next, horizontal error correction is performed in step S3. In the horizontal error correction, as shown in FIG. 9, first, a variable x = 0 is set in step S1a. Variable x
Indicates the position of the packet for error correction, that is, the block, in the frame. The top block in the frame is indicated by a variable x = 0, and the variable x is incremented by one as going downward. Then, in step S3a, it is determined whether or not the variable x <272, and the variable x <2
If it is 72, it is determined that the horizontal error correction has not been performed for all the packets in the frame yet, and step S5a
Proceed to. After performing the horizontal error correction in step S5a, it is determined in step S7a whether the packet subjected to the horizontal error correction is a data packet. If it is not a data packet, the variable x is incremented by "1" in step S9a (x = x + 1), and the process returns to step S3a.

On the other hand, if it is determined in step S7a that the packet is a data packet, the flow advances to step S11a. In step S11a, it is determined whether or not the error correction has been successful. If the error correction has not been successful, the process proceeds to step S13a to perform prefix estimation. In the prefix estimation, first, in step S1b shown in FIG.
As shown in the table, all dps in the estimated value calculation table
Is determined. That is, it is determined whether the data packet for which error correction has failed has been searched for all dps in the estimated value calculation table to which dps in the estimated value calculation table belongs. If all dps have been searched in the estimated value calculation table, the process proceeds to step S9a shown in FIG. The same applies to the case where the estimated value calculation table is cleared.

On the other hand, if all dps in the estimated value calculation table have not been searched in step S1b, the process proceeds to step S3b, where frp, dpn, and inc of each predetermined dps in the estimated value calculation table are counted. It is read out to be substituted into 3 and Equation 4, and the process proceeds to step S5b. In step S5b, it is determined whether Expression 3 is satisfied. If Equation 3 is not satisfied, the process returns to Step S1b, and if Equation 3 is satisfied, the process proceeds to Step S7b. In step S7b, dpn is estimated by Equation 4,
After replacing the estimated dps and dpn with the prefix of the data packet for which error correction has failed, the process proceeds to step S9b, where the horizontal error correction is performed again. Then, in step S11b, it is determined whether the error correction has been successful. If the error correction was not successful,
It returns to step S1b. That is, in this case, steps S1b to S11 are performed until the horizontal error correction is successfully performed using the other dps data in the estimated value calculation table.
The processing of b is repeated. On the other hand, if it is determined in step S11b that the error correction has been successful, the process proceeds to step S11b.
Proceeding to 13b, the estimated value calculation table is updated.

In updating the estimated value calculation table, first, in step S1c shown in FIG.
It is determined whether it is 1. If the information end flag = 1, the above-described processing is executed in step S5c.
If the information end flag is not 1, the process proceeds to step S3c. In step S3c, it is determined whether or not the estimated value calculation table has the same dps as the dps to which the data packet for which the horizontal error correction has failed belongs.
If there is no ps, the above is executed in step S7c. If the same dps is found in step S3c, the above is executed in step S9c. In this way, when the processing in FIG. 11 is completed, step S in FIG.
Update of the table of FIG. 13b is also completed, and step S1 of FIG.
The prefix estimation of 3a is also terminated.

Returning to FIG. 9, if the error correction has been successful in step S11a, the estimated value calculation table is updated in step S15a. In updating the estimated value calculation table, the process shown in FIG. 11 is performed, and the process proceeds to step S9a. Then, after incrementing the variable x by “1” in step S9a, the process returns to step S3a. If x ≧ 272 in step S3a, it is determined that the horizontal error correction has been completed for all the packets in the frame, and the process proceeds to step S5 shown in FIG.

In step S5 shown in FIG. 8, it is determined whether or not the error correction of all the data packets has been successful. If the error correction has not been successful, the flow advances to step S7 to execute vertical error correction. Then, in step S9, the saved estimated value calculation table is copied for use in correcting the horizontal error in step S11. At this time, even if the estimated value calculation table has not been saved yet, that is, the content of the save table is cleared, the save table is copied. Then, in step S11, horizontal error correction is performed.

The horizontal error correction shown in step S11 is as follows.
The processing is performed as shown in FIG. In step S1d shown in FIG. 12, a variable x = 0. If x <272 in step S3d, the process proceeds to step S5d.
In step S5d, it is determined whether the error correction has already been successful. If the error correction has not been successful, it is determined in step S7d whether the packet is a data packet. If it is a data packet, after performing the horizontal error correction in step S9d,
Proceed to step S11d. In step S11d,
If the horizontal error correction has failed, after estimating the prefix in step S13d, step S17d
Proceed to.

On the other hand, if the horizontal error correction has succeeded in step S11d, and if the error correction has already succeeded in step S5d, the flow advances to step S15d to update the estimated value calculation table, and step S17d Proceed to. In step S17d, x
= X + 1, and the process returns to step S3d. Step S3d
As long as x <272, the above processing is repeated. If x ≧ 272, the process proceeds to step S13 in FIG. In addition, in step S5 shown in FIG. 8, when error correction for all data packets in one frame is successful, there is no need to perform vertical error correction and horizontal error correction after vertical error correction. So step S
Proceed to 13.

In step S13, the negative frp element in the estimated value calculation table is deleted, and 190 is subtracted from each frp value in the estimated value calculation table. As described above, the reason why the negative frp element in the estimation value calculation table is deleted is that the data group having the negative frp before the deletion is regarded as 2 frames from the viewpoint of the frame to be decoded.
This is because it is not very useful for prefix estimation because it is the previous frame. The reason for subtracting 190 from each frp in the estimated value calculation table after deleting the negative frp element in the estimated value calculation table is to ensure the continuity of the frp value between consecutive frames. Next, in step S15, the estimated value calculation table is saved. The reason for saving the estimated value calculation table in step S15 after step S13 is to use the saved estimated value calculation table for prefix estimation in horizontal error correction after vertical error correction. Then, in step S17, the process proceeds to the next frame, and returns to step S3. The estimated value calculation table used at the time of the horizontal error correction in step S3 is the same as that in step S3.
15 is an estimated value calculation table that has been saved, that is, an original estimated value calculation table.

The FM multiplex broadcast receiver 1 shown in FIG.
In the case of using an error correction control method in which all data of a packet is overwritten in the receiving memory 16 after error correction at 0 ', it is needless to say that not only the prefix but also the entire packet needs to be stored in the work memory 44. . Further, in each of the above-described embodiments, the estimation of the prefix of the data packet that has failed in decoding is not limited to the estimation performed based on the prefix of the data packet that has succeeded in decoding immediately before. That is, when decoding of a data packet is determined to be unsuccessful, a prefix of a data packet that has failed to be decoded is estimated from a prefix of a data packet for which error correction was successful before and after that (only the prefix of the previous data packet is possible). It may be.

Further, in the above embodiment, (272, 1
90) A case has been described where the shortened difference set cyclic code is applied to product coded, for example, an FM multiplex broadcast receiver.
It is needless to say that the present invention is not limited to this. Further, in each of the above-described embodiments, the case where the error correction control method of the present invention is applied to the FM multiplex broadcast receiver has been described. However, the present invention is not limited to this. It goes without saying that the error correction control method of the present invention can be applied to any data transmission device that transmits data obtained by encoding blocks.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a prefix estimation circuit.

FIG. 3 is an illustrative view showing a structure of a prefix of mobile FM multiplex broadcasting;

FIG. 4 is a timing chart showing load timing of a prefix estimation circuit.

FIG. 5 is a timing chart showing prefix replacement timing.

FIG. 6 is a timing chart showing the operation timing of error correction.

FIG. 7 is a block diagram showing another embodiment of the present invention.

FIG. 8 is a flowchart showing a main routine of the embodiment in FIG. 7;

FIG. 9 is a flowchart showing an error correction routine for horizontal error correction of the embodiment in FIG. 8;

FIG. 10 is a flowchart showing a prefix estimation routine in the embodiment in FIG. 8;

FIG. 11 is a flowchart showing a routine for updating an estimated value calculation table in the embodiment in FIG. 8;

FIG. 12 is a flowchart showing an error correction routine of horizontal error correction after vertical error correction.

FIG. 13 is an illustrative view showing a frame structure of a mobile FM multiplex broadcast;

[Explanation of symbols]

 10, 10 '... FM multiplex broadcast receiver 16 ... reception memory 18 ... synchronous reproduction circuit 20 ... error correction circuit 22 ... shift register 24 ... error correction control circuit 26 ... CRC circuit 28 ... prefix estimation circuit 36 ... selector 38 ... match detection Circuit 40: microcomputer 42: CPU 44: work memory

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Masayuki Takada 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Toru Kuroda 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (72) Kenichi Tsuchida 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Research Institute (72) Inventor Tadashi Isobe 1-110-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation, Research Institute of Broadcasting (72) Inventor Satoshi Yamada 1-1-10, Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation, Research Institute of Broadcasting Technology (56) References JP-A-59-90440 (JP, A) 59-94941 (JP, A) JP-A-63-133721 (JP, A) TAKADA et al., "An FM Multiplex Broadcasting" System for Traffic Information Services, IEEE-IEEE Vehicle Navigation and Information Systems Conference 1993, p. 344-347 (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 1/00 H04H 1/00 H04L 29/02

Claims (5)

(57) [Claims] 1. Data is divided into a plurality of blocks each containing block identification information, and an error correction code having a property that an information symbol appears as it is is used for each block.
Applying horizontal error correction coding to encode each
In both cases, the vertical encoding is performed over a plurality of the blocks.
An error correction control method for a data transmission apparatus for transmitting data obtained by performing directional error correction coding, comprising : (a) identifying a first block to be included in a block in which error correction failed in a first horizontal error correction; the information same
Estimation based on the second block identification information included in the block that has been successfully corrected in the same horizontal error correction ,
And (b) the block in which the first horizontal error correction has failed
Using the estimated first block identification information,
An error correction control method, wherein a second horizontal error correction is performed. 2. The error correction control method according to claim 1, wherein the method is used for horizontal error correction after vertical error correction. 3. The step (a) stores the second block identification information, and stores the second block identification information when error correction fails.
3. The error correction control method according to claim 1, wherein information obtained by adding a predetermined value to the block identification information is estimated as the first block identification information. 4. The step (a) stores the second block identification information, and performs a predetermined operation on the block identification information included in the block for which error correction has failed and the second block identification information. By substituting into the equation, the first
3. The error correction control method according to claim 1, wherein the block identification information is estimated. 5. The error correction control method according to claim 1, which is used for an FM multiplex broadcast receiver.