JP3180775B2 - Power converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an AC-DC converter,
The present invention relates to a single-phase or multi-phase power converter such as a DC-AC converter and an AC-DC-AC converter.

[0002]

2. Description of the Related Art An AC-DC converter (converter) and a DC-AC converter (inverter) are configured to control ON / OFF of a bridge-connected switch.
In a converter and an inverter, switching loss occurs when the switch is turned off and when the switch is turned on. Connecting a capacitor in parallel with a switch to reduce switching loss at the time of turn-off and to suppress noise has already been performed.

[0003]

Incidentally, a capacitor connected in parallel with the switch reduces switching loss and suppresses noise at the time of turn-off. However, when the charge of the capacitor is released through the switch at the time of turn-on, switching loss occurs.

An object of the present invention is to provide a single-phase or multi-phase power converter capable of reducing a switching loss at the time of turning on a switch.

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems and to achieve the above object, the present invention provides at least a first and a second AC terminals, a pair of DC terminals, and a first and a second AC terminals. At least a first, a second, a third, and a fourth switch bridge-connected between a first terminal and the pair of DC terminals, and in a reverse direction to the first, second, third, and fourth switches; A first, second, third and fourth diode connected or built into the first, second, third and fourth switches; and a first, second, third and fourth diode. A converter comprising first, second, third and fourth capacitors or stray capacitances connected in parallel to a switch; a reactor connected between an AC power supply terminal and the AC terminal; Immediately turning on at least one of the second, third and fourth switches. A single-phase or multi-phase power conversion device comprising: a soft switching control circuit for making a voltage between the pair of DC terminals substantially zero. first and second control switches Q11, Q12, and the first and second diodes D11, D12, a first resonant circuit for forming a capacitor or a DC power source C r, the resonant reactor Lr, the switch control circuit 4c And the first control switch Q
One end of the DC power supply E0 is connected to one end of the DC power supply E0, the other end of the first control switch Q11 is connected to one of the pair of DC terminals, and the other end of the DC power supply E0 is connected to the pair of DC terminals. Connected to the other end of the second control switch Q12
And a series circuit of the resonance reactor and the resonance circuit forming capacitor or the DC power supply are connected between the pair of DC terminals, and the switch control circuit 4c connects the first control switch Q11 to at least one of the converters. Turn-off control at a time t3 shortly before the turn-on of one switch, and then a time t shortly after the turn-off of at least one other switch of the converter
Turns controlled by 7, the turn-off control time t 3 of the said second control switch Q12 first control switch Q11
The first control switch Q11 is turned on at a time t9 slightly after the turn-on control time t7 of the first control switch Q11, and the voltage Vco between the pair of DC terminals is reduced. The present invention relates to a power converter characterized in that at least one of the first, second, third and fourth switches is turned on when the value is zero or a value close to zero. Things. Further, as shown in claim 2, it is possible to adopt a configuration in which the converter of claim 1 is replaced with an inverter. In addition, a combination of a converter and an inverter can be used. It is desirable to connect a soft switching capacitor between a pair of DC terminals as described in claims 4 to 6.

[0006]

According to the present invention, since the conversion switch is turned on after the voltage between the pair of DC terminals or the voltage of the soft switching capacitor is reduced to zero or almost zero, the power loss of the switch is reduced. Can be reduced.
Further, the switching loss can be reduced while the excess energy is absorbed by the soft switching control circuit and the power conversion is favorably performed.

[0007]

Embodiments and Examples Next, embodiments and examples of the present invention will be described with reference to FIGS.

[0008]

First Embodiment A three-phase power converter according to a first embodiment of the present invention shown in FIG.
-It has an AC inverter 2, a soft switching control circuit 3 which can also be called a DC link circuit, and a switch control circuit 4.

The first, second and third AC terminals B1, B2 and B3 as input terminals of the converter 1 are connected to the first, second and third boosting reactors L1, L2 and L3 and the first and second AC reactors. And the third AC power supply terminals A1, A2, A3.
It is connected to a 00 V three-phase AC power supply AC. The inverter 2 is connected to the output terminal of the converter 1 via first and second DC lines E1, E2. First and second
Between the DC lines E1 and E2, a soft switching capacitor C, which can also be called a DC link capacitor.
o and the soft switching control circuit 3 are connected. The soft switching capacitor Co is a resonance capacitor, and is a small-capacity capacitor capable of operating at a high frequency. The soft switching control circuit 3 includes a reactor that resonates with the capacitor Co, a switch for selectively forming a resonance circuit, and the like. The rising voltage and the falling voltage of the capacitor Co are the converter 1 and the inverter 2
Of the conversion switch in the specified section at the time of turn-on and turn-off, and a function of alleviating a sudden change in the terminal voltage at the time of turn-on and turn-off of the conversion switch, that is, a soft switching action occurs.

The three-phase output terminal of the inverter 2 includes resistors R1, Rb and Rc via filter reactors La, Lb and Lc.
2, a load R consisting of R3 is connected.

The control circuit 4 includes a control circuit for the converter 1, a control circuit for the inverter 2, and a circuit for controlling the soft switching control circuit 3. In order to control the converter 1 by the control circuit 4, the control circuit 4 is connected to AC power supply terminals A1, A2, A3 and detects current flowing through the AC power supply terminals A1, A2, A3. CT1, CT2, CT3, and
The first and the second for detecting the output voltage of the converter 1
Are connected to the DC lines E1 and E2. In order to control the output voltage of the inverter 2 to be constant, the control circuit 4
Are also connected to the output line of the inverter 2. The output line of the control circuit 4 is also connected to the control terminal (gate) of the conversion switch of the converter 1 and the inverter 2 and the control terminal (gate) of the control switch of the soft switching control circuit 3. 3 is also connected to the voltage detection circuit and the current detector.

FIG. 2 shows the converter 1 and the soft switching control circuit 3 of FIG. 1 in detail. As is apparent from FIG. 2, the converter 1 is a well-known switching type converter capable of improving the power factor, and includes first, second, third, fourth, fifth, and sixth three-phase bridge-connected converters. Diode D
1, D2, D3, D4, D5, D6 and each diode D
Insulated gate type (MOS type) F connected in parallel to 1 to D6
A first, a second, a third, a fourth, a fifth and a sixth converter switch Q1, comprising an ET (field effect transistor),
Q2, Q3, Q4, Q5, Q6 and the first, second, third,
Fourth, fifth and sixth capacitors C1, C2, C3, C
4, C5 and C6. In this converter 1, a first series circuit of the first and second diodes D1 and D2, a second series circuit of the third and fourth diodes D3 and D4, and a second series circuit of the fifth and sixth diodes D5 and D6. One end of each of the three series circuits is connected to a first DC line E1 functioning as a first DC terminal, and the other end is connected to a second DC line E2 functioning as a second DC terminal. ing. The intermediate point between the first, second and third series circuits is the first, second and third AC input terminals B1, B2, B3.
It has become. In FIG. 2, the diodes D1 to D6 and the capacitors C1 to C6 are shown as individual elements. .

FIG. 3 shows the inverter 2 and the soft switching control circuit 3 of FIG. 1 in detail. As is apparent from FIG. 3, the inverter 2 includes first, second, third, fourth, fifth, and sixth inverter switches Qa, Qb, and Qc composed of an insulated gate FET connected in a three-phase bridge. , Q
d, Qe, Qf and the first, second, third, fourth, fifth, and sixth feedback diodes Da, connected in parallel to them.
Db, Dc, Dd, De, Df and first, second, third, fourth, fifth, and sixth parallel capacitors Ca, Cb, Cc,
Cd, Ce, and Cf. The first and second inverter switches Qa and Qb of the inverter 2
, The third and fourth inverter switches Qc,
Qd, a second series circuit, fifth and sixth switches Qe,
One end of a third series circuit of Qf is connected to a first DC line E1 functioning as a first DC input terminal, respectively.
The other ends of these terminals serve as second DC input terminals.
Of the first, second and third filter reactors La and Lb.
, Lc to a three-phase load R consisting of resistors R1, R2, R3.

In order to clarify the relationship between the converter 1 and the inverter 2, the soft switching control circuit 3, which is shown in detail in both FIGS. 2 and 3, periodically changes the voltage Vco of the soft switching capacitor Co. For example, a power supply circuit composed of a rectifier and a capacitor or a 200 V DC power supply E0 composed of a battery, and first and second control switches Q1 composed of an insulated gate type FET.
1, Q12, feedback diodes D11 and D12 connected in parallel to these switches Q11 and Q12, a reactor Lr for resonance, and a capacitor Cr for forming a resonance circuit. First
Is connected between one end of the DC power supply E0 and the first DC line E1. One end of the second control switch Q12 is connected to the first DC line E1 via the reactor Lr, and the other end of the second control switch Q12 is connected to the second DC line E2 via the resonance circuit forming capacitor Cr. It is connected. Therefore, the resonance reactor Lr
A series circuit of the second control switch Q12 and the resonance circuit forming capacitor Cr is connected in parallel to the DC power supply E0 via the first control switch Q11. A series circuit of the resonance reactor Lr, the second control switch Q12, and the resonance circuit forming capacitor Cr is connected in parallel to the soft switching capacitor C0.

The switch control circuit 4 includes the first to fourth switches shown in FIG.
A first control circuit 4a for controlling the sixth converter switches Q1 to Q6 and a second control circuit 4b for controlling the first to sixth inverter switches Qa to Qf shown in FIG. , And a third control circuit 4c for controlling the first and second control switches Q11 and Q12 shown in FIG.

The switches Q1 to Q1 of the converter 1 shown in FIG.
The first control circuit 4a for controlling Q6 includes a U-phase signal forming circuit 21, a V-phase signal forming circuit 22, a W-phase signal forming circuit 23, and a control signal output circuit 24. The U-phase signal forming circuit 21 includes a detection current input circuit 25a connected to the output line 25 of the current detector CT1 of FIG. 1 and a voltage detection circuit connected to the power supply terminal A1 of FIG. 27, an error amplifier 29 connected to an output voltage detection line 28, a reference voltage source 30, and a multiplier for multiplying a reference sine wave obtained from the voltage detection circuit 27 by a voltage control signal obtained from the error amplifier 29. 31, a subtractor 32 for obtaining an output of a difference between a current waveform obtained from the current input circuit 25a and a sine wave obtained from the multiplier 31, and a frequency sufficiently higher than the frequency of the AC voltage of the AC power supply AC. A triangular wave generating circuit 34 for generating a triangular wave with a period sufficiently shorter than the frequency, that is, the period of the AC voltage; a comparator 35 connected to the subtractor 32 and the triangular wave generating circuit 34; And a Vco zero detection circuit 36 for detecting that the voltage Vco of the capacitor C0 has become zero or close to zero. The V-phase signal forming circuit 22 is connected to the current detector CT2 of FIG.
And a line 39 connected to the power supply terminal A2 and a line 28 connected to the DC line E1 to form a U-phase signal for controlling the third and fourth converter switches Q3 and Q4. It is formed in the same manner as the circuit 21. The W-phase signal forming circuit 23 is connected to the DC detector CT3 of FIG. 1 by a line 40, and is connected to a power supply terminal A3 by a line 41.
And the fifth and sixth converter switches Q5 and Q6 which are connected to the DC line E1 by a line 28.
Is formed in the same manner as the U-phase signal forming circuit 21. The V-phase and W-phase signal forming circuits 22, 23
Does not include a component corresponding to the Vco zero detection circuit 36 of the U-phase signal formation circuit 21 and also serves as these of the U-phase signal formation circuit 21.

U-phase, V-phase and W-phase signal forming circuits 21, 2
Numerals 2 and 23 form signals for controlling the switches Q1 to Q6 so as to approximate the waveform of the current flowing through the input terminals A1, A2 and A3 of FIG. 1 to a sine wave and bring the power factor close to one. The operation of the U-phase signal forming circuit 21 will be described with reference to FIG. 4. A waveform A corresponding to the AC input current is obtained from the current input circuit 25a, and this is the input to the subtractor 32. The reference sine wave B is obtained from the voltage detection circuit 27. From the multiplier 31, a waveform C is obtained by multiplying the reference sine wave B by the voltage control signal. The subtractor 32 generates a signal (error signal) indicating the difference between the waveforms A and C, which is
Input. The comparator 35 compares the triangular wave voltage Vt generated from the triangular wave generating circuit 34 shown in FIGS. 10 and 13A with the output voltage V32 of the subtractor 32, and generates a square wave output shown in FIG. 13B. . Vco zero detection circuit 36 of FIG.
Generates a signal indicating that Vco has become zero based on the voltage Vco on the line 28 at time t4 as shown in FIG. The triangular wave generating circuit 34 generates a triangular wave voltage Vt which rises rapidly to a predetermined voltage value in synchronization with the output pulse of the Vco zero detecting circuit 36, and then gradually decreases. Vco
The zero detection circuit 36 is a U-phase, V-phase and W-phase signal forming circuit 2
1, 22, and 23, so that the U-phase comparator 3
The rising of the output pulse of No. 5 and the output pulses of the V-phase and W-phase comparators corresponding to the U-phase comparator 35 are synchronized. As shown in FIG. 10, the triangular wave V
center value of t and outputs 32u, 32v, 32w of the subtractor 32
The input level of the comparator 35 is set so as to match the center value of the comparator 35. Note that 32u, 32v, 32 in FIG.
w indicates the output of the U-phase, V-phase, and W-phase subtractor 32.

FIG. 5 shows the control signal output circuit 24 of FIG. 4 in detail. The control signal output circuit 24 includes first, second, and third NOT circuits 42, 43, 44, first, second, and third OR gates 45, 46, 47, and a timer 48. In FIG. 5, in order to prohibit the switches Q1 and Q2, Q3 and Q4, Q5 and Q6 of the same arm of the bridge circuit from being turned on at the same time, the switching between one on state and the other on state is prohibited. The elements for providing a dead time (pause period) are NOT circuits 42, 43,
44 and OR gates 45, 46, 47. However, a dead time circuit 49 can be independently provided as shown by a dotted line in FIG. NOT circuits 42, 43, 4
4 is connected to the output lines 35a, 35b, 35c of the comparator 35 and the corresponding comparator of another phase. One input terminal of each of the OR gates 45, 46, and 47 is connected to the NOT circuits 42, 43, and 44 of each phase, and the other input terminal is connected to the timer 48, respectively. It is connected to the control terminals of the third and fifth switches Q1, Q3, Q5. The comparator output lines 35a, 35b, 35c of each phase are connected to the control terminals of the second, fourth and sixth switches Q2, Q4, Q6, respectively. The timer 48 is connected to the Vco zero detection circuit 36 shown in FIG. 4 and has a time width T2 from t4 to t6 shown in FIG.
Are generated in synchronization with the Vco zero detection. The output of the OR gate 45, that is, the control signal of the switch Q1 is shown in FIG.
As shown in (1), it is on level (high level) during the period from t0 to t6 and t11 to t21, and is off level (low level) during the period from t6 to t11. The control signal of the second switch Q2 is turned on (high level) during the period from t4 to t10 as shown in FIG. As is clear from FIG.
When the switch Q1 is turned on, a known dead time shown at t10 to t11 is provided, but when the switch Q2 is turned on, no dead time is provided, and the switches Q1 and Q2 are turned on at the same time from t4 to t6. Third
The control signals for the sixth to sixth switches Q3 to Q6 are the first and second switches.
Are formed similarly to the control signals of the switches Q1 and Q2.
The times t0 to t21 in FIGS. 11, 12, 13 and 14 indicate the same time regardless of the difference between the drawings. In FIGS. 11 to 14, the time axis is partially extended or reduced for convenience of illustration.

FIG. 11A shows the voltage Vco of the capacitor Co.
11 (B), (C), (D), (E),
(F) and (G) show the drain-source voltages V1 to V6 of the first to sixth switches Q1 to Q6 of the converter 1 and FIGS. 11 (H), (I), (J) and (K). , (L),
(M) shows drain-source voltages Va to Vf of the first to sixth inverter switches Qa to Qf of the inverter 2, and FIGS. 11 (N) (O) (P) (Q) (R) 2 shows the state of each section of the soft switching control circuit 4. Note that the hatched lines in FIGS. 11B to 11M indicate ON control signals of the respective switches. As is clear from FIGS. 11B to 11G, all the switches Q1 to Q6 of the converter 1 and all the switches Qa to Qf of the inverter 2 are connected to t during one cycle of the triangular wave Vt.
All are turned on in the section from 4 to t6, and are turned on at the same time. When all the conversion switches Q1 to Q6 and Qa to Qf are turned on in the period from t4 to t6, the voltage Vco of the soft switching capacitor Co becomes zero volts as shown in FIG. The capacitor voltage Vco gradually decreases in the interval from t3 to t4, and gradually increases in the interval from t6 to t7. In FIG. 11, the voltage V2 of the switch Q2
, The voltage V4 of the switch Q4, the voltage V5 of the switch Q5,
When the voltage Va of the switch Qa, the voltage Vc of the switch Qc, and the voltage Vf of the switch Qf are in the interval t1 to t2, the capacitor C
o, the voltage gradually decreases in synchronization with the voltage Vco, and the switches Q2, Q4, Q5, Qa, Qc, and Qf achieve soft switching at the time of turn-on.
, The voltage V3 of the switch Q3, the voltage V6 of the switch Q6, the voltage Vb of the switch Qb, the voltage Vd of the switch Qd, and the voltage Ve of the switch Qe are gradually synchronized with the voltage Vco of the capacitor Co in the interval t6 to t7. The soft switching of these switches Q1, Q3, Q6, Qb, Qd, and Qe at the time of turning off is achieved.
The ramp voltage of the capacitor Co in the section from t3 to t4 and in the section from t6 to t7 is created based on the soft switching control circuit 3. The waveforms in FIGS. 11 and 12 are shown in FIG.
The three-phase input voltages Vu1, Vv1, Vw1,
And a minute section including the output voltage Vu2, Vv2, Vw2 of the inverter 2 at the point in time ta. In the section different from the point in time ta in FIG. 9, the ON periods and the OFF periods of the switches Q1 to Q6 and Qa to Qf are different from those in FIG.

FIG. 6 shows a second control circuit 4b included in the control circuit 4 of FIG. 1, that is, an inverter control circuit. The inverter control circuit 4b includes U-phase, V-phase, and W-phase PWM
Pulse forming circuits 51, 52, 53 and control signal output circuit 5
4 and six inverter switches Qa to Qf.
(PWM) pulse for turning on / off the power. The U-phase PWM pulse forming circuit 51 includes a sine wave generating circuit 55, a multiplier 56, a comparator 58, a triangular wave generating circuit 57, a voltage detecting circuit 59, and an error amplifier 60
And a reference voltage source 61. The sine wave generation circuit 55 generates a reference sine wave at the same frequency as the output frequency of the inverter 2. The voltage detection circuit 59 is connected to the U
The output voltage of the phase is detected and sent to the error amplifier 60. The error amplifier 60 multiplies the output corresponding to the difference between the output of the voltage detection circuit 59 and the reference voltage of the reference voltage source 61 by a multiplier 56.
Send to The multiplier 56 multiplies the sine wave by the voltage control signal and sends the sine wave whose amplitude is controlled to the comparator 58. The triangular wave generation circuit 57 generates a triangular wave voltage (carrier) at a frequency sufficiently higher than the output frequency of the inverter 2. The triangular wave generation circuit 57 is provided with the Vco zero detection circuit 36 shown in FIG.
A triangular wave voltage is generated in synchronization with the output of. The input / output relationship of the comparator 58 is the same as that of the comparator 4 in FIG. V phase and W
The phase PWM pulse forming circuits 52 and 53 have substantially the same configuration as the U-phase PWM pulse forming circuit 51.

FIG. 7 shows the control signal output circuit 54 of FIG. 6 in detail. The control circuit 54 includes three NOT circuits 71, 7
2, 73 and three OR gates 74, 75, 76. The switches Qa and Q of each arm of the inverter 2 are
FIG. 7 is a simplified diagram showing elements included in the OR gates 74, 75 and 76 for preventing b, Qc and Qd, and Qe and Qf from being simultaneously turned on. However, a known dead time (pause period) circuit 77 for preventing two switches of the same arm from being turned on at the same time can be provided independently at a position shown by a dotted line in FIG. An output line 58a of the comparator 58 is connected to a control terminal of the first inverter switch Qa and a first NOT switch.
It is connected to a circuit 71. Output lines 58b and 58c of the V-phase and W-phase comparators corresponding to the U-phase comparator 58 are connected to the control terminals of the third and fifth inverter switches Qc and Qe, and are connected to the second and third inverter switches Qc and Qe. Are connected to NOT circuits 72 and 73. First, second and third O
One input terminal of the R gates 74, 75, 76 is connected to NOT circuits 71, 72, 73, and the other input terminal thereof is connected to the timer 48 of FIG. Fourth and sixth inverter switches Qb, Qd
, Qf.

FIG. 14 shows the U-phase switch Q shown in FIGS.
FIG. 6 is a waveform chart for explaining formation of control signals for a and Qb. The comparator 58 includes a voltage Vt of the triangular wave generation circuit 57 and a sine wave voltage V56 of the output of the multiplier 56 as shown in FIG.
And generates a square wave shown in FIG. 14B, which is a control signal for the switch Qa in FIG. 14F. NO
The inverted signal of FIG. 14B shown in FIG. 14C is obtained from the T circuit 71. The OR gate 74 receives the pulse shown in FIG. 14C and the pulse shown in FIG.
A control signal for the second inverter switch Qb shown in FIG. As a result, both the first and second inverter switches Qa and Qb are simultaneously turned on in the section from t4 to t6. V-phase and W-phase inverter switch Q
The control signals for c, Qd, Qe, and Qf are created in the same manner as for the U phase. The on-time widths of the switches Qa to Qf in a section different from the point in time ta in FIG. 9 are shown in FIGS.
Different from 4.

As is apparent from FIGS. 11 (H) to 11 (M), the switches Qa to Qf of the inverter 2 are simultaneously turned on in the section from t4 to t6. The switches Qa, Qc, and Qf are simultaneously turned on at time t4. Voltage Va at time t4
, Vc, and Vf are almost zero, so that soft switching (zero volt switching) is achieved and switching loss is suppressed. Switches Qb, Qd, Qe
Is turned off at time t6, and the voltages Vb, Vd and Ve increase with a slope during the turn-off period from t6 to t7. Therefore, soft switching (zero volt switching) of these switches is achieved, and switching loss and noise are suppressed. Note that FIG.
As can be seen from (F), the turn-on time t13 of the switch Qb is later than the turn-off time t12 of the switch Qa, and a dead time is provided between the two.

The third control circuit 4c of the control circuit 4 of FIG.
Is, V11 zero detecting circuit 81 as shown in FIG. 8 and Vco <V _EO
A detection circuit 82, a t1 determination timer 83, a resonance current zero detection circuit 84, and first and second RS flip-flops 85, 8
6. The V11 zero detection circuit 81 comprises a comparator. One input terminal of this comparator is connected to the voltage detection circuit 3a of the first control switch Q11 by a line 3c, and the other input terminal is connected to a reference potential point at or near zero level. Therefore, the V11 zero detection circuit 81
Is a time point t at which the voltage V11 gradually decreases and crosses the reference potential point (zero level or its vicinity) as shown in FIG.
In step 7, the signal shown in FIG. The output line of the V11 zero detection circuit 81 is connected to a first flip-flop 85.
12 (E), the flip-flop 85 is set at the time point t7 in the pulse of FIG. 12 (E), and generates a high level output at the time point t7 as shown in FIG. 12 (G). The first control switch Q11 is turned on. Vco <V _EO detection circuit 82 comparator - consist data.
One input terminal of the comparator of the detection circuit 82 is connected to a soft switching capacitor C0 by a line 28.
, And the other input terminal is connected to a reference voltage source slightly lower than the power supply E0. Therefore, the detection circuit 82 outputs a signal shown in FIG. 12D at the time t3 when the capacitor voltage Vco becomes lower than the reference voltage. Vco
<The output line of the _VEO detection circuit 82 is connected to the reset terminal R of the first flip-flop 85. Therefore,
The first flip-flop 85 is reset to a low level at time t3 as shown in FIG. 12 (G), and the first control switch Q11 is turned off. t1 determination timer 83
Is connected to the Vco zero detection circuit 36 of FIG. 4 by a line 37, and measures a predetermined period T1 from the Vco zero detection time t4, that is, the rising time of the triangular wave Vt as shown in FIG. The predetermined period T1 is set slightly shorter than the cycle of the triangular wave Vt. This predetermined period T1 is between to and t1 in FIG.
This corresponds to the sum of the period and the period from t4 to t21. The output line of the t1 determination timer 83 is connected to the set terminal S of the second flip-flop 86. Accordingly, the second flip-flop 86 is set at the time point t1 as shown in FIG. 12H in response to the output pulse of the t1 determination timer 83 in FIG. Outputs ON control signal. The zero resonance current detection circuit 84 comprises a comparator, one input terminal of which is connected to the current detector 3b of FIG. 2 by a line 3d, and the other input terminal of which has a zero level or a level near this. It is connected to the given reference potential point. As a result, the resonance current zero detection circuit 84 outputs a signal indicating the time point t9 at the end of the half-wave on the negative side of the resonance current Ir shown in FIG. 11N as shown in FIG. The signal is applied to the reset terminal R of the flip-flop 86. As a result, the second flip-flop 86 is set in the period from t1 to t9 as shown in FIG. 12 (H), and controls the second control switch Q2 to the ON state. The output of the second flip-flop 86, V11 zero detecting circuit 81 and Vco of Figure 8 <V _EO detection circuit 8
It is also connected to 2 and is used to limit the operation period of the V11 zero detecting circuit 81 and Vco <V _EO detection circuit 82. That, V11 zero detecting circuit 81 and Vco <V _EO detection circuit 8
2 generates an effective output only during the period from t1 to t9.

Next, the operation of the power converter of FIG. 1 in each section of FIG. 11 will be described. In the following description, current paths are indicated only by reference numerals of circuit elements. Also,
As described above, FIG. 11 shows the state of each part in a short period including ta in FIG.

[0026]

[To-t1 section] At time ta in FIG. 9, the voltage of the first input terminal A1 is the highest, and then the second input terminal A1.
2 and the voltage at the third input terminal A3 is the lowest and negative. Also, in the section from t0 to t1, the first, third and sixth converter switches Q1, Q3 and Q6 are turned on, and the second, fourth and fifth inverter switches Qb and
Qd and Qe are on, and the first control switch Q11 of the soft switching control circuit 3 is on. As a result, A1-L1-D1, Q1-Q11-E0-D6 and Q6 are connected between converter 1 and soft switching control circuit 3.
-L3-A3 circuit, 2-L2-Q3 and D1-Q11-E0
The circuit of -D6-L3-A3 is formed. Further, between the inverter 2, the soft switching control circuit 3, the reactors La, Lb, Lc and the load R, La-R-
Lc-D5 and Qe-Q11-E0-Db and Qb circuit, L
A circuit of b-R-Lc-De and Qe-Q11-E0-Dd and Qd is formed. When the voltage Vco of the capacitor Co is lower than the voltage (200 V) of the power supply E0, E0 -Q
An 11-Co circuit is formed, and the voltage of the capacitor Co is 2
00V. In this section from t0 to t1, the converter 1
, A step-up action occurs, and a pair of DC lines E1, E2
When a voltage of 200 V or more is generated during
is maintained at 200 V or higher, the boosted energy is fed back to the DC power supply E0, and the energy stored in the reactors La to Lc and the load R in the output stage of the inverter 2 is fed back to the DC power supply E0. .

[0027]

[T1 to t2 section] In the t1 to t2 section, the switches of the converter 1 and the inverter 2 are in the same state as the previous t0 to t1 section, and the two switches Q11 and Q12 of the soft switch control circuit 3 are both Is on. Second at t1
When the control switch Q12 is turned on, the current Ir of the resonance circuit of the reactor Lr and the capacitor Cr becomes as shown in FIG.
Start to flow as shown in 1 (N). Since the current Ir gradually increases from t1, a zero current switch of the second control switch Q12 is achieved, and this switching loss is suppressed. In the section from t1 to t2, the current is shunted to the resonance circuit containing Lr, so that the current I11 that has been fed back to the power supply E0 through the first control switch Q11 gradually decreases as shown in FIG. , T2, the feedback current becomes zero.

[0028]

[T2 to t3 section] In the t2 to t3 section, the switches Q1 to Q6, Qa to Qf, Q11 and Q12 are set to the previous t1 to t3.
The same control state as in the section t2 is maintained. Since the resonance cycle of the resonance circuit including Lr is t1 to t9, which is sufficiently longer than t1 to t2 and t2 to t3, the resonance current Ir continues to increase even in the interval from t2 to t3 as shown in FIG. . Since the feedback current passing through the first control switch Q11 becomes zero at time t2 as shown in FIG. 11D, it is possible to supply a current from the DC power supply E0 to the resonance circuit including Lr. The current I11 flows in the circuit of -Q11-Lr-Q12-Cr.

[0029]

[T3 to t4 section] In the t3 to t4 section, the converter
Switches Q1 to Q6 of the inverter 1 and the switch Q of the inverter 2.
a to Qf are kept in the same control state as in the previous section. However, in the soft switching control circuit 3, FIG.
As shown in (P), the first control switch Q11 is controlled to be off, and the second control switch Q12 is kept on. t
At time 3, the voltage Vco of the capacitor C0 is equal to the voltage Vco of the power supply E0.
It corresponds to the point when it is lower than _EO . That is, Vco <V
_EO is detected, and at t3, the first control switch Q
11 is turned off. The first control switch Q11 has a stray capacitance C between the drain and the source as shown by a dotted line in FIG.
11, the voltage V11 between both terminals is
As shown in (P), the voltage gradually increases from the time t3, and zero volt switching is achieved. In the section from t3 to t4, the voltage Vco of the capacitor Co decreases with a slope as shown in FIG. 11A due to resonance of the circuit of Co-Lr-Q12-Cr, and becomes zero at t4. In the section from t3 to t4, the switches Q1, Q3, Q6 of the converter 1 and the switches Qb, Qd, Qe of the inverter 2 are on, and the switches Q2, Q4, Q5, Qa,
Qc and Qf are off. Therefore, the voltages (drain-source voltages) V2, V4, V5, Va, between the terminals of the switches Q2, Q4, Q5, Qa, Qc, Qf in the OFF state are set.
Vc and Vf become substantially equal to the voltage Vco of the capacitor Co, as shown in FIGS. 11 (C), (E), (F), (H),
As shown in (J) and (M), it gradually decreases in the interval from t3 to t4, and becomes substantially zero at time t4.

[0030]

[T4 to t5 section] The voltage V of the capacitor C0 at time t4
When it is detected that co has become substantially zero, the switches Q2, Q4, Q5, Qa, Qc and Qf are turned on. At this time t4, these drain-source voltages are as shown in FIGS. 11B, 11E, 11F, 11H, 11J,
Since it is substantially zero as shown in (M), soft switching (zero volt switching) is achieved and switching loss is reduced. Since all the switches Q1 to Q6 and Qa to Qf of the converter 1 and the inverter 2 are controlled in the ON period during the period from t4 to t5, the capacitor Co is short-circuited by the switches Q1 to Q6 and Qa to Qf. Keep at zero. The outputs of the reactors L1, L2 and L3 are short-circuited by the switches Q1 to Q6, and a current flows through the reactors L1, L2 and L3, and energy is stored in these. The resonance current Ir becomes zero at time t5 as shown in FIG. 11N, and thereafter flows in the opposite direction.

[0031]

[T5 to t6 section] In the t5 to t6 section, the previous t4 to t6
Similarly to the section 5, the switches Q1 to Q6 and Qa to Qf of the converter 1 and the inverter 2 are kept on. Therefore, except for the point where the direction of the resonance current Ir becomes the negative direction as shown in FIG. 11 (N), the operation in the section from t5 to t6 is t
This is the same as the operation in the section from 4 to t5. The time point t6 is determined by the timer 48 in FIG.

[0032]

[T6 to t7 section] At time t6, the switches Q1, Q3,
Q6, Qb, Qd and Qe are turned off, the short circuit of the capacitor Co is released, and the capacitor Co, the resonance circuit forming capacitor Cr, the second control switch Q12 or the diode D12 and the resonance reactor Lr are formed. A resonance circuit is formed. As a result, the voltage Vco of the capacitor Co gradually increases in the interval from t6 to t7 as shown in FIG. As a result, the capacitors C1, C3, C6,
The switches Q1, Q3, Q6, Qb, Qb, Cb, Cd, Ce gradually increase in voltage and turn off at time t6.
The voltages between the terminals of Qd and Qe are also shown in FIGS.
As shown in (G), (I), (K), and (L), the voltage gradually increases, and soft switching at the time of turn-off is achieved. At time t7, the voltage V _EO (200
V) and the voltage Vco (200 V) of the capacitor C0 become the same, so that the voltage V11 of the first control switch Q11 is
It becomes zero as shown in 1 (P). In the section from t6 to t7, A1-L1-Q2-Cr-Q12-Lr-Q5-L
3-A3 circuit and A2-L2-Q4-Cr-Q12-
The reactor L1 by the circuit of Lr-Q5-L3-A3,
The operation of accumulating energy in L2 occurs, and furthermore, Cr-Q12
-Lr-Qa-La-R-Lc-Qf circuit and Cr
A circuit of -Q12-Lr-Qc-Lb-R-Lc-Qf also occurs, and energy is stored in the reactors La and Lb. t
At the time 7, the voltage Vco of the capacitor C0 is a predetermined value (200
V).

[0033]

[T7 to t8 section] At time t7 when Vco becomes 200 V, the first control switch Q11 is turned on. t7 ~
In the section t8, the switches other than the first control switch Q11 are the same as the previous sections t6 to t7, and the switches Q2 and Q
4, Q5, Qa, Qc, Qf, and Q12 are on.
Since the voltage V11 of the first control switch Q11 is zero at time t7, the first control switch Q11 performs a soft turn-on operation, and the switching loss is small. This t7
In the section from time t8 to time t8, a current flows through the reactor Lr with the same circuit as that in the section from time t6 to time t7, and Lr-Q11 or Dr
The current I11 also flows through the circuit of 11-E0-Cr-Q12 or D12. The current I11 in the section between t7 and t8 is shown in FIG.
This is the negative current shown in (O). The time t8 is the time when the current I11 crosses zero.

[0034]

[T8 to t9 section] The operations of the converter 1 and the inverter 2 in the t8 to t9 section are the same as those in the previous t7 to t8 section, and the switches Q2, Q4, Q5, Qa, Qc, and Qf are controlled to be turned on. . Further, the first and second control switches Q11 and Q12 are also on. In the interval from t8 to t9, the current I11 of the circuit of E0-Q11-Lr-Q12-Cr becomes a positive direction as shown in FIG. At time t9, the current Ir of the resonance reactor Lr becomes zero.

[0035]

[T9 to t10 section] At time t9, the second control switch Q
12 is turned off control. At time t9, the current Ir passing through the second control switch Q12 is substantially zero as shown in FIG. 11 (N), so that the second control switch Q12 achieves soft switching (zero current switching).
This switching loss is small. In the section between T9 and t10, switches other than the second control switch Q12 are connected to the previous section t.
Control is performed in the same manner as in the case of 8 to t9. Therefore, A1 -L1 -Q
2-E0-Q11-Q5-L3-A3 circuit, A2-L2
-Q4 -E0 -Q5 -L3 -A3 circuit, F0 -Q11-
Qa-La-R-Lc-Qf circuit, E0-Q11-Q3
The circuit of -Lb -R-Lc -Qf is formed.

[0036]

[T10-t11 section] In the t10-t11 section, Q4, Q5, Q
a, Qc, Qf, and Q11 are in the on-control state, and Q1, Q
2, Q3, Q5, Qb, Qa, Qe, and Q12 are off. When the switch Q2 is turned off, the parallel capacitor C2 is gradually charged, the voltage V2 of the capacitor C2 and the voltage V2 of the switch Q2 rises with a slope as shown in FIG. 11C, and soft switching is achieved. Is reduced. On the other hand, the first switch Q
Since 1 is connected in series to the second switch Q2,
From the voltage between the DC lines E1 and E2 (about 200 V)
Is the value obtained by subtracting the voltage V2 of the switch Q2 from
As shown in FIG. 11 (B), it falls with an inclination in the interval from t11 to t11. Therefore, when the first switch Q1 is turned on at time t11, soft switching (zero volt switching) is achieved and switching loss is reduced.

[0037]

[T11-t12 section] In the t11-t12 section, the switch Q1,
Q4, Q5, Qa, Qc, Qf, Q11 are turned on,
The remaining switches are turned off. Thereby, AC-
A1-L1-Q1-Q5-L3-A3 circuit and AC
A current flows through the circuit of -A2-L2-Q4-Eo-Q11-Q5-L3-A3. In the section from t10 to t11, E0
-Q11-Qa-La-R-Lc-Qf circuit and E0
The circuit of -Q11-Qc-Lb-R-Lc-Qf is formed, and the DC-AC conversion operation by the inverter 2 occurs.

[0038]

[T12-t13 interval] In the t12-t13 interval, the switch Q2 of the inverter 2 is turned off at t12, and the switch Qb is turned on at t13.
This is the section that turns on. The operation of converter 1 in the section from t12 to t13 is the same as that in the previous section from t11 to t12.
From t12 to t13, the switches Qc and Q
f is turned on, and the switches Qa, Qb, Qd, and Qe are turned off. When the switch Qa is turned off at t11, the capacitor Ca is gradually charged, and this voltage Va becomes the voltage shown in FIG.
And rises with a slope as shown in FIG.
Voltage Vb falls with a slope as shown in FIG. 11 (I) and becomes zero at t11. Therefore, the switches Qa and Qb
Soft switching is achieved.

[0039]

[T13-t14 interval] The t13-t14 interval shows the state after the switch Qb is turned on at the time t14. This t13-t14
In the section, the converter 1 continues the same operation as in the previous section, and the inverter 2 operates according to the ON state of the switches Qb, Qc, and Qf.

[0040]

[T14 to t15 section] In the t14 to t15 section, the switch Q5
Turns off. As a result, the capacitor C5 is gradually charged, and this voltage V5 rises with a slope as shown in FIG. 11 (F), and the voltage V6 of the switch Q6 has a slope as shown in FIG. 11 (G). It falls and becomes almost zero at time t15. Accordingly, soft switching of the switches Q5 and Q6 is achieved. Note that in the section from t14 to t15, control of switches other than the switch Q5 is performed in the previous section t5.
Same as 13 to t14.

[0041]

[T15-t16 Section] At time t15, the switch Q6 is turned on. As a result, in the period from t15 to t16, the switches Q1, Q4, Q6, Qb, Qc, Qf, and Q11 are controlled to be on, and the other switches are controlled to be off.

[0042]

[T16 to t17 section] In the t16 to t17 section, the switch Qf of the inverter 2 is turned off at t16. As a result, the parallel capacitor Cf is gradually charged, and the voltage Vf rises with a slope as shown in FIG.
Conversely, the voltage Ve of the switch Qe falls with a slope as shown in FIG. 11 (L) and becomes substantially zero at time t17. Therefore, soft switching of the switches Qe and Qf is achieved.

[0043]

[Interval t17 to t18] At t17, the switch Qe is turned off. As a result, in the period from t17 to t18, Q1, Q4
, Q6, Qb, Qc, and Qe are turned on, and the other switches are turned off.

[0044]

[T18 to t19] At time t18, the switch Q4 is turned off. As a result, the parallel capacitor C4 is charged, and this voltage V4 rises with an inclination as shown in FIG. 11 (E), and conversely, the voltage V3 of the switch Q3 becomes
As shown in (D), it falls with an inclination, and becomes almost zero at t19. As a result, soft switching of the switches Q3 and Q4 is achieved. In this section from t18 to t19, AC
-A1 -L1 -Q1 and D1 -Q11-E0 -Q6 and D6-
L3-A3 circuit and AC-A2-L2-D3-Q11-E
A current flows through the circuits of 0-Q6 and D6-L3-A3. Inverter 2 operates in the same manner as in the previous section.

[0045]

[T19-t20 interval] At t19, the switch Q3 is controlled to be turned on. As a result, in the section from t19 to t20, the switches Q1,
Q3, Q6, Qb, Qc, Qe, and Q11 are turned on, and the other switches are turned off.

[0046]

[T20 to t21] At time t20, the switch Qc is controlled to be turned off. Thereby, the parallel capacitor Cc is charged,
This voltage Vc rises with a slope as shown in FIG. 11 (J), and conversely, the voltage Vd of the switch Qd falls with a slope as shown in FIG. 11 (K), and becomes almost zero at t21. Become.
Thereby, soft switching of the switches Qc and Qd is achieved. When the switch Qd is turned on at the time t21, the state becomes the same as that at the time t0.
This is repeated in the same manner as the period from 0 to t21.

As is apparent from the above description, according to the present embodiment, soft switching can be reliably and easily achieved both when the switches Q1 to Q6 of the converter 1 and the switches Qa to Qf of the inverter 2 are turned off and on. Can be.

[0048]

Second Embodiment Next, a second embodiment will be described with reference to FIGS.
The power converter of the embodiment will be described. However, in FIGS. 15 to 17, substantially the same parts as those in FIGS. 1 to 3 are denoted by the same reference numerals, and description thereof is omitted. The power converter of the second embodiment shown in FIGS. 15 to 17 has substantially the same configuration as that of FIGS. 1 to 3 except that the soft switching capacitor C0 is omitted from the power converter of FIGS. Have been.
As shown in FIGS. 15 to 17, a pair of DC lines E1, E
Even if no special soft-switching capacitor is connected between the two, the capacitors C1 to C6 connected in parallel to the switches Q1 to Q6 or their stray capacitances or the capacitors connected in parallel to the switches Qa to Qf are connected. The capacitors Ca to Cf or the stray capacitances thereof or the stray capacitance between the pair of DC lines E1 and E2 is changed to the pair of DC lines E1 and E2.
Since they are connected between the two, they function similarly to the soft switching capacitor C0 of FIGS. Therefore, the same effects as those of the first embodiment can be obtained by the second embodiment.

[0049]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) Switch Q1 of converter 1 and inverter 2
The method of forming control signals for turning on and off Q6 and Qa to Qf can be changed in various ways. For example, a switch control signal can be created by a digital controller. (2) The load R can be a motor. When the load R is a motor or has an inductance, the reactors La to Lc can be omitted. (3) Switches Q1 to Q6, Qa to Qf, Q11, Q12
Can be another semiconductor switch such as a transistor or an IGBT (insulated gate bipolar transistor). (4) The output frequency of the inverter 2 can be changed. (5) The present invention can be applied to a single-phase or two-phase converter or inverter. (6) To omit the inverter 2 and use a combination circuit of the converter 1, the soft switching control circuit 3 and the capacitor Co, and to omit the converter 1 and use a combination circuit of the inverter 2, the soft switching control circuit 3 and the capacitor Co. Can be. (7) In the case of a converter alone, in the case of a combination circuit of a converter and an inverter, the power supply E0 can be a capacitor. (8) The capacitor Cr for forming the resonance circuit can be used as a DC power supply. In this case, the voltage of the DC power supply is
_Is set to about half (100 V) which is lower than the voltage V _EO . (9) Vco zero detection circuit 36, V11 zero detection circuit 81, V
A part or all of the co <V _EO detection circuit 82 and the resonance current zero detection circuit 84 can be omitted, and a timer can generate an equivalent output.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a power converter according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a converter and a soft switching control circuit of FIG. 1 in detail.

FIG. 3 is a circuit diagram illustrating an inverter and a soft switching control circuit of FIG. 1 in detail;

FIG. 4 is a circuit diagram showing a converter control circuit portion of the switch control circuit of FIG. 1;

FIG. 5 is a block diagram schematically showing a control signal output circuit of FIG. 4;

FIG. 6 is a block diagram showing an inverter control circuit portion of the switch control circuit of FIG. 1;

FIG. 7 is a block diagram schematically showing a control signal output circuit of FIG. 6;

FIG. 8 is a block diagram showing a circuit for controlling a switch of the soft switching control circuit of the switch control circuit of FIG. 1;

FIG. 9 is a waveform diagram showing an input AC voltage of the converter of FIG. 1 and an output AC voltage of the inverter.

FIG. 10 is a waveform diagram showing inputs of a comparator in the U-phase, V-phase, and W-phase signal forming circuits of FIG. 4;

FIG. 11 is a waveform diagram showing a state of each unit in FIGS. 1 to 3;

FIG. 12 is a waveform chart showing a state of each unit in FIGS. 4, 5, and 8;

FIG. 13 is a waveform chart showing a state of each unit in FIGS. 4 and 5;

FIG. 14 is a waveform diagram showing a state of each unit in FIGS. 6 and 7;

FIG. 15 is a book diagram showing a power converter according to a second embodiment of the present invention.

FIG. 16 is a circuit diagram showing a converter and a soft switching control circuit of FIG. 15 in detail.

FIG. 17 is a circuit diagram showing the inverter and the soft switching control circuit of FIG. 15 in detail.

[Explanation of symbols]

 1 Converter 2 Inverter Co Soft switching capacitor Lr Resonance reactor Q1 to Q6, Qa to Qf, Switch Q11, Q12 Control switch

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M ^7/ 00-7/98

Claims (6)

(57) [Claims] 1. At least first and second AC terminals,
A pair of DC terminals, at least first, second, third and fourth switches bridge-connected between the first and second AC terminals and the pair of DC terminals; The first, second, and third switches connected in parallel in the reverse direction to the second, third, and fourth switches or built in the first, second, third, and fourth switches;
Third and fourth diodes, and first, second, and third diodes connected in parallel to the first, second, third, and fourth switches.
And a converter comprising: a fourth capacitor or a stray capacitance; a reactor connected between an AC power supply terminal and the AC terminal; and at least one of the first, second, third, and fourth switches. A single-phase or multi-phase power conversion device comprising: a soft-switching control circuit for making a voltage between the pair of DC terminals almost zero immediately before turning on the power supply; (E0)
A first and a second control switch (Q11, Q12), a first and a second diode (D11, D12), a first resonance circuit forming capacitor or a DC power supply (C r ), A reactor (Lr) and a switch control circuit (4c), one end of the first control switch (Q11) is connected to one end of the DC power supply (E0), and the first control switch (Q11) Is connected to one of the pair of DC terminals, the other end of the DC power supply (E0) is connected to the other of the pair of DC terminals, the second control switch (Q12) and the resonance reactor. And a series circuit of a capacitor for forming a resonance circuit and a DC power supply are connected between the pair of DC terminals. The switch control circuit (4c) connects the first control switch (Q11) to at least one of the converters. Switch At a time (t3) slightly before the on-time, then at a time (t7) shortly after the turn-off of at least one other switch of the converter, the second control switch ( little time prior to the turn-off control time (t 3) of said Q12) first control switch (Q11) (t1) deterministic -
The first control switch (Q11) is turned on at a point (t9) slightly later than the turn-on control point (t7) of the first control switch (Q11), and the voltage (Vco) between the pair of DC terminals is reduced. A power converter characterized in that at least one of the first, second, third and fourth switches is turned on when the value is zero or a value close to zero. 2. A pair of DC terminals, at least first and second AC terminals, and at least first, second, third and fourth bridge-connected terminals between the DC terminals and the AC terminals. An inverter switch, and first, second, third, and fourth inverters connected in parallel to the first, second, third, and fourth inverter switches or built in the first, second, third, and fourth inverter switches. Third and fourth feedback diodes,
First, second, third and fourth parallel capacitors or the first, second, third and fourth inverters connected in parallel to the first, second, third and fourth inverter switches An inverter having a stray capacitance of a switch; a smoothing reactor or an inductance component connected to the AC terminal of the inverter; and at least one of the first, second, third, and fourth inverter switches A single-phase or multi-phase power conversion device comprising: a soft-switching control circuit for making a voltage between the pair of DC terminals almost zero immediately before turning on one of the two terminals. DC power supply (E0)
A first and a second control switch (Q11, Q12), a first and a second diode (D11, D12), a first resonance circuit forming capacitor or a DC power supply (C r ), A reactor (Lr) and a switch control circuit (4c), one end of the first control switch (Q11) is connected to one end of the DC power supply (E0), and the first control switch (Q11) Is connected to one of the pair of DC terminals, the other end of the DC power supply (E0) is connected to the other of the pair of DC terminals, the second control switch (Q12) and the resonance reactor. the series circuit of the resonance circuit for forming a capacitor or a DC power source is connected between the pair of DC terminals and the switch control circuit (4c) is at least 1 of the inverter the first control switch (Q11) Two switches At a time (t3) slightly before the on-time, then at a time (t7) shortly after the turn-off of at least one other switch of the converter, the second control switch ( little time prior to the turn-off control time (t 3) of said Q12) first control switch (Q11) (t1) deterministic -
The first control switch (Q11) is turned on at a point (t9) slightly later than the turn-on control point (t7) of the first control switch (Q11), and the voltage (Vco) between the pair of DC terminals is reduced. A power source configured to turn on at least one of the first, second, third, and fourth inverter switches when the value is zero or a value close thereto. Conversion device. 3. A pair of inverter DC terminals and at least first and second inverter DC terminals.
An inverter AC terminal, at least first, second, third, and fourth inverter switches bridge-connected between the inverter DC terminal and the inverter AC terminal; The first, second, third and fourth feedback switches connected in parallel to the second, third and fourth inverter switches or built in the first, second, third and fourth inverter switches A diode, and first, second, third and fourth parallel capacitors connected in parallel to the first, second, third and fourth inverter switches or the first, second, third and fourth capacitors; An inverter having a stray capacitance of the inverter switch of No. 4, and a smoothing reactor or an inductance component connected to the inverter AC terminal, wherein the pair of inverter DC terminals is connected to the pair of inverters. Directly Power converter according to claim 1, characterized in that connected to the terminal. 4. At least first and second AC terminals,
A pair of DC terminals, at least first, second, third and fourth switches bridge-connected between the first and second AC terminals and the pair of DC terminals; First, second, third and fourth diodes connected in reverse parallel to the second, third and fourth switches or built in the first, second, third and fourth switches; A first, second, third and fourth capacitor or stray capacitance connected in parallel to the first, second, third and fourth switches; an AC power supply terminal and the AC terminal And a soft-switching capacitor connected between the pair of DC terminals; and immediately before turning on at least one of the first, second, third, and fourth switches, The voltage of the soft switching capacitor A single-phase or multi-phase power converter and a soft switching control circuit for the crucible zero, the soft switching control circuit includes a DC power supply (E0)
A first and a second control switch (Q11, Q12), a first and a second diode (D11, D12), a first resonance circuit forming capacitor or a DC power supply (C r ), A reactor (Lr) and a switch control circuit (4c), one end of the first control switch (Q11) is connected to one end of the DC power supply (E0), and the first control switch (Q11) Is connected to one end of the soft switching capacitor (Co), the other end of the DC power supply (E0) is connected to the other end of the soft switching capacitor (Co), and the second control switch ( Q12), a series circuit of the resonance reactor and the resonance circuit forming capacitor or the DC power supply is connected in parallel to the soft switching capacitor (C0), and the switch control circuit (4c) One control switch (Q11) is turned off at a time (t3) slightly before the turn-on time of at least one switch of the converter, and then shortly after the turn-off time of another at least one switch of the converter. turns the control at time (t7), on-controlled at slightly before time (t1) than the turn-off control time of the second said first controlled switch controlled switch (Q12) of (Q11) (t 3), is formed so as to turn off control at a later point in time a little (t9) than the turn-on controlling point (t7) of said first control switch (Q11), the soft switching voltage of the capacitor (C0) (Vco) is zero Or when at least one of the first, second, third and fourth switches is turned on. Power converter, wherein the door. 5. A pair of DC terminals, at least first and second AC terminals, and at least first, second, third and fourth bridge-connected between the DC terminals and the AC terminals. An inverter switch, and first, second, third, and fourth inverters connected in parallel to the first, second, third, and fourth inverter switches or built in the first, second, third, and fourth inverter switches. Third and fourth feedback diodes,
First, second, third and fourth parallel capacitors or the first, second, third and fourth inverters connected in parallel to the first, second, third and fourth inverter switches An inverter having a stray capacitance of a switch; a smoothing reactor or an inductance component connected to the AC terminal of the inverter; a soft switching capacitor connected between the pair of DC terminals; A soft-switching control circuit for making the voltage of the soft-switching capacitor almost zero just before turning on at least one of the first, second, third and fourth inverter switches. Wherein the soft switching control circuit includes a DC power supply (E0).
A first and a second control switch (Q11, Q12), a first and a second diode (D11, D12), a first resonance circuit forming capacitor or a DC power supply (C r ), A reactor (Lr) and a switch control circuit (4c), one end of the first control switch (Q11) is connected to one end of the DC power supply (E0), and the first control switch (Q11) Is connected to one end of the soft switching capacitor (Co), the other end of the DC power supply (E0) is connected to the other end of the soft switching capacitor (Co), and the second control switch ( Q12), a series circuit of the resonance reactor and the resonance circuit forming capacitor or the DC power supply is connected in parallel to the soft switching capacitor (C0), and the switch control circuit (4c) One control switch (Q11) is turned off at a time (t3) slightly before the turn-on time of at least one switch of the converter, and then shortly after the turn-off time of another at least one switch of the converter. turns the control at time (t7), on-controlled at slightly before time (t1) than the turn-off control time of the second said first controlled switch controlled switch (Q12) of (Q11) (t 3), The first control switch (Q11) is formed so as to be turned off at a time (t9) slightly later than the turn-on control time (t7) of the first control switch (Q11), and the voltage (Vco) of the soft switching capacitor (C0) becomes zero. Or, when the value is close to this, the first,
A power converter characterized in that at least one of the second, third and fourth inverter switches is turned on. 6. A pair of inverter DC terminals and at least first and second inverter DC terminals.
An inverter AC terminal, at least first, second, third, and fourth inverter switches bridge-connected between the inverter DC terminal and the inverter AC terminal; The first, second, third and fourth feedback switches connected in parallel to the second, third and fourth inverter switches or built in the first, second, third and fourth inverter switches A diode, and first, second, third and fourth parallel capacitors connected in parallel to the first, second, third and fourth inverter switches or the first, second, third and fourth capacitors; And a smoothing reactor or an inductance component connected to the inverter AC terminal. The pair of inverter DC terminals is connected to the soft switching capacitor. Power converter according to claim 4, characterized in that it is connected across the capacitor.