JP3175319B2 - VTR control signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control signal generating circuit for generating a control signal for tracking a video tape recorder, for example.

[0002]

2. Description of the Related Art For example, there is known an automatic track finding (hereinafter, referred to as ATF) circuit for performing tracking servo without using a control signal as used in an 8 mm video camera.

The ATF multiplexes four pilot signals (hereinafter, referred to as PLT signals) having different frequencies with a video signal as a control signal for a phase servo for a capstan at the time of recording. Is a tracking servo method in which phase servo is applied to a capstan that controls the tape speed by utilizing the above method. In such a tracking servo system, a PLT signal is extracted from a tape track, and crosstalk components from both adjacent tracks of a scanning track are separated and compared to detect a track shift. This comparison output is applied to the capstan as a capstan phase error signal. Also, at the time of variable speed reproduction, accurate tracking can be performed by using the PLT signal.

In the tracking servo described above, programmable timing data TD and pattern data PD for switching the PLT signal are set in a data table in advance. According to this data table,
Data is output from a predetermined reference signal. Here, if the reference signal is periodic and the end of the output signal is near the next reference signal, there is no time to set the next timing data TD or pattern data PD. For this reason,
In order to reduce the data setting time, the reference signal is divided and the timing is output. Further, when the timing data TD and the pattern data PD are set, complicated processing such as a comparison between the timing of data not output and the current time is required.

[0005]

As described above, in the above-described tracking servo system, complicated processing such as division of a reference signal and comparison of the timing of data that has not been output with the current time may be required. .

It is therefore an object of the present invention to provide a VTR control signal generation circuit capable of generating programmable timing data and pattern data.

[0007]

SUMMARY OF THE INVENTION The present invention provides control means for forming a plurality of timing information and pattern information from absolute time information, a RAM for storing the timing information and pattern information obtained by the control means, and a RAM. And a pattern signal generating means for outputting a pattern signal of the pattern information based on the timing information stored in the VTR.

[0008]

The pattern signal of the pattern data is output from the programmable pattern generator based on the timing data stored in the RAM. This simplifies complicated processing for data setting.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram of a video tape recorder to which the present invention is applied. In FIG. 1, when a rotary drum 2 having two heads 1A and 1B arranged opposite to each other at 180 ° is driven, a phase generator 3 extracts frequency information and phase information of the rotary drum 2 and outputs the information. A signal is supplied to a programmable pattern generator (hereinafter, referred to as PPG) 4. The video signals extracted by the heads 1A and 1B are supplied to the RF switch 6 via the amplifiers 5A and 5B. R
The F switch 6 is switched by a switching pulse SWP output from the PPG 4.

The output signal of the RF switch 6 is supplied to a video signal processing circuit 7 and a low-pass filter 8. The video signal supplied to the video signal processing circuit 7 is a luminance signal Y
And a chroma signal C. The luminance signal Y is FM-demodulated, and the chroma signal C is frequency-converted. Thereafter, the luminance signal Y and the chroma signal C are supplied to the memory 9 as output video signals. The memory 9 is a memory used, for example, at the time of variable speed reproduction, and only passes an output video signal at the time of normal reproduction. The timing of storing the video signal in the memory 9 is controlled by a memory write enable signal (hereinafter, referred to as an MWE signal) from the PPG 4.

On the other hand, the low-pass filter 8 extracts a PLT signal from the supplied video signal, and
It is supplied to the TF circuit 10. Further, the tracking timing signal input from the controller 1 is supplied to the ATF circuit 10 via the PPG 4. Note that P
The PG 4 includes, for example, two RAMs that store different timing data TD and pattern data. One of the two RAMs is selected by the switching pulse SWP, and the data of the RAM is stored in the ATF circuit 1.
0 is supplied.

In the ATF circuit 10, the low-pass filter 8
And a control signal PCS for controlling the phase of the capstan 11 based on the timing data supplied from the PPG 4. This control signal PCS is applied to the capstan 11 via the capstan driver 12. The phase of the capstan 11 is always controlled to an optimum state based on the supplied control signal PCS.

FIG. 2 is a circuit block diagram of the PPG 4 according to the present invention. In FIG. 2, the controller 1
Are connected to the RAM 22 and the RAM 23 via the bus 21. By the controller 1, the RAM 22 and RA
The following output timing data TD and pattern data PD are input to M23. That is, RAM2
2 includes timing data TD (T ₁ , T ₂ , T _3.
. ) And pattern data PD (D ₁ , D ₂ ,
D ₃ . . _. ) Is input. Further, timing data TD (t ₁ , t ₂ , t ₃ ...) And pattern data PD (d ₁ , d ₂ , d ₃ ...) Are input to the RAM 23.

The timing data TD and the pattern data PD of the RAM 22 and the RAM 23 are passed through a data select switch 24. Data select switch 24
Is the switching pulse SWP input from the terminal 25
Is controlled by The timing data TD of the RAM selected by the data select switch 24 is supplied to the timing comparator 27 via the timing data latch 26. The switching between the RAMs 22 and 23 is performed every vertical cycle. The timing comparator 2
7, the output signal PG of the phase generator 3 is supplied via a timing counter 28.

On the other hand, the output pattern data PD of the selected RAM is latched by the output data latch 30 via the output data circuit unit 29. Timing comparator 2
7 and the timing data TD supplied to the phase generator 3
, The control signal CS is supplied from the timing comparator 27 to the output data latch 30. By the control signal CS, the pattern data PD latched in the output data latch 30 is output via the buffer 31.

For example, the first switching pulse SWP
When the RAM 22 is selected, the above processing is performed on the timing data TD and the pattern data PD of the RAM 22, and the pattern data PD is output from the buffer 31. During this time, the timing data TD and the output pattern data PD of the RAM 23 are set via the controller 1.

In the next switching pulse SWP, RA
Switching from M22 to RAM23 is performed, and RAM2 is switched.
3, the same processing is performed on the timing data TD and the pattern data PD, and the pattern data P
D is output. During this time, the timing data TD and the pattern data PD of the RAM 22 are set via the controller 1. Thus, the switching pulse SW
Only by switching the RAM in which the timing data TD and the pattern data PD are stored at P, the data setting for tracking can be easily set.

FIG. 3 is a timing chart at the time of switching the data stored in the RAMs 22 and 23, for example, in the triple speed reproduction mode. FIG. 3A
During the period when the switching pulse SWP1 shown in FIG.
The video signal of the head 1A is extracted. In period 1, the MWE signals (MWE1 and MW
To output E2), the PLT signal is output at a timing as shown in FIG. 3C. The data table of the RAM 22 is supplied to the ATF circuit 10.

On the other hand, when the switching pulse SWP is set to low (period 2), the output signal of the head 1B is extracted from the RF switch 6. In period 2,
In order to output the MWE signal (MWE3), the PLT signal is output at a timing as shown in FIG. 3C. Also, R
The data table of AM 22 is supplied to the ATF circuit 10. Thus, by supplying the three MWE signals (MWE1, 2 and 3) to the memory 9, triple speed reproduction becomes possible. In addition, it is also possible to perform variable speed reproduction such as triple speed while switching the pilot signal.

[0020]

According to the present invention, the data for tracking can be easily set by automatically switching the RAM having the data table with the switching pulse as a trigger. Therefore, even when the reference signal is periodic and the end of the output signal is near the next reference signal, there is no need to divide the reference signal. Also,
When setting timing data and pattern data,
There is no need for complicated processing such as comparing the timing of data that has not been output with the current time.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a video tape recorder to which the present invention is applied.

FIG. 2 is a circuit block diagram of a programmable pattern generator.

FIG. 3 is a timing chart when switching data stored in a RAM.

[Explanation of symbols]

 1A, 1B Head 4 Programmable pattern generator 10 ATF circuit 22, 23 RAM

────────────────────────────────────────────────── (5) References JP-A-61-224788 (JP, A) JP-A-63-237248 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 15/467 H04N 5/782

Claims (4)

(57) [Claims] 1. A control means for forming a plurality of pieces of timing information and pattern information from absolute time information, and first and second storage means for storing the timing information and the pattern information obtained by the control means. Pattern signal generating means for outputting a pattern signal of the pattern information based on the timing information stored in the first and second storage means, wherein the first and second storages are performed at a timing of a vertical cycle. A control signal generation circuit for a VTR, which switches means. 2. The control signal generating circuit for a VTR according to claim 1, wherein said timing information and said pattern information are information for switching a pilot signal for ATF tracking control. 3. The VTR control signal generating circuit according to claim 1, wherein said timing information and said pattern information are information for realizing variable speed reproduction. 4. The VT according to claim 1, wherein the timing information and the pattern information switch a pilot signal for ATF tracking control and realize variable speed reproduction.
R control signal generation circuit.