JP3169810B2 - ATM echo canceller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an ATM (Asynchronous
ous Transfer Mode) This relates to an echo canceller for cellularized voices and the like.

[0002]

2. Description of the Related Art Heretofore, there have been few examples of this type of ATM cell level echo canceller, and even if there is little or no very small cell delay fluctuation of an echo superimposed cell at the subscriber's near end, the In most cases, only the delay is assumed to be semi-fixed and variable, and the cell loss is not considered much as it is small.

[0003]

In such a conventional technique, when the delay fluctuation of the input cell of the echo canceller fluctuates greatly, the echo superimposed cell input to the echo canceller and the echo canceler internal to cancel the echo are used. It becomes very difficult to match the phase with the pseudo echo signal generated in the step (1), which causes not only deterioration of the characteristics of the echo canceller but also a case where the echo canceller cannot be converged. Further, there is a problem that the cell loss greatly affects the convergence characteristics of the echo canceller, and the convergence is greatly delayed.

An object of the present invention is to provide a practical ATM echo canceller capable of effectively removing echoes even when delay fluctuations of input cells of the echo canceller fluctuate greatly.

[0005]

According to the present invention, there is provided an ATM echo canceller which receives and processes a far-end cell receiving circuit and a receiving cell of the far-end cell receiving circuit and generates a pseudo echo signal. A signal generation circuit, a near-end cell receiving circuit, and a capacity capable of absorbing an increase in a cell arrival delay due to fluctuations in a near-end cell due to a payload length of a cell received by the near-end cell receiving circuit; A pseudo echo signal accumulating circuit for temporarily accumulating a pseudo echo signal, an echo canceling circuit for removing and outputting an echo superimposed on the near-end receiving cell, and outputting a near-end receiving cell from which the echo has been eliminated. A pseudo-echo signal accumulation circuit and the near-end cell reception circuit are interconnected by a near-end cell reception completion notification signal line and a pseudo-echo signal accumulation completion notification signal line. The near-end cell reception completion notification signal line indicates that the near-end cell has been received, and the pseudo echo signal storage completion notification signal indicates to the pseudo echo signal storage circuit the payload length of the near-end cell. Notifying the mutually connected parties that the corresponding amount of pseudo echo signals has been completely stored, and only when the completion notification signals of the both notification signal lines match, the near-end side cell receiving circuit Sends the corresponding received cell and the pseudo echo signal storage circuit to the echo removal circuit in synchronization with the pseudo echo signal in an amount corresponding to the corresponding cell payload.

[0006] The ATM echo canceller according to claim 2 is:
The near-end cell receiving circuit and the pseudo echo signal storage circuit, when detecting a cell loss at each input, considers that a cell loss has occurred, and detects the near-end cell reception completion notification signal line or the pseudo echo signal storage Each completion notification signal is forcibly transmitted to the corresponding signal line of the completion notification signal line.

[0007] The ATM echo canceller according to claim 3 is:
The far-end cell receiving circuit is connected to the pseudo-echo signal storage circuit and the far-end cell loss notification signal line, and the near-end cell receiving circuit and the far-end cell receiving circuit detect a cell loss at each input. Assuming that there has been a cell loss, forcibly sending each notification signal to the corresponding signal line of the near-end cell reception completion notification signal line or the far-end cell loss notification signal line,
If the echo replica signal storage circuit receives a notification of the cell loss occurs at the far end side from the far end cell loss notification signal line, counted from the time that sent a signal to the echo replica signal storage completion notification signal line immediately before At the time when the average cell arrival interval is reached, a completion notification signal is forcibly transmitted to the pseudo echo signal accumulation completion notification signal line.

According to the first aspect of the present invention, in order to perform the echo canceling by subtracting the pseudo echo signal predicted and generated in advance, the arrival of the near end cell on which the echo is superimposed and the near end cell in the pseudo echo signal storage circuit are provided. The near-end cell receiving circuit and the pseudo-echo signal storage circuit connected to each other inform each other that the pseudo echo signal of the amount corresponding to the payload length of the packet has been completely stored, The cell receiving circuit transmits the received cell to the echo removing circuit by synchronizing the received cell with the pseudo echo signal storage circuit and the pseudo echo signal of the amount corresponding to the cell payload at the same time, thereby performing echo canceling in cell units. be able to.

According to a second aspect of the present invention, when one or both cells do not arrive due to a cell loss on the near end side or the far end side, the cell reception circuits on the near end side and the far end side independently detect cell loss. When a cell loss is detected, the reception completion notification signal is forcibly transmitted to each cell reception completion notification signal line, thereby reducing the cell reception waiting delay of the partner of the waiting received cell. Can be minimized.

[0010] The "waited received cell"
A cell that is in a state where it cannot be transmitted due to waiting for processing in a cell that has been received at the near end or the far end, and is a cell to be processed at the time of echo canceling. In this case, the target cell (the target cells) is received and processed until it is processed. Therefore, if there is a cell loss in the other party, it is waited until a timeout occurs. Strictly speaking, the effect differs between the near-end side and the far-end side. The effect on the received cell waiting at the near-end side is the largest, and a pseudo echo indicates that there is a cell loss in the corresponding cell on the far-end side. Transmission is delayed until the signal accumulation circuit (in the case of the embodiment of FIG. 1) times out. In this case, the “cell reception waiting delay of the other party” corresponds to a delay of waiting for the completion of accumulation of the pseudo echo signal generated from the far-end cell to the pseudo echo signal accumulation circuit. On the far end side, since the transmission delay of the user cell itself does not occur, the transmission waiting delay of the pseudo echo signal in the pseudo echo signal accumulation circuit generated from the far end side cell is set to "the waiting received cell". Would be equivalent. In this case, the “later cell reception waiting delay” corresponds to the waiting time until the near-end cell is received. In this case, the near-end cell reception circuit times out due to the near-end cell loss. However, as a result, only the transmission of the pseudo echo signal is delayed, and there is no direct delay outside the echo canceller, but in consideration of the subsequent recovery operation, the accumulated pseudo echo signal must be transmitted. There is.

In the second aspect, when a cell loss occurs in the far-end side input, the influence of the delay until the completion notification signal is forcibly output to the pseudo echo signal accumulation completion communication signal line is large,
The output cell is delayed by greatly affecting the signal after the echo cancellation until the end.

Therefore, in the third aspect, when the near-end cell receiving circuit and the far-end cell receiving circuit detect a cell loss at each input, the near-end cell receiving circuit and the far-end cell receiving circuit deem that there is a cell loss and complete the near-end cell receiving. The notification signal line or the corresponding signal line of the far-end side cell loss notification signal line is forcibly sent out each notification signal, and the pseudo echo signal storage circuit stores cells at the far end from the far-end side cell loss notification signal line. taking receiving notification of loss occurrence, just before <br/> echo replica signal storage completion notification signal line echo replica signal terminal ku product completion notification signal from the time that sent to the count to the time it reaches the average cell arrival interval A completion notification signal is forcibly transmitted to the signal line.

Thus, the timing at which the completion notification signal is output to the pseudo echo signal accumulation completion notification signal line is substantially the same as when there is no cell loss. The effect can be almost eliminated.

[0014]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an ATM echo canceller according to a first embodiment of the present invention, and FIG. 2 is a timing chart thereof. In FIG. 2, A and B are samples of cell headers on the far end side and near end side respectively attached for the sake of explanation, and serve as triggers for the corresponding signals. The corresponding positional relationship above is also shown.

The far-end cell input line 10 is connected to the far-end cell receiving circuit 1. The received cell on the far end side is checked for the cell header and AAL (ATN adaptation layer) in the far end side cell receiving circuit 1, and if the cell is recognized as a normal cell, the delay fluctuation (the cell arrival interval is set to the average cell arrival interval due to the fluctuation of the delay time). After the signal is absorbed by the pseudo-echo signal generation circuit 4 through the far-end cell receiving circuit output 11 and processed, the pseudo-echo signal is output from the pseudo-echo signal output 41. The output is temporarily stored in the pseudo echo signal storage circuit 6. The pseudo echo signal storage circuit 6 has a storage capacity enough to absorb the increase in the cell arrival delay due to the cell fluctuation at the near end to the payload length of the cell input from the near end input line 20, and the internal temporary storage circuit. When the pseudo echo signal is stored in an amount equal to or greater than the payload length of the cell at the near end, "1" is output to the pseudo echo signal accumulation completion notification signal 62 to indicate that the accumulation of the pseudo echo signal is completed. This is notified to the side cell receiving circuit 2.

The near-end input line 20 is connected to the near-end cell receiving circuit 2. The near-end cell receiving circuit 2 checks the cell header and AAL (ATM adaptation layer) of the received cell, and if there is no abnormality, outputs “1” to the near-end cell reception completion notification signal line 22 and outputs the signal to the near-end cell. The pseudo-echo signal accumulation circuit 6 is notified of the cell reception completion on the side. At this time, if the pseudo echo signal storage completion notification signal 62 from the pseudo echo signal storage circuit 6 is “1”, the corresponding reception cell on the near end side is brought closer to the echo removal circuit 5 in synchronization with the pseudo echo signal storage circuit 6. It is output from the end-side receiving cell output line 21.

After outputting "1" to the pseudo echo signal storage completion notification signal 62, the pseudo echo signal storage circuit 6 outputs the near end cell reception completion notification signal line 2 from the near end cell reception circuit 2.
When the near-end cell reception completion notification signal line 22 outputs "1", the near-end cell reception circuit 2 outputs a pseudo echo signal having a data amount corresponding to the payload of the corresponding cell.
Output to the echo removing circuit 5 from the pseudo echo signal output line 61 in synchronization with the output of the received cell.

The near-end receiving cell and the corresponding pseudo-echo signal of one cell input synchronously are subtracted by the echo removing circuit 5 to remove the echo superimposed on the near-end receiving cell. Is output to the far-end-side cell output circuit 3 through the echo removal output line 51, and is returned to the pseudo echo signal generation circuit 4 to be used for learning the impulse response parameters. The far-end cell output circuit 3 includes a cell header and AAL
After the restoration of the (ATM adaptation layer), it is output from the output line 31. Here, “learning of impulse response parameters” refers to an echo path (near end side) used when an echo canceller estimates a echo from an input signal (voice) and performs a convolution operation for generating a negative pseudo echo. Of the impulse response parameter is repeatedly changed from the residual echo remaining after the echo canceling, and the correction of the impulse response parameter is repeatedly performed so that the residual error is minimized.

FIG. 3 shows a case where a cell loss occurs in the far-end input cell Rin when the near-end side cell receiving circuit 2 and the pseudo echo signal accumulating circuit 6 have independent cell receiving interval observation timers. . T represents the average cell arrival interval, α is the delay increase due to the far-end fluctuation, γ is the negative delay increase due to the far-end fluctuation, β is the delay increase due to the near-end fluctuation, and δ is the near-end fluctuation. This represents a negative delay increase due to fluctuation on the end side.

The received cell stream Rin from the far-end input, FIG.
In the case of, the next cell following the cell header A is lost due to cell loss (cell loss), and the cell is normally received thereafter. Similarly, the received cell flow Sin from the near-end input indicates that a cell loss has occurred at the far-end input at a position corresponding to the cell header B.

The far-end cell receiving circuit 1 has a far-end input Ri
Since n has been input, the output signal 11 of the far-end side cell receiving circuit 1 has lost the cell to come after the cell header A due to cell loss. FIG. 3 shows a state in which a pseudo echo signal to be output to the output signal 41 of the pseudo echo signal generation circuit 4 cannot be generated because there is no input cell signal in a portion where cell loss occurs in the signal 11. The signal 22 for notifying the pseudo echo signal storage circuit 6 of the completion of the reception of the near-end cell is set to "1" every time the reception of the input Sin on the near-end side in the cell unit is completed. A signal 62 for notifying the near-end cell receiving circuit 2 of the completion of the accumulation of the pseudo echo signal is output every time the pseudo echo signal output 41 is accumulated for one cell.
1 ", but in the case of FIG.
Since the pseudo echo signal output 41 at the point where the cell loss has occurred is not output, it is not set to “1” at the normal position,
The signal 62 is forcibly set when the cell reception interval observation timer of the pseudo echo signal storage circuit 6 has timed out.
When both the signal 22 and the signal 62 are set to "1", the near-end measurement cell receiving circuit 2 and the pseudo echo signal storage circuit 6 synchronize and the near-end measurement reception cell output line 21 The pseudo-echo signal output line 61 outputs the near-end measurement reception cell and the stored pseudo-echo signal, respectively. Therefore, the echo canceling circuit 5 performs the echo canceling by subtracting the pseudo-echo signal from the near-end reception cell. And outputs the result to the echo removal output line 51.

In the case of FIG. 3, the effect of the delay until the signal 62 is set to "1" due to timeout is large, and the signal 51 after the echo canceling is also greatly affected to the end to delay the output cell. .

FIG. 4 is a time chart for explaining the operation when a cell loss occurs in the near-end side input Sin. The difference from FIG. 3 is that the cell reception interval observation timer of the near-end side cell receiving circuit 2 sets a timeout. Signal 22
Is set to "1", and the signal 62 is set to "1" every time accumulation of the pseudo echo signal output 41 for one cell is completed. The meaning and operation of the other signals are exactly the same as those in FIG.

The cell loss at the near-end side input as shown in FIG. 4 does not affect the delay to the echo removal output line 51 (because the cell receiving the delay is not missing).

FIG. 5 is a block diagram of an ATM echo canceller according to a second embodiment of the present invention. In the present embodiment, the near-end cell receiving circuit 2 and the far-end cell receiving circuit 1 are provided with independent cell receiving interval observation timers, respectively. Observe the interval,
Further, the far-end cell receiving circuit 1 observes the receiving interval at which the far-end receiving cell arrives, and arrives at each cell even if it exceeds the maximum fluctuation delay time (average cell arrival interval + delay fluctuation difference) of each receiving circuit. When there is no input cell, it is considered that a loss has occurred in each input cell, and "1" is forcibly transmitted to the corresponding signal line of the near-end cell reception completion notification signal line 22 or the far-end cell loss notification signal line 12. I do.

FIG. 6 shows an output signal 51 when a cell loss occurs at the far-end side input Rin, which is a problem in the case of FIG.
6 is a time chart for explaining the operation of the embodiment (FIG. 5) in which the increase in the output delay in FIG.

FIG. 6 shows a case where the next cell after the cell header A is lost in the far-end side input Rin in exactly the same manner as in FIG. 3, and the subsequent cells are normally received. I have. In the embodiment of FIG. 6 (FIG. 5), unlike the embodiment of FIG. 3 (FIG. 1), the cell reception interval observation timer of the cell arriving at the far-end input Rin is set to the far-end cell reception circuit 1.
(In the case of FIG. 3, the cell reception interval observation timer on the far end side is provided in the pseudo echo signal accumulation circuit 6). As for the near-end input Sin, the operation of the near-end cell reception interval observation timer is the same in both the cases of FIGS. Description is omitted.

In FIG. 6, when the cell arriving at the far-end input Rin is lost due to cell loss, the far-end cell receiving circuit 1 calculates (average cell arrival interval T + difference α of far-end delay fluctuation).
, A timeout occurs, and the far-end cell loss communication signal line 12 is forcibly set to "1".

The meanings of the signals other than the signal 12 in FIG. 6 are the same as those in FIG.
Is different from the case of FIG. When the far-end cell loss communication signal line 12 from the far-end cell receiving circuit 1 is set to "1", the pseudo echo signal storage circuit 6 sets the previous pseudo echo signal storage completion notification signal line 62 to "1". When the count reaches the average cell arrival interval T counted from the time set in (1), the pseudo echo signal accumulation completion notification signal line 62 is forcibly set to "1".

Thereafter, the operation is exactly the same as that of FIG. 3, but the timing at which the pseudo echo signal accumulation completion notification signal line 62 is set to "1" is almost the same as when there is no cell loss. In addition, as shown in FIG. 6, the influence on the cell output signal 51 after the echo canceling can be almost eliminated.

[0032]

As described above, the present invention has an effect that the echo can be effectively removed even when the delay fluctuation of the input cell of the echo canceller fluctuates greatly.

[Brief description of the drawings]

FIG. 1 is a block diagram of an ATM echo canceller according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the first embodiment.

FIG. 3 is a diagram showing a case where a cell loss has occurred in a far-end-side input cell in the timing chart of FIG. 2;

FIG. 4 is a diagram showing a case where a cell loss occurs in a near-end input cell in the timing chart of FIG. 2;

FIG. 5 is a block diagram of an ATM echo canceller according to a second embodiment of the present invention.

FIG. 6 is a timing chart showing a case where a cell loss has occurred in a far-end side input cell in the second embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Far end side cell receiving circuit 2 Near end side cell receiving circuit 3 Far end side cell output circuit 4 Pseudo echo signal generation circuit 5 Echo removal circuit 6 Pseudo echo signal accumulation circuit 10 Far end side input line 11 Far end side cell receiving circuit Output 12 Far-end cell loss notification signal line 20 Near-end input line 21 Near-end reception cell output line 22 Near-end cell reception completion notification signal line 31 Far-end output line 41 Pseudo echo signal output 51 Echo removal output line 61 pseudo echo signal output line 62 pseudo echo signal accumulation completion notification signal Rin Far end side input cell Sin Near end side input cell

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroshi Fujitani 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Kazuma Miura 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-7-111479 (JP, A) JP-A-8-125592 (JP, A) JP-A-7-46247 (JP, A) JP-A-8-186571 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04B 3/23 H03H 21/00 H04Q 3/00 H04L 12/28

Claims (3)

(57) [Claims] A far-end cell receiving circuit; a pseudo-echo signal generation circuit for inputting and processing a reception cell of the far-end cell receiving circuit to generate a pseudo-echo signal; a near-end cell receiving circuit; A pseudo echo signal having a capacity enough to absorb the increase in cell arrival delay due to the fluctuation of the cell at the near end to the payload length of the cell received by the near end cell receiving circuit, and temporarily storing the pseudo echo signal. A storage circuit, an echo removal circuit that removes and outputs an echo superimposed on the near-end receiving cell, and a far-end cell output circuit that outputs the near-end receiving cell from which the echo has been removed, The pseudo-echo signal accumulation circuit and the near-end cell reception circuit are interconnected by a near-end cell reception completion notification signal line and a pseudo-echo signal accumulation completion notification signal line, and the near-end cell reception completion notification signal line is Near end The pseudo-echo signal storage completion notification signal is connected to the pseudo-echo signal storage circuit to indicate that the pseudo-echo signal storage completion signal has been stored in the pseudo-echo signal storage circuit in an amount corresponding to the payload length of the near-end cell. Only when the completion notification signals of the two notification signal lines match each other, the near-end cell receiving circuit determines the corresponding reception cell, and the pseudo echo signal storage circuit does not. An ATM echo canceller for synchronizing and sending a pseudo echo signal of an amount corresponding to a cell payload to the echo canceling circuit. 2. The near-end cell receiving circuit and the pseudo echo signal accumulating circuit, when detecting a loss of a cell at each input, consider that a cell loss has occurred, and notify the near-end cell reception completion notification signal line. 2. The ATM echo canceller according to claim 1, wherein each completion notification signal is forcibly transmitted to a corresponding signal line of the pseudo echo signal accumulation completion notification signal line. 3. The far-end cell receiving circuit is connected to the pseudo echo signal storage circuit by a far-end cell loss notification signal line, and the near-end cell receiving circuit and the far-end cell receiving circuit are When a cell loss is detected at the input, it is regarded that a cell loss has occurred, and the respective notification signals are forcibly applied to the corresponding signal line of the near-end cell reception completion notification signal line or the far-end cell loss notification signal line. When the pseudo echo signal storage circuit receives the notification of the occurrence of the cell loss at the far end from the far end cell loss notification signal line, the pseudo echo signal storage circuit transmits the signal to the pseudo echo signal storage completion notification signal line immediately before. 2. The ATM echo canceller according to claim 1, wherein a completion notification signal is forcibly transmitted to the pseudo echo signal accumulation completion notification signal line at a time when an average cell arrival interval is counted from a time.