JP3168683B2 - Switching power supply - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply for supplying a drive signal to a switching element by synchronizing an oscillation frequency of an oscillator with an external synchronization signal.

[0002]

2. Description of the Related Art In general, a switching power supply having a plurality of power conversion circuits is disclosed in, for example, an inverter circuit having a transformer and a switching element.
No. 261 is known. In such a power supply device, a control IC having an oscillator as a feedback circuit is independently used in order to control a pulse conduction width of a switching element included in an inverter circuit and a power factor correction circuit.
Due to the beat generated due to the difference in oscillation frequency between the oscillators, feedback noise from the power supply side to the input voltage line increases. Therefore, in order to reduce the feedback noise, there has conventionally been proposed a device that externally supplies a synchronization signal to each control IC and synchronizes the oscillator with a frequency based on the synchronization signal.

That is, as shown in FIG. 3, a rectifier circuit 2 composed of a diode bridge is connected to both ends of a commercial power supply 1 via input terminals + V1, -V1, and a switching element 3 composed of a MOS FET is connected to the rectifier circuit 2. And a power factor improvement circuit 6 which is a power conversion circuit composed of an inductance 4 and a diode 5, and outputs a boosted voltage by switching by the switching element 3. A smoothing capacitor 7 for smoothing the boosted voltage is connected between the output terminals of the power factor correction circuit 6, and resistors 8, 9 for dividing the DC input voltage Vi smoothed by the smoothing capacitor 7. And an operational amplifier 10 for comparing and amplifying the input detection voltage divided by the resistors 8 and 9 with the reference voltage, and the pulse width control of the switching element 3 based on the signal amplified and amplified by the operational amplifier 10 The control IC 11 is provided as a feedback circuit of the power factor correction circuit 6. The control IC 11 includes a PWM comparator 12 and an oscillator 13 that supplies a sawtooth wave to the PWM comparator 12.
And a driver circuit 14 for driving the switching element 3. The PWM comparator 12 compares a signal amplified and compared from the operational amplifier 10 with a saw-tooth wave output from the oscillator 13. A driving signal having a pulse conduction width based on the driving signal is supplied to the switching element 3 via the driver circuit 14. That is, when the switching element 3 is on, the power factor correction circuit 6
Energy is stored in the inductance 4 by the DC current from the rectifier circuit 2. When the switching element 3 is off, the energy stored in the inductance 4 is superimposed on the voltage supplied from the rectifier circuit 2 and output.
Numeral 11 indicates a change in the DC input voltage Vi detected by the resistors 8 and 9, the voltage waveform and the current waveform from the AC power supply are brought close to each other, and the energy stored in the inductance 4 via the switching element 3 so as to improve the input power factor. Control.

The DC input voltage Vi is connected to the transformer 15 and M
It is supplied to an inverter circuit 17 as a power conversion circuit including a switching element 16 composed of an OS type FET. Then, by switching the switching element 16, the voltage induced from the secondary winding of the transformer 15 is rectified and smoothed by the rectifying and smoothing circuit 18, and a DC output voltage Vo is supplied between the output terminals + V2 and -V2. Also, the inverter circuit
As a feedback circuit of 17, a series circuit of resistors 19 and 20 connected between the output terminals + V2 and -V2 to divide the DC input voltage Vi and an output detection voltage and a reference voltage divided by the resistors 19 and 20 are provided. Operational amplifier 21 for comparison and amplification, and this operational amplifier
Switching element 16 based on the signal amplified and compared at 21
And a control IC 11A for controlling the pulse width. Then, in the control IC 11A, the PWM comparator 12
A compares the amplified signal from the operational amplifier 21 with the sawtooth wave output from the oscillator 13A, and supplies a drive signal having a pulse conduction width based on the comparison result to the switching element 16 via the driver circuit 14A. Then, control is performed so as to keep the DC output voltage Vo constant.

[0005] The oscillator 13 incorporated in the control IC 11 has a timing capacitance terminal CT and a timing resistance terminal RT for setting the oscillation frequency. A series circuit of a capacitor 22 and a resistor 23 is connected between the timing capacitor terminal CT and the ground.
A synchronization signal generation circuit 25 that outputs a pulsed reset synchronization signal via a capacitor 24 is connected to the connection point with
Further, a constant current generating resistor 26 is connected between the timing resistor terminal RT and the ground. Similarly, in the control IC 11A, a series circuit of a capacitor 22A and a resistor 23A is connected between the timing capacitor terminal CT and the ground, and a connection point between the capacitor 22A and the resistor 23A is connected via the capacitor 24A to the synchronous circuit. A signal generating circuit 25 is connected, and a resistor 26A is connected between the timing resistor terminal RT and the ground.
Connect.

FIG. 4 shows a waveform diagram of the timing capacitor terminal CT. In the control IC 11, the current flowing from the timing capacitance terminal CT to the capacitor 22 is set based on the current flowing from the timing resistance terminal RT to the resistor 26, and is controlled by a time constant circuit formed by the capacitor 22 and the resistor 26. The capacitor 22 is charged to increase the terminal voltage of the timing capacitor terminal. The terminal voltage of the timing capacitor terminal CT is always the control I
When this terminal voltage exceeds a high-level threshold voltage, which is a first set voltage preset in the oscillator 13, the capacitor 22 is forcibly discharged and a predetermined second voltage is detected . 2 settings
Upon reaching the Low level of the threshold voltage is a voltage, by repeating the operation for charging the capacitor 22 again, a sawtooth wave having an oscillation frequency based on the charge and discharge time from the Low level to reach the threshold voltage of the High-level , From the oscillator 13 to the non-inverting input terminal of the PWM comparator 12. At this time, when a reset synchronizing signal is applied from the synchronizing signal generation circuit 25 to the connection point between the capacitor 22 and the resistor 23 in a cycle shorter than the charging / discharging time defined by the capacitor 22 and the resistor 26, the terminal voltage of the timing capacitor terminal CT Is superimposed on the charging voltage of the capacitor 22 and exceeds the high-level threshold voltage, thereby forcibly discharging the capacitor 22. Therefore, the control IC 11 oscillates based on the cycle of the reset synchronization signal supplied from the outside. It will operate with a sawtooth wave having a frequency. This is the inverter circuit 17
The same applies to the timing capacitance terminal CT of the control IC 11A for controlling the synchronization signal generation circuit.
The oscillation frequency of the oscillator 13A is determined based on the period of the reset synchronization signal applied from 25 to the connection point between the capacitor 22A and the resistor 23A. Therefore, the control ICs 11, 11
A is synchronized by the reset synchronizing signal from the synchronizing signal generating circuit 25, and no beat occurs due to the difference in frequency between the oscillators 13 and 13A, so that feedback noise can be reduced.

[0007]

In the prior art, the frequency of the reset synchronizing signal from the synchronizing signal generating circuit 25 is widely varied in a cycle shorter than the charging / discharging time determined by the capacitor 22 and the resistor 26. Then, especially, the cycle of the reset synchronization signal is short, and the capacitor
When the reset synchronizing signal is output while the charging voltage of the terminal 22 is low, the terminal voltage of the timing capacitor terminal CT is set to H
When the capacitor 24 having a large capacity is required to increase the voltage to a level higher than the threshold voltage of the high level, and as shown in FIG.
Since the peak-to-peak voltage value Vp of the timing capacitor terminal CT immediately before the supply of the reset synchronization signal also changes, the gain of the feedback loop changes significantly, and stable control is not performed. That is, in this type of switching power supply device, the frequency variation range of the reset synchronization signal that can maintain the synchronization of the control ICs 11 and 11A is only about 10 to 20%, and the frequency variation of the reset synchronization signal is wide. There is a problem that it is difficult to add a required output voltage variable circuit, an overcurrent protection circuit, and the like.

Accordingly, an object of the present invention is to solve the above problems and to provide a switching power supply device capable of varying the frequency of a reset synchronization signal over a wide range.

[0009]

The present invention comprises a plurality of power conversion circuits having switching elements, and independently uses a control IC having a built-in oscillator as a feedback circuit for controlling each of the switching elements. In the control IC,
The timing capacitor terminal to which a capacitor is connected and this
The amount of current flowing from the
And a timing resistor terminal for setting
This capacitor is charged by the flowing current,
The terminal voltage of the capacitor terminal rises and exceeds the first set voltage
And discharge the capacitor, and the timing capacitance terminal
When the terminal voltage of
The operation of charging the capacitor again is repeated.
The terminal voltage of the timing capacitor terminal of the second setting
The time from the voltage to reach the first set voltage, before
And sets the oscillation frequency of the serial oscillator, to synchronize the oscillation frequency of each oscillator, for each control
This timing capacitor terminal is connected to each timing capacitor terminal of the IC.
Period of the switching power supply apparatus provided with a synchronizing signal generation circuit, the reset synchronization signal terminal voltage of supplying reset <br/> preparative synchronizing signal which exceeds the first set voltage
Is shorter, the capacitor from the timing capacitor terminal is shorter.
To increase the current flowing through the
Shorter, the longer the cycle of the reset synchronization signal,
The current flowing from the timing capacitor terminal to the capacitor is
A current adjustment circuit for reducing the charge time of the capacitor is connected between the synchronization signal generation circuit and the timing resistor terminal.

[0010]

According to the above arrangement , the reset circuit is provided by the current adjusting circuit .
The shorter the period of the sync signal, the shorter the
Increase the current flowing through the capacitor
The charging time is shortened and the cycle of the reset synchronization signal is long.
The current flowing from the timing capacitor terminal to the capacitor
To increase the charging time of this capacitor,
The peak-to-peak voltage value of the timing capacitor terminal CT immediately before the supply of the reset synchronization signal is kept constant, and the change in the gain of the feedback loop is suppressed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, the same parts as those in FIG. 3 shown in the conventional example are denoted by the same reference numerals, and detailed description of the common parts will be omitted.

A current adjustment circuit 32 having a frequency / voltage conversion circuit 31 is connected between the timing resistance terminal CT of the oscillator 13 incorporated in the control IC 11 and the synchronization signal generation circuit 25. The frequency / voltage conversion circuit 31 supplies the reset synchronization signal from the synchronization signal generation circuit 25 to the base of the transistor 33 whose emitter is grounded, and connects a capacitor 34 between the collector of the transistor 33 and the ground. A current source 35 and a sample and hold circuit 36 for holding a peak voltage at the connection point are connected to a connection point between the collector and the capacitor 34, respectively. Also,
The bases of a pair of transistors 37 and 38 are connected together, and the collector of one transistor 37 and a sample-and-hold circuit
A current limiting resistor 39 is inserted and connected between the outputs of the transistor 36, and the collector and the base of the transistor 37 are connected to supply a predetermined reference voltage to the emitter. Further, the collector of the other transistor 38 is grounded, and a current limiting resistor 40 is connected between the emitter of the transistor 38 and the timing resistor terminal RT of the oscillator 11, thereby forming the current adjusting circuit 32. A current adjusting circuit 32A is also connected between the oscillator 11A and the synchronizing signal generating circuit 25. The current adjusting circuit 32A, like the current adjusting circuit 32, includes a transistor 33A, a capacitor 34A, a current source 35A, and a sample and hold circuit 36A. / Voltage conversion circuit consisting of
The circuit configuration is the same as that of FIG. 3 except that a current limiting resistor 39A and a current limiting resistor 40A are connected to a pair of transistors 37A and 38A.

Next, the operation of the above configuration will be described. When the power is turned on, the AC power supply voltage from the commercial power supply 1 is rectified by the rectifier circuit and supplied to the power factor correction circuit 6, and the voltage boosted by switching by the switching element 3 is smoothed by the smoothing capacitor 7. The DC input voltage Vi is supplied to the inverter circuit 17. The DC input voltage Vi is divided by the resistors 8 and 9, and the divided input detection voltage is compared and amplified by the operational amplifier 10 with the reference voltage and supplied to the control IC 11. The control IC 11 is a PWM
The comparator 12 compares the amplified signal from the operational amplifier 10 with the sawtooth wave from the oscillator 13, and switches the voltage waveform and the current waveform from the AC power supply closer through the driver circuit 14 based on the comparison result. The pulse width of the element 3 is controlled. Further, in the inverter circuit 17, the voltage induced in the secondary winding of the transformer 15 by the switching of the switching element 16 is converted into a rectifying and smoothing circuit 18.
To supply a DC output voltage Vo between the output terminals + V2 and -V2.
An output detection voltage obtained by dividing the voltage by resistors 19 and 20 is compared with a reference voltage by an operational amplifier 21 and supplied to a control IC 11A. The PWM comparator 12A is an operational amplifier
The signal amplified and compared from 10A is compared with the sawtooth wave from the oscillator 13A, and the driver circuit 14
, The pulse width of the switching element 16 is controlled so that the DC output voltage Vo is stabilized. The above is the same operation as the conventional example.

On the other hand, in the frequency / voltage conversion circuit 31 of the current adjustment circuit 32, when the transistor 33 is off, the current flowing from the current source 35 is supplied to the capacitor 34, and the connection point between the capacitor 34 and the current source 35 Is gradually increased by charging the capacitor. In addition, the synchronization signal generation circuit 25
When the reset synchronizing signal is output to the base of the transistor 33, the transistor 33 is turned on, the capacitor 34 is discharged, and the potential at the connection point between the capacitor 34 and the current source 35 drops. Then, the sample and hold circuit 36
Holds a peak voltage at a connection point between the capacitor 34 and the current source 35, applies a predetermined output voltage to the resistor 39 based on the peak voltage, and supplies a pair of transistors 37,
Supplied as 38 base currents. At this time, based on the collector current flowing through one transistor 37, the collector current of the other transistor 38 also flows, and the transistors 37, 37
38 operates as a so-called current mirror. In other words, the shorter the cycle of the reset synchronization signal, the more the capacitor 34
When the potential at the connection point between the
Is discharged, the sample-and-hold circuit 36 connects the resistor 40 from the timing resistor terminal RT through the transistors 37 and 38.
And the charging time of the capacitor 22 connected to the timing capacitor terminal CT is shortened. On the other hand, the longer the cycle of the reset synchronization signal, the longer the capacitor 34 and the current source.
Since the capacitor 34 is discharged in a state where the potential of the connection point with the node 35 is high, the sample hold circuit 36 reduces the current flowing from the timing resistor terminal RT to the resistor 40,
Extend the charging time of 22. This is the same effect in the current adjustment circuit 32A. At this time, the waveform of the timing capacitor terminal CT becomes as shown in FIG. 2, and when the frequency of the reset synchronizing signal becomes lower than the frequency of the reset synchronizing signal shown by the solid line as shown by the broken line, the current adjusting circuit 32 charges the capacitor 22. In the state where the reset synchronizing signal is not supplied, the timing capacitor C
The rise of the terminal voltage of T becomes gentle. Therefore, regardless of the frequency of the reset synchronizing signal, the peak-to-peak voltage value Vp of the timing capacitor terminal CT immediately before the supply of the reset synchronizing signal becomes substantially constant, and while the change in the gain of the feedback loop is suppressed, each control IC 11 , 11A, the synchronization of the oscillators 13 and 13A by the reset synchronization signal is stably performed.

According to the embodiment as described above, the current adjusting circuit 32, 32A, Lise from the synchronizing signal generating circuit 25
The shorter the period of the synchronization signal, the shorter the timing capacitor terminal C
The current flowing from T to the capacitor 22 is increased,
The shorter the charging time of the capacitor 22 and the longer the period of the reset synchronization signal from the synchronization signal generation circuit 25 ,
Reduce the current flowing from the terminal CT to the capacitor 22
Since the charging time of the capacitor 22 is increased, the peak-to-peak voltage value Vp of the timing capacitor terminal CT immediately before the reset synchronization signal is supplied is always constant even when the frequency of the reset synchronization signal changes unlike the conventional example. Thus , the power factor improving circuit 6 and the inverter circuit 17 can make the influence on the gain of the feedback loop extremely small. Therefore, even if the frequency of the reset synchronizing signal is varied at least twice or more, each of the control ICs 13 and
Stable control by 13 A is continuously performed, and an output voltage variable circuit, an overcurrent protection circuit, and the like can be easily added.

Further, even if the cycle of the reset synchronizing signal is shortened, the peak-to-peak voltage value Vp of the timing capacitance terminal CT is always kept constant, so that the capacitor 24 having a small capacitance is used.
, The terminal voltage of the timing capacitor terminal CT is set to Hig.
It is possible to increase the threshold voltage to a level equal to or higher than the h-level threshold voltage, and it is also possible to reduce the size of the device.

The present invention is not limited to the above embodiment, and various modifications can be made. For example, the switching element is not limited to a MOS FET, but may be a transistor or the like, and the switching power supply device can be applied not only to a single-type forward type but also to various types such as a bridge type and a push-pull type.

[0018]

According to the present invention, there is provided a control IC having a plurality of power conversion circuits each having a switching element and having an oscillator as a feedback circuit for controlling each of the switching elements.
And a capacitor is connected to this control IC.
Connected timing capacitor terminal and this timing capacitor terminal
Timing to set the amount of current flowing from the capacitor to the capacitor
Resistor terminal, and the current flowing through the capacitor
Of the timing capacitor terminal is charged
When the voltage rises and exceeds the first set voltage, the capacitor
And the terminal voltage of the timing capacitor terminal becomes low.
When the capacitor reaches the second set voltage, the capacitor is reset.
The charging operation is repeated.
The terminal voltage of the switching capacitor terminal is changed from the second set voltage to the second voltage.
The time required to reach the set voltage of 1 is determined by the oscillation of the oscillator.
And sets as the frequency, in order to synchronize the oscillation frequency of each oscillator, each of the respective control IC Timing
The terminal voltage of this timing capacitor terminal is
In a switching power supply device provided with a synchronizing signal generating circuit for supplying a reset synchronizing signal exceeding the first set voltage, the shorter the cycle of the reset synchronizing signal is,
Current flowing from the timing capacitor terminal to the capacitor
To shorten the charging time of this capacitor,
The longer the period of the set synchronization signal, the more the timing capacity
Reduce the current flowing from the
A current adjusting circuit for extending the charging time of the capacitor connected between the synchronizing signal generating circuit and the timing resistor terminal, thereby providing a switching power supply device capable of varying the frequency of the reset synchronizing signal over a wide range. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a switching power supply device according to the present invention.

FIG. 2 is a waveform diagram of a timing capacitor terminal according to the first embodiment;

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is a waveform diagram of a timing capacitor terminal according to the first embodiment;

[Explanation of symbols]

 3,16 switching element 6 power factor improvement circuit (power conversion circuit) 11,11A control IC 13,13A oscillator 15 inverter circuit (power conversion circuit)22, 22A capacitor  32 Current adjustment circuit CT Timing capacitance terminal RT Timing resistance terminal

Claims (1)

(57) [Claims] 1. A control IC having a plurality of power conversion circuits having switching elements and a built-in oscillator as a feedback circuit for controlling each of the switching elements is used independently, and the control IC includes a capacitor. Connected to
From the timing capacitor terminal and the
Timing resistor terminal that sets the amount of current flowing to the capacitor
The capacitor is connected to the capacitor by a current flowing through the capacitor.
The capacitor is charged and the terminal voltage of the timing capacitor terminal rises.
When the voltage rises and exceeds the first set voltage, the capacitor is discharged.
And the terminal voltage of the timing capacitor terminal decreases,
When the set voltage of 2 is reached, the capacitor is charged again.
The timing capacitor end at this time.
The terminal voltage of the slave is changed from the second set voltage to the first set voltage.
The time required to reach the voltage is defined as the oscillation frequency of the oscillator.
In order to synchronize the oscillation frequencies of the respective oscillators, the respective timing capacitors of the respective control ICs are set.
The terminal voltage of the timing capacitor terminal is applied to the first terminal.
In a switching power supply device provided with a synchronizing signal generating circuit for supplying a reset synchronizing signal exceeding a set voltage, the shorter the period of the reset synchronizing signal, the more the timer
The current flowing from the
To shorten the charging time of this capacitor,
The longer the period of the synchronization signal, the more the timing capacitor terminal
Reduce the current flowing through the capacitor
A switching power supply device, wherein a current adjusting circuit for increasing a charging time of the power supply is connected between the synchronization signal generating circuit and the timing resistor terminal.