JP3168595B2 - Sync signal addition circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an SMPTE D-1.
The present invention relates to a synchronization signal adding circuit suitable for application to a component digital VTR of a type.

[0002]

2. Description of the Related Art In a SMPTE D-1 type component digital VTR or the like, since a recorded digital video signal does not have a synchronization signal added thereto, when a reproduced digital video signal is output as an analog video signal, it is reproduced. It is necessary to add a composite synchronizing signal such as a horizontal synchronizing signal and a vertical synchronizing signal digitally or analogly to the digital video signal.

FIG. 4 is a system diagram showing an example of a synchronization signal adding circuit 10 used in such a case. In the figure, a reproduced digital video signal is supplied via a terminal 12 to a latch circuit 14 functioning as a bit shift circuit. The digital video signal is quantized by 8 bits, and the definition of quantization at that time is well known, and the peak white level is (E) in 235 ° hexadecimal H display.
B) H, the same applies to the following display, and the black level is quantized to correspond to 16 (10) H.
In order to further add a digital synchronizing signal to this black level as it is, the number of bits on the lower side is insufficient (the same applies to the case of using an analog synchronizing signal).

Therefore, as described above, the latch circuit 14
To perform the bit shift processing. In the figure, 10
The digital video signal is input to the upper 8 bits of the bits, and the lower 2 bits have a fixed value. And
The upper 9 bits are taken out at the output side. The bit-converted digital video signal is converted into an analog signal by a D / A converter 16, and after being subjected to band limitation by a low-pass filter 18, is output via an amplifier 20 to an output terminal 22.
It is led to. On the output terminal 22 side, a synchronization adding means 30 is provided.
Is connected.

In this embodiment, since a digital video signal is converted into an analog signal and then an analog synchronizing signal (horizontal synchronizing signal) is added, an analog synchronizing signal is supplied to a terminal 32, which is a low-pass filter. 34
And is subject to band limiting. The reason for limiting the band is that if the rising and falling of the synchronization signal is sharp,
This is because ringing occurs at the change point when the synchronization signal is added.

When a band-limited synchronization signal is input,
When the switching transistor Q is turned on, a synchronization signal is added during the horizontal blanking period (black level) of the video signal.

[0007]

In the conventional synchronizing signal adding circuit, when a synchronizing signal is added as an analog signal, a synchronizing adding means 30 is required as shown in FIG. The signal adding means 30 must be provided with a low-pass filter 34 for preventing ringing. Therefore, only a synchronizing signal whose waveform has been reduced can be added to the video signal. Switching noise generated when the switching transistor Q is turned on cannot be removed.

In the case of a progressive scan signal (NTSC or PAL non-interlace scan signal) performed using two digital VTRs, a ternary synchronization signal is used. In such a case, the synchronization signal cannot be added by using the synchronization adding means 30 itself. This is because the synchronization signal is a ternary signal.

In view of the above, the present invention solves such a conventional problem, and proposes a synchronizing signal adding circuit capable of adding a synchronizing signal purely digitally.

[0010]

According to the present invention, there is provided a synchronization signal adding circuit for adding a synchronization signal to a reproduced digital video signal.
A pair of latch circuits capable of inputting a predetermined number of bits larger than the quantization bit number N (N is an integer) of the digital video signal; Supplied,
A bit-converted M-bit (M> N) digital video signal is output, and the N-bit digital synchronizing signal is bit-converted into an M-bit digital synchronizing signal in the other latch circuit. The digital synchronization signal is added to the digital video signal in a state where the number of bits is matched with the digital video signal.

[0011]

As shown in FIG. 1, the 8-bit reproduced digital video signal Sa supplied to the terminal 12 is supplied to the latch circuit 40 in a state shifted down by 1 bit. At this time, assuming that the most significant bit is always at the high level, the black level 16 (10) H at the time of 8-bit is converted to 54 by 10-bit conversion.
5 (221) H.

The sync chip portion of the synchronizing signal is lowered by 188 from the black level 545. However, since the black level is 545, the synchronizing signal is digitally converted as it is to the digital video signal after 10-bit conversion. Can be added to Actually, it is used as a 9-bit digital signal. Therefore, first read the data from the digital synchronization signal data storage unit 46 as 8-bit data, 10-bi enter this into the latch circuit 48
As well as the converted 10-bit data.
Output the upper 9 bits of the data as output data.
You. In other words, 8-bit input data is bit-converted into 9-bit data. After performing bit matching with the digital video signal, a digital synchronizing signal is added to the digital video signal at a predetermined timing, and then converted into an analog signal.

As described above, a sufficient dynamic range for adding a digital synchronization signal to a digital video signal can be ensured by the bit shift. Since the synchronization signal can be digitally added, the synchronization signal may be binary data or ternary data.

[0014]

Next, a case where an example of a synchronization signal adding circuit according to the present invention is applied to the above-described component digital VTR will be described in detail with reference to the drawings.

FIG. 1 shows an example of a synchronizing signal adding circuit 10 used in the above-described component digital VTR. The same parts as those in FIG. In the following, an example is shown in which a video signal without a sync signal is selectively output in addition to a video signal to which a sync signal is added. As described above, the rotary magnetic head device (not shown) is connected to the terminal 12.
Is input. The digital video signal Sa is quantized by 8 bits (= N bits).

A description will be given of a system that outputs a video signal without adding a synchronizing signal thereto. A digital video signal Sa supplied to a terminal 12 (a digital synchronizing signal shown in FIG. The same applies to Sc.) The upper 8 bits of the 10-bit latch circuit 14 are input, and the upper 9 bits of the output 10 bits are used as the output. The bit-converted digital video signal is converted into an analog signal in the D / A converter 16. The analogized video signal is supplied to a level attenuating means 56 and a switching means 54 which will be described later.
The signal is supplied to the low-pass filter 18 through the filter and band-limited, and then guided to the output terminal 22 via the amplifier 20.

When a synchronizing signal is digitally added, the configuration is as follows. The digital video signal Sa input to the terminal 12 is supplied to a 10-bit input latch circuit 40. The latch circuit 40 is used, as described later, in order to provide a range in which a synchronization signal can be digitally added.
Is converted into a 9-bit digital video signal S by the latch circuit 40.
This is for bit conversion to b. In this case, the digital video signal Sa is shifted down by one bit to the bits (D1 to D8) excluding the most significant bit and the least significant bit, and the most significant bit and the least significant bit are always at a high level. You. The upper 9 bits (Q0 to Q8) of the 10-bit output are used as the bit-shifted digital video signal Sb (FIG. 2B), and the bit-shifted digital video signal Sb is input to the D / A converter 16.

When the input / output relationship of the latch circuit 40 is as shown in FIG. 1, the peak white level 234 (EB) H in 8 bits is converted into 10 bits of 983 (3D7) H, and the black level is changed. 16 (10) H is 545 (22
1) Converted to H As a result, the dynamic range of the converted digital video signal Sb is 439 (1B7).
H. Then, of the 10-bit data, the latch
Use upper 9-bit data from circuit 40 as data
I do. Therefore, as shown in FIG.
983 (3D7) H is a 9-bit data of 490 (1EA) H.
And the black level 545 (221) H is 2
It is output as 72 (110) H 9-bit data.
The dynamic range with 9-bit output is (490-27)
2) = 218 (DA) H.

On the other hand, the level ratio between the video signal and the sync signal added thereto is 7: 3 (because the video signal portion from the black level to the peak white level is 700 mV and the sync signal portion is -300 mV). ), The range from the black level to the sync chip level of the synchronization signal may be 3/7 (983-545) = 188. The sync tip level is 545-188 = 357 (165) H. This is enough bits when converted into 9-bit data. Here, the 10-bit data 357
The upper 9 bits of (165) H become 179 (B3) H.
You.

In consideration of the bit consistency with the 9-bit digital video signal Sb, the digital synchronizing signal Sc is changed from 545 (221) H to 357.
(165) If 8-bit data up to H is used,
The digital synchronization signal Sc can be digitally combined with the digital video signal Sb. Therefore, in this example, the data storage means (RO) for the digital synchronization signal Sc (FIG. 2C) is used.
M etc.) 46 are provided. The digital sync signal of 8 bits read from the data storage unit 46 is supplied in a state of being shifted one bit down to a 10-bit latch circuit 48, where put the latch circuit 40
Then, the same bit conversion processing is performed. The digital synchronization signal Sc converted into 9 bits is supplied to the D / A converter 16.

In order to realize such a conversion operation, an address signal generator 42 for the data storage means 46 is provided, and a synchronization signal based on a horizontal synchronization pulse or a frame pulse supplied through an input terminal 44 is provided here. The signal read timing is determined. Then, at this read timing, the data for the synchronization signal is read.

Reference numeral 50 denotes a timing signal generator, which generates control pulses Pa to Pd as shown in FIGS. 2D to 2G and controls the above-described latch circuits 14, 40, 48 and the like as appropriate. A control pulse (not shown) for synchronizing is supplied to the terminal 52, and a synchronizing signal is added or deleted according to the control pulse.

The control pulse Pd is supplied to a switching means 54 provided at a stage subsequent to the D / A converter 16, and an analog signal via a volume 56 which is a level attenuating means and an analog signal which is not level-controlled are appropriately converted. Selected. The switching means 54 is provided for the following reason.

That is, 10-bit data having higher order 8-bit data is used.
When the digital video signal is converted into bit data, the peak white level 235 becomes 943 (3AF) H and the black level 1 becomes
6 (10) H becomes 67 (43) H, and the dynamic range at that time is 877 (36D) H. Therefore, the value obtained by lowering the dynamic range 877 by 6 dB becomes the dynamic range 439 (1B7) H in the video signal portion when the synchronization signal is added. From the above, the video signal without the synchronizing signal is output through the level attenuating means 56.

Conversely, an amplifier may be connected to the switching terminal Y to increase the output level by 6 dB and output the result. In that case, the level attenuating means 56 provided on the switching terminal X side becomes unnecessary.

When the control signal supplied to the terminal 52 is used to control the synchronous signal deletion mode, the control pulse Pa goes low and the control pulses Pb, Pc, Pd go high, and only the latch circuit 14 is active. Since the other latch circuits 40 and 48 are inhibited, a video signal without a synchronizing signal is output from the D / A converter 16 and therefore from the terminal 22 at this time.

On the other hand, when the mode is controlled to the synchronous signal addition mode, the operation is reversed, and the latch circuit 14 is always in the inhibit state, and the latch circuits 40 and 48 are controlled as shown in FIG.
The active mode is repeated at the timing shown in FIG. Therefore, in the section P, only the latch circuit 40 becomes active, and a 9-bit digital video signal Sb is output.
This is D / A converted. In the section Q, only the latch circuit 48 becomes active and only the 9-bit digital synchronizing signal Sc is D / A converted. Therefore, the analog video signal Sd to which the synchronizing signal is added as shown in FIG. Is obtained.

In the case of a synchronization signal having three values as shown in FIG. 3C, the minus peak level is 357 (165) H, the zero level (corresponding to the black level) is 545 (221) H, and the plus level is plus. The peak level is 733 (2
DD) Synchronous data should be constructed so as to be H (if the data in the storage means 46 is set as such). As a result, an analog video signal Sd as shown in FIG. 3H can be easily obtained by adding the digital video signal to the ternary digital synchronizing signal as in the case of the binary signal.

The present invention is not limited to the above-described component digital VTR, but can be applied to a synchronous addition system of another digital VTR.

[0030]

As described above, the synchronization signal adding circuit according to the present invention converts the reproduced digital video signal and the digital synchronization signal into bits, and then adds the digital synchronization signal to the reproduced digital video signal. It was made.

According to this, it is possible to easily add the digital synchronization signal to the digital video signal without changing the digital signal. Since it can be added in the state of a digital synchronization signal, its rise and fall do not deteriorate even when it is converted into an analog signal. Even in that case, ringing does not occur.

Further, since the video signal and the synchronizing signal can be digitally synthesized, there is no occurrence of an offset due to temperature characteristics and a level change in a signal synthesizing portion.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an example of a synchronization signal adding circuit according to the present invention.

FIG. 2 is an explanatory diagram of addition of a synchronization signal.

FIG. 3 is an explanatory diagram of addition of a synchronization signal.

FIG. 4 is a system diagram showing an example of a conventional synchronization signal adding circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Synchronous signal addition circuit 14, 40, 48 Latch circuit 16 A / D converter 42 Address signal generator 50 Timing signal generator 46 Synchronous signal data storage means 54 Switching means 56 Level attenuation means

Claims (1)

(57) [Claims] 1. A synchronizing signal adding circuit for adding a synchronizing signal to a reproduced digital video signal, comprising: a pair of a predetermined number of bits larger than a quantization bit number N (N is an integer) of the digital video signal. A latch circuit, the digital video signal is supplied to the one latch circuit in a bit-shifted state, and a bit-converted M-bit (M> N) digital video signal is output therefrom; The N-bit digital synchronizing signal is bit-converted into the M-bit digital synchronizing signal in the other latch circuit, and the digital synchronizing signal after the bit conversion is matched with the digital video signal in the number of bits. A synchronization signal adding circuit, which is added to a signal.