JP3167541B2 - Sampling gate circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for inputting an analog signal to a digital circuit. In particular, the present invention relates to a sampling gate circuit that holds an instantaneous value of a signal under measurement in a capacitor and measures the value. The present invention is particularly suitable for use as an input circuit of a wideband sampling oscilloscope.

[0002]

2. Description of the Related Art A / D is performed by sampling an analog signal.
Conventionally, a sampling gate circuit that samples an instantaneous value of a signal under measurement has been used as an input circuit for performing the conversion. The sampling gate circuit basically includes a gate circuit for interrupting a signal under test, a memory capacitor for holding a voltage input when the gate circuit is connected, and a terminal between the terminals of the memory capacitor. And a measurement system for measuring the voltage. A circuit including a gate circuit and a memory capacitor is called a sample / hold circuit or an S / H circuit.

As a measurement system, a buffer amplifier having a high input impedance for amplifying a signal stored in a memory capacitor is used. However, when a wide band S / H circuit of 10 GHz or more is configured, the memory capacitor is 1p.
In many cases, the input capacitance of the buffer amplifier acts as if it were a second memory capacitor, causing the S / H circuit band to degrade or ramp up. To avoid this situation, a configuration is adopted in which a high resistance is inserted between the memory capacitor and the buffer amplifier to prevent the sampled high-frequency signal from flowing into the input capacitance of the buffer amplifier.

In such a sampling gate circuit, since a parasitic capacitance exists in the gate circuit, distortion occurs in a measured waveform. Techniques for correcting such waveform distortion are disclosed in JP-A-4-48270 and JP-A-4-1743.
No. 67 or JP-A-5-90924. The configurations disclosed as examples in these publications are shown in FIGS. 10 to 12 as first, second and third conventional examples, respectively.

In these conventional examples, the signal source to be measured is equivalently represented by the signal voltage source to be measured E0 and the internal impedance R0, and the output is supplied to the first sampling gate (gate circuit) 101 as the signal to be measured. Applied. The first sampling gate 101 is equivalently composed of a switch S31, a resistor R31 representing an on-resistance when the switch S31 is turned on, and a capacitor C31 representing a capacitance between terminals of a gate element (generally, a diode). expressed. A memory capacitor C32 is connected between the output of the first sampling gate 101 and the ground,
Amplifying means, that is, a buffer amplifier 102 in the first and second conventional examples and a differential amplifier 103 in the third conventional example are connected via a buffer resistor R33. Between the input of the buffer amplifier 102 or the differential amplifier 103 and the ground, a resistor R34 and a capacitor C3 which is an input capacitance are provided.
4 is connected. The output of the buffer amplifier 102 or the differential amplifier 103 is shaped by a shaping circuit 104 (omitted in FIG. 12).
Sampled again at 05.

In the first conventional example shown in FIG. 10, in order to correct the waveform distortion caused by the capacitor C31, an input signal of the first sampling gate 101 includes a resistor R36 and a parallel circuit of a resistor R35 and a capacitor C35. Through,
Applied to the input of the buffer amplifier 102. Resistance R3
5 and the capacitor C35 are connected to the resistor R34 and the capacitor C3.
4 and has a time constant substantially equal to the product of C3 and the capacitor C31 at the intersection of capacitors C35 and C34.
It is set so as to obtain the same value as the attenuation ratio with respect to the input signal by the capacitor C32. An attenuator 106 for attenuating an input signal with the same attenuation ratio is connected to the resistor R36, and the output of the attenuator 106 is added to the output of the buffer amplifier 102 by the differential amplifier 107 in reverse phase.

In the second conventional example shown in FIG. 11, the input signal of the first sampling gate 101 is input to the equivalent network 110, and when the first sampling gate 101 is not performing the sampling operation, the capacitor C34 A signal waveform substantially equal to the waveform of the signal obtained between the terminals is obtained. The switch S32 connected in parallel to the capacitor C34 and the switch S33 connected to the output of the equivalent network 110 enable the capacitor C34 when the first sampling gate 101 performs a sampling operation.
And the output of the equivalent network 110 is passed through, and the second sampling gate 105 shuts down after completing the sampling operation. Then, a difference signal between the output of the buffer amplifier 102 and the output of the equivalent network 110 is obtained by the differential amplifier 107.

The equivalent network 110 is composed of an amplifier (or attenuator) 111, capacitors C41 and C44, and resistors R43 and R44. The signal under test passes through the amplifier 111 and a capacitor C41 connected to its output side.
The voltage is applied to the parallel connection of the resistor R44 and the capacitor C44 via the direct connection of the resistor R43.

This conventional example also has a command terminal 11 for inputting a sampling command for instructing sampling.
2. Upon receiving this sampling command, a sampling pulse generator 113 which generates a sampling pulse for turning on the switch S31 of the first sampling gate 101 for a short time, and upon receiving the sampling command, a switch S32 for a certain period. A one-shot multivibrator 114 for turning off S33, a delay circuit 115 for determining a sampling time difference between the first sampling gate 101 and the second sampling gate 105,
And a sampling pulse generator 116 for the second sampling gate 105.

In the conventional example shown in FIG. 12, an equivalent sampling network 120 is provided in addition to the equivalent network 110 in the conventional example shown in FIG. By obtaining the difference signal, a reproduced waveform faithful to the source signal waveform is obtained. The output of each of equivalent network 110 and equivalent sampling network 120 is subtracted by differential amplifier 103 from the signal stored on capacitor 34.

The equivalent sampling network 120 is provided with a capacitor C52 for storing electric charge proportional to the amount of electric charge when the electric charge is stored in the capacitor C32 instantaneously. An attenuator 121 for applying an input signal to the capacitor C52 and a resistor R
51, R52 and a capacitor C51, a network connected to the capacitor C52, and a switch S51 for disconnecting the first sampling gate 101 after the operation of the first sampling gate 101. At a certain time, a resistor R53 is provided with a time constant equal to a time constant of a circuit including the capacitor C32, the resistor R33, the capacitor C34, and the resistor R34 to the capacitor C52 to take out the electric charge. The electric charge taken out through the resistor R53 is accumulated And a reset resistor R54 for discharging and resetting the capacitor C53.

A switch S52 is connected to the output of the equivalent sampling network 120, and a capacitor C53
Is supplied to the differential amplifier 103 when the switch S51 is disconnected, and the terminal of the capacitor C53 is grounded when the switch S51 is connected.

[0013]

However, the above three prior arts have problems in the following points.

First, a first conventional example (JP-A-4-4827)
No. 0) requires a high-speed step-like signal rising at a time constant of R0 × C31 × C32 / (C31 + C32) at the input terminal of the buffer amplifier 102. However, since this signal is applied to the resistor R34 and the capacitor C34 through the resistor R36 and the parallel circuit of the resistor R35 and the capacitor C35, the rising time constant is (R0 + R36) × C35 × C34 / (C35 + C3
4). In general, C31 (0.1p
F degree) ≦ C32 ≒ C34 (0.5-1 pF), R0
(Approximately 25Ω) ≪R36 (approximately several hundred Ω), the time constant of the resistor R36, the capacitor C34, and the capacitor C35 is 100 to 200 ps, and the rise time is approximately 200 ps to 400 ps. The / H circuit cannot utilize the first conventional example.

In the second conventional example (Japanese Patent Laid-Open No. 4-174667), the operation of removing the waveform distortion is incomplete. This will be described in comparison in the description of the embodiment of the present invention.

The third conventional example (Japanese Patent Laid-Open No. 5-90924) can correct the waveform distortion in principle, but has the following problems in the circuit configuration.

First, since two systems of correction circuits are connected to the terminal to which the signal to be measured is applied, the influence on the signal to be measured is large and causes a measurement error.

Second, the configuration of the correction circuit is different from the original S / H circuit. In the third conventional example, an equivalent sampling network 120 for removing waveform distortion based on a sampling operation includes an attenuator 121, a resistor R51,
It outputs a combined response of a real-time response by R52 and capacitor C51 and an equivalent-time response by switch S51, capacitor 52, resistors 53 and 54, and capacitors 52 and 53. This response is the difference between the original S / H circuit response minus the step response of the S / H circuit and the response of the blow-by correction circuit (equivalent network 110). In order to obtain the response of this difference, a circuit configuration different from the original S / H circuit must be adopted, and a highly accurate correction signal is obtained by a combination of different impedances, different time constants, and a finite equivalent band. It is difficult. In addition, the number of adjustment points inevitably increases. These different circuit configurations and the large number of adjustment points are not suitable for IC technology, which is a basic technology for realizing an ultra-high-speed S / H circuit.

Third, since the element constant and the circuit configuration are different between the original S / H circuit and the correction circuit, the circuit response to temperature changes is different, and the correction function does not function sufficiently in a low temperature or high temperature environment. Causes distortion.

Fourth, since the value of the resistor 34 for discharging the electric charge stored in the memory capacitor C32 is large, the measurement repetition period becomes long. memory·
Since the charge stored in the capacitor C32 must be discharged to a sufficiently negligible level during one measurement period, the discharging resistor R34 needs to be set to a somewhat large value. However, in order to prevent interference between samples, this charge must be sufficiently discharged before the next measurement. Therefore, the measurement repetition period is several times to several tens times or more longer than the measurement time determined by the memory capacitor C32 and the buffer resistor R33.

An object of the present invention is to solve such a problem and to provide a sampling gate circuit having a high correction effect without providing a special circuit for a distortion correction circuit. A further object of the present invention is to provide a sampling gate circuit having a short measurement repetition period as a technique necessary for operating such a sampling gate circuit.

[0022]

According to the present invention, there is provided a sampling system comprising:
The gate circuit includes a memory capacitor that holds the input signal voltage to be measured, a gate circuit that interrupts the input of the signal to be measured to the memory capacitor, and a measuring unit that measures the voltage held in the memory capacitor. A sampling gate circuit comprising: a switch connected in parallel to the memory capacitor; and means for discharging the charge stored in the memory capacitor by turning on the switch. .

Although separate elements can be used for the switch and the memory capacitor, the switch is a switch represented by an equivalent circuit in the voltage control switch, and the memory capacitor is realized by the capacitance between the terminals of the voltage control switch. You can also.

First control means for turning on and off the switch at a predetermined time position of the signal to be repeatedly input, and a gate circuit connected to input the signal to be measured to the memory capacitor and measure by the measuring means. And a correction value measurement mode in which the signal to be measured leaks to the memory capacitor while the gate circuit is in the disconnected state and the measurement is performed by the measurement means. The second control means for once executing the signal measurement mode and once for executing the correction value measurement mode near the time position, and the measuring means is operated after a predetermined time has elapsed since the switch was opened. And third control means for causing the measurement means to obtain a measurement value obtained in the correction value measurement mode from the measurement value obtained in the signal measurement mode. It may include means for correcting the waveform distortion by subtracting.

Separately from this, two circuits each comprising a gate circuit and a switch are provided, and both switches of the two circuits are intermittently switched at predetermined time positions of a signal to be measured repeatedly inputted. One control means, a second control means for controlling one of the gate circuits to be in a connected state near a time position when the switch is opened, and a measurement after a predetermined time has elapsed since the switch was opened. And a third control means for operating the means, and the measuring means may include means for subtracting the outputs of the two circuits to correct the waveform distortion.

[0026]

By providing a switch in parallel with the memory capacitor, the correction circuit can be realized with the exact same circuit configuration as the original S / H circuit, so that a high-precision distortion correction circuit that does not require various adjustments can be realized. . This is a very useful characteristic when the S / H circuit is made ultra-wideband by a monolithic IC. Further, by changing the operation mode of one sampling gate circuit in two ways, the S / H circuit and the correction circuit can be realized in a time division manner, and high correction accuracy can be realized without requiring a special circuit for correction. . Further, the electric charge stored in the memory capacitor can be rapidly discharged by the conduction of the switch, and the measurement repetition cycle can be shortened.

A parallel connection circuit of a switch and a memory capacitor is described in the second conventional example described above (JP-A-4-1743).
No. 67). However, the switch is a memory capacitor (C
Rather than being connected in parallel with 32), the capacitor is connected in parallel with the second memory capacitor (C34) connected to the capacitor via a buffer resistor, that is, the input capacitance of the measurement system. In this case, the effect described in Japanese Patent Application Laid-Open No. 4-174367 cannot be obtained, and distortion of a time constant substantially determined by the capacitance between the terminals of the switches constituting the sampling gate and the buffer resistance occurs. The time constant is longer than the sampling time, and causes a decrease in bandwidth. As described above, the second conventional example is different from the present invention in both the configuration and the operation and effect.

[0028]

FIG. 1 is a block diagram showing a sampling gate circuit according to a first embodiment of the present invention.

This circuit includes a memory capacitor C2 for holding an input signal voltage to be measured, a gate circuit 10 for interrupting the input of a signal to be measured to the memory capacitor C2, and a memory capacitor C2. A buffer resistor R3 as a measuring means for measuring the applied voltage, an A / D converter 30, a digital memory 40, and a computing unit 50.

The signal source under test is equivalently represented by the signal source under test E0 and the internal impedance R0, which are connected in series between the input terminal of the sampling gate circuit and ground. The gate circuit 10 is constituted by a voltage control switch, and its equivalent circuit is represented as a circuit in which a parasitic resistance R1 is connected in series to a parallel circuit of a switch S1 and a parasitic capacitance C1. A circuit including the memory capacitor C2 is connected between the output terminal of the gate circuit 10 and the ground, and an S / H circuit is configured. The output of the S / H circuit is input to the A / D converter 30 via the buffer resistor R3. A parasitic input capacitance C3 exists between the input terminal of the A / D converter 30 and the ground. The A / D converter 30 is connected to a digital memory 40 via a bus line for digital signals, and the digital memory 40 is also connected to a computing unit 50 via a bus line for digital signals.

The feature of this embodiment is that the switch S2 connected in parallel to the memory capacitor C2
And a pulse generation circuit 60 as means for discharging the electric charge stored in the memory capacitor C2 by turning on the switch S2. Also,
In this embodiment, the switch S2 is connected to the voltage control switch 20.
The memory capacitor C2 is realized by the capacitance between the terminals of the voltage control switch 20. In this case, the equivalent circuit of the voltage control switch 20 is represented as a circuit in which a parasitic resistance R2 is connected in series to a parallel circuit of the switch S2 and the inter-terminal capacitance, and the inter-terminal capacitance operates as the memory capacitor C2. A separate capacitor can be connected in parallel with the voltage control switch 20 to adjust the capacity of the memory capacitor.

This embodiment further includes a pulse generation circuit 60 as first control means for turning on and off the voltage control switch 20 (switch S2) at a predetermined time position of the signal to be measured which is repeatedly input, and a gate circuit. 10 (switch S1) becomes connected and the memory capacitor C2
A signal measurement mode in which a signal to be measured is input to the memory and a measurement is performed, that is, a mode in which the gate circuit 10 and the memory capacitor C2 operate as an S / H circuit, and a mode in which the signal to be measured is Controlling the switching to the correction value measurement mode in which the measurement is performed in a state where the signal leaks to the capacitor C2, and causing the signal measurement mode to be executed once near the above-described predetermined time position;
Further, a third control means for once executing the correction value measurement mode includes an impulse generation circuit 70 and a counter 80, and operates the measurement means after a predetermined time has elapsed since the switch S2 was opened. A delay circuit 90 is provided as control means, and the arithmetic unit 50 includes program means for subtracting a measurement value obtained in the correction value measurement mode from a measurement value obtained in the signal measurement mode to correct waveform distortion.

The pulse generation circuit 60 repeatedly generates an edge twice at the same point of the signal waveform to be measured.
2 is controlled. The impulse generation circuit 70 generates a pulse on one of the down edge and the up edge of the output of the pulse generation circuit 60. The counter 80 generates one pulse in response to two pulse inputs from the impulse generation circuit 70, and operates the gate circuit 10 (switch S1) once for every two intermittent operations of the voltage control switch 20 (switch S2). Thus, the connection is controlled in the vicinity of the above-described time position. The delay circuit 90 includes an impulse generation circuit 70
And outputs a trigger signal to the A / D converter 30.

FIG. 2 shows a configuration example of the voltage control switch 20. This example is a circuit using a diode bridge,
(A) shows an actual circuit, and (b) shows an equivalent circuit. In these two circuits, terminals A to D correspond to each other.
Such a circuit configuration is conventionally used for a gate circuit, and a similar circuit can be used for the gate circuit 10 of the present embodiment.

Next, the operation of this embodiment will be described with reference to FIGS. 3 shows the pulse generation timing of the pulse generation circuit 60 for the signal under measurement, FIG. 4 shows the operation of each unit, and FIG. 5 shows the equivalent circuit in each operation state (phase). In FIG. 4, (a) shows a pulse generation circuit 6
0, the output voltage of the impulse generation circuit 70, the output voltage of the counter 80, the output voltage of the delay circuit 90, the change in the operating state (e) 8) and (f) show the rising timing when a step-like voltage E is assumed as the signal to be measured.
3 and 4, the horizontal axis represents time.

Here, an example will be described in which the operation is performed first in the signal measurement mode and then in the correction value measurement mode. The switches S1 and S2 are turned on when the voltage is positive. Further, the pulse generation circuit 60 generates a pulse having an edge at the same point of the repetitive waveform generated by the signal-under-measurement voltage source E0 twice, and then generates pulses at sequentially different points of the repetitive waveform. Further, it is assumed that the impulse generation circuit 70 generates a positive pulse at the down edge of the output of the pulse generation circuit 60.

As shown in FIG. 4, both the signal measurement mode and the correction value measurement mode are started when the output voltage of the pulse generation circuit 60 changes from a high level to a low level (strictly in the vicinity thereof). The time when the signal measurement mode is started is t = t ₀ , the time difference (sampling cycle) between the signal measurement mode start time and the correction value measurement mode start time for a certain measurement point is T ₀ , and the impulse generation circuit 70 and the counter 80 determine the time. The delay time is T ₁ , the time width of the output pulse of the counter 80 is T _2, and the time obtained by subtracting T ₁ and T ₂ from the delay time by the impulse generation circuit 70 and the delay circuit 90 is T ₃ . The time difference T ₀ is set to an integral multiple of the period of the signal under measurement. T ₁ is the time difference between the time at which time the switch S1, switch S2 starts operation starts the operation, T ₂ is the sampling time, T ₃ is a time for starting the A / D conversion from the sampling is completed is there. At T _3, the gate circuit 10 operates and the signal voltage source E under test is
0 to the memory capacitor C2 of the voltage control switch 20
Is set to the time from when the electric charge flows into the circuit until the entire circuit enters a steady state. During the high-level generation period of the pulse generation circuit 60, the time from when the switch S2 of the voltage control switch 20 is closed to when the entire circuit enters the steady state is set. Set to more than hours.

The equivalent circuit in the signal measurement mode or the correction value measurement mode includes the pulse generation circuit 60 and the counter 8
0 and the output state of the delay circuit 90, Phase 1: t <t ₀ Phase 2: t ₀ ≦ t <t ₀ + T ₁ Phase 3: t ₀ + T ₁ ≦ t <t ₀ + T ₁ + T ₂ Phase 4: t ₀ + T ₁ + T ₂ ≦ t <t ₀ + T ₁ + T ₂
+ T ₃ Phase 5: t ₀ + T ₁ + T ₂ + T ₃ ≦ t Phase 6: t <t ₀ + T ₀ Phase 7: t ₀ + T ₀ ≦ t <t ₀ + T ₀ + T ₁ + T ₂
+ T ₃ Phase 8: Classified as t ₀ + T ₀ + T ₁ + T ₂ + T ₃ ≦ t. The equivalent circuits for phases 6, 7, and 8 are shown in FIG.
As shown in FIG.

Here, at time t = 0, the step-like voltage E
Consider the response when you enter The time during which this voltage E is maintained is sufficiently longer than the time required for measurement in each mode,
Thereafter, the voltage temporarily returns to zero, and becomes the voltage E again at t = T ₀ . Note that an arbitrary waveform can be represented by a convolution of a step signal, so that the following description based on this assumption is also valid for an arbitrary waveform.

At this time, as shown in FIG. 4 (f), there are different cases depending on which of the phases 1 to 5 the time t = 0 when the voltage E is input. A for these 5 cases
The output of the / D converter 30 will be described with reference to FIG. Immediately after power is supplied to the circuit, the parasitic capacitance C
1. The initial charge remains in the memory capacitor C2 and the parasitic input capacitance C3, but this charge is discharged when sampling is repeated, so that the initial charge is set to zero. Assuming that the resistance value of the buffer resistor R3 is sufficiently large, the delay time T
₁ and charge passing through the buffer resistor R3 during the sampling time T ₂ are sufficiently small as compared with the charge stored in the memory capacitor C2, can be ignored. In the following description, the internal impedance R0, the parasitic resistance R1 of the gate circuit 10, and the voltage control switch 2
0, R ₀ , R ₁ , R
_2, and the values of the parasitic capacitance and the inter-terminal capacitance of the gate circuit 10 and the voltage control switch 20 are C ₁ , C ₂
And further defined as R≡R ₀ + R ₁ + R ₂ C≡C ₁ C ₂ / (C ₁ + C ₂ ).

(1) When the voltage rises in phase 5, that is, t ₀ + T ₁ + T ₂ + T ₃ ≦ t = 0 The input is zero from time t = t ₀ to t = t ₀ + T ₁ + T ₂ + T _3. Therefore, the value after A / D conversion is naturally zero. In the case of the correction value measurement mode, since the voltage rises in phase 8, the operation starts at time t = t ₀ + T ₀ to t
= T ₀ + T ₀ + T ₁ + T ₂ + T _{3 The} input is zero, and the value after A / D conversion is zero. Therefore, [measured value in signal measurement mode]-[measured value in correction value measurement mode] = 0.

(2) When the voltage rises in phase 4, that is, t ₀ + T ₁ + T ₂ ≦ t = 0 <t ₀ + T ₁ +
The T ₂ + T ₃ A / D converter 30 calculates the time t = t ₀ + T ₁ + T ₂ + T ₃
At this time, the voltage value indicated by both ends of the parasitic input capacitance C3 is digitally converted and output. In the correction value measurement mode,
During the phase 7, the voltage E is input and the A / D converter 3
0 outputs a voltage value indicated by the two ends of the parasitic input capacitance C3 at time _{t = t 0 + T 0 +} T 1 + T 2 + T 3. In each case, the initial value is zero, and the time from when the voltage E is input to when the A / D conversion is performed is equal, so that the same value is output. Therefore, [measured value in signal measurement mode]-[measured value in correction value measurement mode] = 0.

(3) When the voltage rises in phase 3, ie, when t ₀ + T ₁ ≤t = 0 <t ₀ + T ₁ + T ₂ t = t ₀ + T ₁ + T ₂ , the memory capacitor C2
Is as follows.

[0044]

(Equation 1) At time t = t ₀ + T ₁ + T ₂ + T ₃ , the steady state is reached, and the voltage of the parasitic input capacitance C3 (= A / D conversion output) is as follows.

[0045]

(Equation 2) On the other hand, in the correction value measurement mode, the voltage of the parasitic input capacitance C3 is as follows since the initial charge is in a steady state with zero.

[0046]

(Equation 3) Therefore, the difference between the measured values in the signal measurement mode and the correction value measurement mode is as follows.

[0047]

(Equation 4)

(4) When the voltage rises in phase 2, that is, when t ₀ ≦ t = 0 <t ₀ + T ₁ t = t ₀ + T ₁ , the voltage of the memory capacitor C2 is as follows.

[0049]

(Equation 5) However, in the T ₂ of the gate circuit 10 is conducting time, the charge stored in the parasitic capacitance C1 is discharged. As a result,
T = t ₀ + T ₁ + T _{2 at which the} gate circuit 10 is turned off again
At this time, the voltage of the memory capacitor C2 is as follows.

[0050]

(Equation 6) _{t = t 0 + T 1 +} T 2 + T becomes ₃ when the circuit reaches a steady state, the voltage of the parasitic input capacitance C3 is expressed by the following equation.

[0051]

(Equation 7) In the correction value measurement mode, it is the same as in the case of (3), and the voltage of the parasitic input capacitance C3 is as follows.

[0052]

(Equation 8) Therefore, the difference between the measured values in the signal measurement mode and the correction value measurement mode is as follows.

[0053]

(Equation 9)

(5) When the voltage rises in phase 1, that is, t = 0 <t _{0 In} this case, in the state of phase 1 (FIG. 5A) until t = t ₀ when the signal measurement mode is started. Voltage E is applied. As a result, the voltage at both ends of the parasitic capacitance C1 when t = t ₀ is expressed by the following equation.

[0055]

(Equation 10) At time t = t ₀ , the state of the phase 2 is completed, and when this phase ends t = t ₀ + T ₁ , the memory capacitor C2
Is as follows.

[0056]

[Equation 11] Further, from t = t ₀ + T ₁ , the state of phase 3 is established,
The voltage across the memory capacitor C2 at the end of this phase at t = t ₀ + T ₁ + T ₂ is as follows.

[0057]

(Equation 12) In the period T _2, (4) in the case as well as a parasitic capacitance C1
Is discharged.

At t = t ₀ + T ₁ + T ₂ , phase 4 is reached, and at t = t ₀ + T ₁ + T ₂ + T ₃ the circuit reaches a steady state. The voltage at both ends of the parasitic input capacitance C3 at this time is expressed by the following equation.

[0059]

(Equation 13) On the other hand, the correction value measurement mode is started from t = t ₀ + T ₀ , but before T ₀ ≦ t <t ₀ + T _0, the phase 5 is started.
In this state, the voltage E is applied. Therefore, t = t ₀
The voltage across the parasitic capacitance C1 at + T ₀ is expressed by the following equation.

[0060]

[Equation 14] At t = t ₀ + T ₀ , the correction value measurement mode is entered, and the phase 6
T = t ₀ + T ₀ +
The voltage across the parasitic input capacitance C3 at the time of T ₁ + T ₂ + T ₃ is as follows.

[0061]

(Equation 15) Therefore, the difference between the measured values in the signal measurement mode and the correction value measurement mode is as follows.

[0062]

(Equation 16) As described above, with reference to FIG. 4 and FIG. 5, the operation of the embodiment shown in FIG. 1 was analyzed separately for the cases (1) to (5). To summarize the results, in the cases (1) and (2), the difference is zero, and the input signal is accurately reproduced. In the cases of (3) and (4), the rising of the step is dull and the frequency band is narrow. However, (3)
Is a phenomenon that occurs because the pulse time width (T ₂ ) at the time of sampling has a certain finite value, and is not a distortion to be improved in the present invention. Further, (4) is a period from entering the signal measurement mode until the sampling pulse is input to the gate circuit 10, T ₁ may be set to a very small value. At this time, since the last term on the right side of Equation 9 is almost zero, only the pulse width T ₂ narrows the equivalent band. (5) In the case of, as t increases, converges in a relatively short time constant of the RC ₁ to the following values.

[0063]

[Equation 17] Here, K is a correction coefficient represented by the following equation.

[0064]

(Equation 18) That is, the output value of the A / D converter 30 when operating in the signal measurement mode and the A / D when operating in the correction value measurement mode.
By dividing the difference from the output value of the / D converter 30 by the correction coefficient K, the amplitude value of the input signal can be obtained.

For comparison, the same analysis was performed on the second conventional example shown in FIG. Here, to correspond to the above-described analysis, the respective capacities of the capacitor C31, the memory capacitor C32, and the capacitor C34 are set to C
_1, and C ₂ and C _3, the sum of the resistance values of the internal impedance R0 with resistance R31 of the measured signal source R, the resistance value of the buffer resistor R33 and the R _3. As a result, in each case of (1) to (4), the same output as that of the embodiment shown in FIG. 1 was obtained, but in the case of (5), the following equation was obtained.

[0066]

[Equation 19] Of e is the third term on the right side of the equation _{-t 0 / (C 1 + C} 2) R
Cube _of claim are included, a large time constant (C ₁ + C ₂₎
Waveform R ₃ indicates that rises. This is disclosed in Japanese Unexamined Patent Publication No. Hei.
No. 7 is different from the description.

Using the codes shown in FIG.
To describe the description of Japanese Patent No. 743673, the amplitude of the distortion correction signal (the inverted input of the differential amplifier 107) is determined by the sampled signal waveform (differential amplifier) in the phase in which the gate switch operates after the step input is applied. 10
7 (non-inverting input of 7) times C ₁ / (C ₁ + C ₂ ) times. However, C ₁ and C ₂ are each a capacitor C3
1. The capacity of the memory capacitor C32. But,
The amplitude of the signal waveform does not depend on the time difference between the rising time of the input step and the time when the sampling operation is performed, but the amplitude of the distortion correction signal decreases as the time difference increases. The former is obvious because the switch S31 operates in the track hold mode, and the latter is the capacitor C4.
This is because 1 is charged by the step input. As a result, in the second conventional example, the relationship of C ₁ / (C ₁ + C ₂ ) times cannot be maintained, and the charge time constant C41 × R
43 = k (C ₁ + C ₂ ) × R ₃ / k = (C ₁ + C ₂ ) ×
Distortion of R ₃ occurs. C41 is a capacitor C4
1 volume, R _3, R43 is a buffer resistor, respectively R3
3, represents the resistance value of the resistor R43.

FIG. 6 shows a step response calculated using element parameters for realizing a band of about several tens of GHz.
Indicates the transition portion in an enlarged manner. The solid line is based on the embodiment of the present invention, and the broken line is based on the second conventional example described above. In this example, R ₀ = 25Ω, R ₁ = 4Ω, R ₂
= 4Ω, R ₃ = 1kΩ, C ₁ = 30fF, C ₂ = 55f
F, C ₃ = ₁ pF, T ₁ = 1 ps, T ₂ = 4.4 ps,
T ₃ = 5 ns. 6 and 7, the horizontal axis represents time, and the vertical axis represents normalized output (a value obtained by dividing the output value by K).
It is.

In this example, R ₀ + R ₁ + R ₂ = 25 + 4
Since + 4 = 33Ω and R ₃ = 1 kΩ, the time constant after t = 0 decreases to 33/1000 = 0.933 times. This is a value smaller than the sampling period T _2, a level that is not recognized as waveform distortion. Thus, in the present invention, the waveform after time t> 0 is greatly improved.

The sampled memory capacitor C
The time constant at which the signal stored in 2 is transmitted to the measuring means is (C ₁
+ C ₂ ) × R ₃ = (55f + 30f) × 1K ≒ 0.1n
s, the time constant for discharging the signal stored in the parasitic input capacitor C3 is C ₃ × R ₃ = 1p × 1k = 1n.
The sampling operation can be performed every s or less.

The third conventional example will be described for comparison. In the configuration, a resistor R is used to prevent the signal-to-noise ratio from deteriorating.
34 has to be set to a value ten times or more the buffer resistance R33, and the memory capacitor C32 and the capacitor C34 have to be set.
Has a discharge constant exceeding 10 ns. As a result, in the third conventional example, the sampling period becomes 100 ns or more, and it is difficult to realize high-speed sampling.

FIG. 8 is a circuit diagram showing the sampling and sampling of the second embodiment of the present invention.
FIG. 3 is a block diagram showing a gate circuit. In this embodiment, a voltage control switch 20 'is further provided between the input of the A / D converter 30 and the ground, and the voltage control switch 20'
The operation at the same timing as in the first embodiment is different from the first embodiment. The voltage control switch 20 'allows the signal stored in the parasitic input capacitance C3 to be rapidly discharged.
The insertion of such a voltage control switch 20 'does not affect the above analysis. The switch is connected to the output side of the buffer resistor R3 in a manner similar to the second conventional example, but its purpose and operation are clearly different.

FIG. 9 is a diagram showing the sampling and output of the third embodiment of the present invention.
FIG. 3 is a block diagram showing a gate circuit. In this embodiment, two S / H circuits are provided, one of which is operated in a signal measurement mode and the other is operated in a correction value measurement mode, and the output thereof is subtracted. Further, two input portions of the measuring means are provided corresponding to the S / H circuit. That is, one system includes a gate circuit 10-1, a voltage control switch 20-1, a buffer resistor R13, an input capacitor C13, and an A / D converter 30-1, and the other system includes a gate circuit 10-2, Voltage control switch 20-
2, buffer resistor R23, input capacitance C23 and A / D
A converter 30-2 is provided as a first control means for intermittently turning on and off the voltage control switches 20-1 and 20-2 of the two circuits at a predetermined time position of the signal to be measured which is repeatedly input. A pulse generation circuit 60 is provided, and one gate circuit 10-1 is connected to the voltage control switches 20-1 and 20-2.
An impulse generation circuit 70 is provided as a second control means for controlling the connection state in the vicinity of the time position when 0-2 opens, and the predetermined control is performed after the voltage control switches 20-1 and 20-2 are opened. A / D after time has passed
A delay circuit 90 is provided as third control means for operating the converters 30-1 and 30-2, and the arithmetic unit 50 can correct the waveform distortion by subtracting the outputs of the two circuits.
With such a configuration, an output in the signal measurement mode and an output in the correction value measurement mode can be obtained simultaneously.

Here, an example in which two A / D converters are used has been described. However, a differential amplifier is arranged before the A / D converter to reduce the number of relatively expensive A / D converters. You can also.

[0075]

As described above, in the sampling gate circuit of the present invention, by providing a switch for discharging electric charge in parallel with the memory capacitor, the capacitance between the terminals existing in the switch of the gate circuit and the sampled signal can be obtained. It is possible to reduce the time constant of the distortion generated due to both the parasitic capacitance existing in the measurement system for measuring the signal, and to rapidly discharge the sampled signal. As a result, it is possible to realize an S / H circuit having a high sample rate, a wide band, and a low distortion characteristic.

Further, since the S / H circuit can be operated as a correction circuit, only one S / H circuit is connected to the terminal to which the signal under measurement is input, and the parallel connection of the correction circuits is not required. It can be unnecessary. At this time, the influence of the S / H circuit connection on the signal under measurement is minimized, and a favorable result as a measuring instrument can be obtained.

Further, since a voltage control switch constituting a gate circuit and a memory capacitor can be easily realized by a diode bridge, it is advantageous for IC implementation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a sampling gate circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a voltage control switch.

FIG. 3 is a diagram illustrating timing of pulse generation by a pulse generation circuit.

FIG. 4 is a diagram showing a signal waveform of each part of an example circuit, a change in an operation state, and a timing example of a step signal to be measured.

FIG. 5 is a diagram showing an equivalent circuit in each operation state.

FIG. 6 is a diagram showing an example of a step response obtained by calculation.

FIG. 7 is an enlarged view showing a transition section in FIG. 6;

FIG. 8 is a block diagram showing a sampling gate circuit according to a second embodiment of the present invention.

FIG. 9 is a block diagram showing a sampling gate circuit according to a third embodiment of the present invention.

FIG. 10 is a block diagram showing a first conventional example.

FIG. 11 is a block diagram showing a third conventional example.

FIG. 12 is a block diagram showing a third conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Gate circuit 20 Voltage control switch 30 A / D converter 40 Digital memory 50 Operation unit 60 Pulse generation circuit 70 Impulse generation circuit 80 Counter 90 Delay circuit C1 Parasitic capacitance C2 Memory capacitor C3 Parasitic input capacitance R1 Parasitic resistance R2 Parasitic resistance R3 Buffer resistance S1, S2 switch

Continuation of front page (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 27/02 G01R 13/34 H03M 1/12

Claims (1)

(57) [Claims] 1. A method for holding an input signal under test voltage.
Between the memory capacitor (C2) and the input of the signal under test to this memory capacitor
A gate circuit (10) for measuring a voltage held in the memory capacitor;
Sampler provided with a fixing means (R3, 30, 40, 50)
A gate circuit connected in parallel to said memory capacitor.Front by conduction
Discharging the charge stored in the memory capacitorS
Switch (S2) and this switchRoughness of the signal under test that is repeatedly input
The first control means (6) intermittent at a predetermined time position
0), The gate circuit becomes connected and the memory capacity becomes
Input the signal to be measured to the
The signal measurement mode to be executed and the gate circuit in the disconnected state.
If the signal under test leaks to the memory capacitor and
The correction value measurement mode for executing the measurement by the measurement means
Control the switching and once the signal near the time position
Signal measurement mode, and once the correction value measurement mode
Second control means (70, 80) for executing the mode, At a predetermined time after opening the switch
Third control for operating the measuring means after a lapse of time
Means (90) With The measuring means may be a measured value obtained in the signal measuring mode.
Subtracts the measurement value obtained in the correction value measurement mode from
Including means for correcting shape distortion Sampling characterized by that
Gate circuit.