JP3166685B2 - Method for manufacturing wiring structure of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a method for manufacturing a wiring structure of a semiconductor device having a wiring for supplying a high-frequency current to the semiconductor device.

[0002]

2. Description of the Related Art In recent years, communication speed and frequency have been rapidly advancing mainly in the field of information communication. For example, 2.4 to 10 Gb / s in optical communication, inter-base communication, satellite communication, or wireless communication number GH _Z ~60GH _Z in the LAN or the like, 76GH _Z band in yet-vehicle radar, etc., commercialization or product development of devices etc. have been actively carried out. In such a device, a small-sized, low-cost, high-reliability, high-speed, high-frequency semiconductor integrated circuit is required especially for a signal input / output unit. By the way, in a miniaturized semiconductor integrated circuit, miniaturization and low resistance of a wiring for connecting a semiconductor element and transmitting a signal are also important. Particularly, in a high frequency region, a skin effect generated as the frequency increases becomes important. The problem that the current flowing through the wiring concentrates on the wiring surface and the wiring resistance increases increases.

[0003] This skin effect is caused, for example, by the lower insulating film 10 on a semiconductor substrate 101 as shown in the wiring sectional view of FIG.
In Au wirings 103 are formed on the 2, for example, width W = 10 [mu] m, when the cross-sectional structure of thickness d = 2 [mu] m, when a current of high-frequency current of 40GH _Z, the surface area, such as stippling in FIG. The current flows only in this case, and the area in which the current flows is 0.45 times as large as that of the DC current. Incidentally, the skin depth δ can be expressed as δ = (ρ / π × f × μ ₀ × μ) ^1/2 . Here, ρ: specific resistance, f: frequency, μ ₀ :
Vacuum permeability, μ: relative permeability. Therefore, taking the above-mentioned Au line as an example, ρ = 〜2.5 × 10 ⁻⁴ Ωc
m, as mu = to 1, with f = 1GH _Z δ = ~2.4μ
m, the δ = ~0.4μm at f = 40GH _Z.

In order to suppress such a skin effect,
2. Description of the Related Art Conventionally, wiring has been made of a stranded wire or a mesh wire obtained by bundling small-diameter wires. For example, in the field of semiconductor devices, as described in Japanese Patent Application Laid-Open No. 6-302640, a bonding wire is formed of a stranded wire in which fine wires are bundled. Further, as described in Japanese Patent Application Laid-Open No. 05-55383, a proposal has been made to increase the surface area by dividing a wiring on a semiconductor substrate into stripes. Therefore, in order to suppress the skin effect in the wiring formed on the semiconductor substrate, a configuration in which the wiring is formed in a stripe shape and a plurality of narrow wirings are arranged as in the latter case is effective.

An example of a conventional manufacturing method for forming a wiring structure in which a plurality of narrow wirings are arranged on a semiconductor substrate will be described. First, as shown in FIG.
01 on the surface of the underlying insulating film 202 on Ti
After forming an Au / Ti layer 203 by sputtering u: 2 μm, a photoresist film 204 is formed in a desired thin line shape as a mask for Au processing by a lithography method. Next, as shown in FIG. 5B, the Au / Ti layer 203 other than the photoresist mask is dry-etched with Ar particles using the photoresist film 204 as a mask.
Is removed by etching to form a narrow wiring 205. Thereafter, after removing the photoresist film 204, an insulating film 206 is formed on the narrow wiring 205 including the surface of the base insulating film 202, thereby forming the wiring structure shown in FIG. Is done. In this wiring structure, the wiring width W, the fine line width W1, the fine line interval W2, and the wiring thickness d are obtained.

[0006]

When the wiring is constituted by a plurality of narrow wirings in order to reduce the frequency change of the wiring resistance due to the skin effect described above, for example, as shown in FIG. Wiring width W is 10 μm and wiring thickness d is 2 μm
m is 40 when the wiring interval W2 and the number of thin lines N are changed.
The wiring change in the effective cross-sectional area of at GH _Z shown in FIG. In addition,
In this case, the width dimension W1 of the narrow wiring is inevitably determined from the respective values of W, W2, and N. Therefore, the characteristic of FIG. And W2. As described above, in order to reduce the frequency dependency by increasing the effective area without changing the wiring width W, it is necessary to reduce the fine line interval W2 as much as possible. However, in the recent photolithography technology, in order to form a uniform narrow wiring having a long wiring length, the wiring interval of the narrow wiring is limited to about 1 μm. However, as shown in FIG. 6, the effective cross-sectional area is almost the same as in the case where no division is performed. On the other hand, the interval W2 narrow wiring and 1μm possible in the prior art, even the most effective 0.8μm width W1 of the narrow wiring at 40GH _Z, D
In order to obtain an effective cross-sectional area equivalent to that at the time of C, the total wiring width W is about 22 μm or more, and it is difficult to achieve high integration of the semiconductor device.

An object of the present invention is to provide a method of manufacturing a wiring structure which can be applied at a high frequency while suppressing the skin effect and realizes high integration.

[0008]

The production method of the present invention comprises:
Forming a first conductor film on a plate; and forming the first conductor film on the plate.
Selectively remove the film at the required interval, leaving a part of the lower side in the thickness direction.
Etching, arranged at the required intervals and the lower side
Forming a plurality of first narrow wirings connected by portions
Wiring of the first narrow wiring on the first narrow wiring
Step of depositing a first insulating film having a thickness smaller than the width dimension
Anisotropically etching the first insulating film to form the first insulating film.
Leaving only on the side surface of the narrow wiring, and the first insulating film
Exposed surface of the first conductor film exposed in a region sandwiched by
A second conductive film is selectively grown to form a second narrow wiring.
And a step of forming.

[0009]

In the present invention, as can be seen from FIG. 6, if the interval W2 between the narrow wirings can be made as small as 0.2 μm, the total wiring width W can be reduced to about 14 μm, and the semiconductor can be improved simultaneously with the improvement of the high frequency characteristics. The device can be highly integrated. In the present invention, the film thickness of the first insulating film can be controlled up to several hundreds of mm because of the conventionally used CVD method or the like, and the film thickness of the first insulating film can be reduced to about 1/10 of the stripe space obtained by the current lithography. Can be reduced. As a result, a wiring interval smaller than the width of the narrow wiring can be formed, so that a stripe-shaped wiring can be formed at most not exceeding twice the conventional wiring width. Can be realized.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are sectional views showing a reference example of the present invention in the order of manufacturing steps. In addition, this reference example is 4
This is an example in which the present invention is applied to a wiring having a stripe structure for supplying a high-frequency current of 0 GHz, in which a plurality of arranged narrow wirings have a wiring width W1 of 1 μm, an interval W2 of 0.2 μm, and a wiring width W of 8.2 μm. Shall be First, FIG.
As shown in FIG. 1A, T is deposited on a base insulating film 2 made of a silicon oxide film provided on a semiconductor substrate 1 by sputtering.
After depositing i: 100A and Au: 1000, Au: 1.8 μm and Ti: 100A are further deposited by vapor deposition to form a first metal film 3 having a laminated structure. Next, as shown in FIG. 1B, the surface of the first metal film 3 is formed by CVD.
After the silicon oxide film 4 is formed 5000 by the method, three photoresists 5 are opened at an interval of 1.4 μm by lithography on the area where the narrow wiring is to be formed. 4 is removed by anisotropic etching using CF 4 to remove the first metal film 3.
To expose.

Next, as shown in FIG. 1C, the exposed portion of the first metal film 3 is removed by etching over the entire thickness by using anisotropic etching of Ar particles, and the underlying insulating film 2 is removed. After the exposure, the photoresist 5 is removed to form a first narrow wiring 6 which is a part of the wiring to be formed. Subsequently, as shown in FIG. 1D, a silicon oxide film 7 is formed on the entire surface of the base insulating film 2 including the first narrow wiring 6 by the CVD method at 2500 °, and then vertical to the surface of the semiconductor substrate 1. Perform anisotropic etching with CF ₄ from the direction,
The silicon oxide film 7 is removed by etching at 2500 ° to expose the underlying insulating film 2 again. At this time, a silicon oxide film 7 of about 2000 ° is left on the side surface of the first narrow wiring 6. Also, 5000 nm of silicon oxide film layer 4 is left on the surface of first narrow wiring 6.

Next, as shown in FIG. 2A, a second layer of Ti: 100 ° and Au: 2 μm is vertically formed on the substrate by a vapor deposition method.
After forming the metal film 8, a photoresist 9 is applied to the entire surface of the substrate. At this time, the concave portion is filled with the photoresist due to the fluidity of the photoresist 9, while the photoresist 9 on the first narrow wiring 6 is thinned, and the surface of the photoresist 9 is entirely flat. Becomes After that, dry etching using CF ₄ is performed to expose the surface of the second metal film 8 until the thin photoresist 9 on the first narrow wiring 6 is removed as shown in FIG. ,
Further, the second metal film 8 is etched by dry etching using Ar particles to expose the surface of the silicon oxide film 4 on the first narrow wiring 6. As a result, it is possible to form the second narrow wiring 10 having a width almost equal to that of the first narrow wiring 6, and the first and second narrow wirings 6 and 10 are extremely different from each other in the wiring size W1. Small wiring interval W2
Is formed.

Next, as shown in FIG. 2C, the silicon oxide film 4 and a part of the silicon oxide film 7 on the side surfaces of the first narrow wiring 6 are removed by etching with CF _4, and the silicon oxide film 7 is left in the recess. After the photoresist 9 is removed, a photoresist 11 having a width of 8.2 μm is formed in a region including the first narrow wiring 6 and the second narrow wiring 10. Then, the first metal film 3 other than the portion covered with the photoresist 11 is removed again by the dry etching method using Ar particles,
The underlying insulating film 2 is exposed. As a result, as shown in FIG. 2D, a striped wiring having a wiring width W in which the first narrow wiring 6 and the second narrow wiring 10 having the narrow wiring width W1 are arranged at the wiring interval W2 is formed. It can be formed. here,
The wiring interval W2 is determined by the thickness of the silicon oxide film 7,
Since the CVD method for forming the silicon oxide film 7 can be formed to a thickness of several hundreds degrees with good control, the wiring distance W2 can be reduced to about 100 degrees, and the fine line distance W2 smaller than the fine line width W1. Can be formed.

In the wiring structure manufactured as described above, the first
Even when the wiring width W1 of the second narrow wirings 6 and 10 is set to 1 μm which is close to the limit of the photolithography technology,
Since the interval W2 between the narrow wirings is set to 0.2 μm, the overall wiring width W is 8.2 μm. Therefore,
An effective cross-sectional area at 40 GHz can be secured without increasing the wiring width W substantially, high-frequency characteristics can be improved, and high integration of the semiconductor device can be realized.

Next, an embodiment of the present invention will be described with reference to FIG. Note that parts equivalent to those in the reference example are denoted by the same reference numerals. First, the step of FIG. 3A shows an etching step of the first metal film 3 after performing the steps of FIGS. 1A and 1B of the reference example . In the embodiment, when the first narrow wiring 6 is formed by etching the first metal film 3, when the lower part of the thickness direction is left, that is, before the underlying insulating film 2 is exposed. End the etching. Here, the lower part of the first metal film 3 is 200
The thickness of 0A is left. Next, as shown in FIG. 3B, after removing the photoresist layer 5 on the surface, CVD is performed.
A silicon oxide film 7 is formed at 2500 A by the
The silicon oxide film 7 is removed by etching until the surface of the first metal film 3 is exposed between the first narrow wirings 6 using an anisotropic etching method according to the above. At this time, a silicon oxide film 7 of about 2000 A is left on the side surface of the first narrow wiring 6. Also, 5000 A of the silicon oxide film 4 remains on the upper surfaces of the first metal film 3 and the first narrow wiring 6.

Next, the first metal film 3 is used as a conductive path at the time of plating, and Au plating is performed to a thickness of 1.8 μm, thereby forming the first metal film 3 as shown in FIG. The second metal film 8 is formed in the exposed portion, that is, in a region sandwiched between the first narrow wiring 6 and the silicon oxide film 7. Therefore, the second metal film 8 is formed as it is as the second narrow wiring 10 having approximately the same width as the first narrow wiring 6. Here, the first and second narrow wirings 6, 10
Are connected at the lower part of the first metal film 3 in the thickness direction, and are arranged at an extremely small wiring interval W2 with respect to the wiring dimension W1 in the upper part of the thickness excluding this part. A striped structure is formed. After that, as shown in FIG. 3D, the silicon oxide film 4 is removed by dry etching with CF _4, and then, similarly to the process of FIG.
After that, the first metal film 3 excluding the wiring portion is removed by dry etching to expose the base insulating film 2 and form a desired wiring.

In the wiring structure of this embodiment, even if the wiring width W1 of the first and second narrow wirings 6 and 10 is 1 μm, which is a value close to the limit of the photolithography technique, the distance W2 between the narrow wirings can be reduced. Can be formed to 0.2 μm, and the wiring width W can be 8.2 μm. Therefore, the effective cross-sectional area at 40 GHz can be secured without increasing the wiring width W, and the high frequency characteristics can be improved. High integration of a semiconductor device can be realized. Further, in this embodiment, the first metal film 3 formed as a conductive path functions as a common conductive layer for each of the narrow wirings 6 and 10. Therefore, even if the impedance of each of the narrow wirings is shifted, this shift is reduced. Since it is kept to a minimum, it is also effective in suppressing current propagation loss.

Note that the wiring structure of the present invention is not limited to the above-described metal materials, and the values of the narrow wiring and the wiring interval, and further, the values of the wiring width and the wiring thickness are the same as those of the above-described embodiment. It is not limited to.

[0020]

As described above, the present invention provides the first
Selective etching of body film, leaving a lower part in the thickness direction
After the first narrow wiring formed at required intervals to form a first insulating film only on the side surfaces of the first narrow wiring by, the
A second conductor film is selectively formed in a region sandwiched between the first insulating films.
By growing and forming the second narrow wiring, the lower side
And a striped wiring structure in which the narrow wirings are arranged at wiring intervals extremely smaller than the wiring widths of the first and second narrow wirings. Thus, in the present invention, the influence of the skin effect, which has a large effect at a high frequency, can be reduced by dividing the wiring into fine lines, and the resistance change of the wiring can be reduced even when the frequency changes. As a result, a wiring structure having excellent high-frequency characteristics can be obtained. Further, since the wiring interval of the narrow wiring is determined by the thickness of the insulating film formed in a self-aligned manner and its etching conditions,
It is possible to easily form even a wiring interval as small as about m, a large increase in the wiring width can be suppressed, and an increase in the circuit area can be suppressed, and high integration of the semiconductor device can be realized. Further, in the present invention, by forming the wiring by the self-alignment, it is possible to obtain a wiring having a narrow width with good reproducibility even for a fine line having a long wiring length or a fine line having a complicated shape.

[Brief description of the drawings]

FIG. 1 is a first sectional view showing a reference example of the present invention in the order of manufacturing steps.

FIG. 2 is a second sectional view showing a reference example of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view showing an embodiment of the present invention in the order of manufacturing steps.

FIG. 4 is a diagram for explaining a skin effect in wiring.

FIG. 5 is a sectional view showing an example of a conventional method for manufacturing a wiring structure in the order of steps.

FIG. 6 is a diagram showing a stripe interval dependency of an effective wiring area.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Low-value insulating film 3 First metal film 4 Silicon oxide film 5 Photoresist 6 First narrow wiring 7 Silicon oxide film 8 Second metal film 9 Photoresist 10 Second narrow wiring 11 Photoresist

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205-21/3213 H01L 21/768

Claims (1)

(57) [Claims] A step of forming a first conductive film on a substrate; and selectively etching the first conductive film at a required interval except for a part of a lower side in a thickness direction. Forming a plurality of first narrow wirings arranged at a lower portion and connected at the lower part; and forming the first narrow wirings on the first narrow wirings.
Applying a first insulating film having a thickness smaller than the wiring width dimension of the narrow wiring, and anisotropically etching the first insulating film to form only the side surface of the first narrow wiring. Leaving a second conductive film selectively on an exposed surface of the first conductive film exposed in a region sandwiched by the first insulating film;
Forming a narrow wiring of the present invention.