JP3165809B2 - Judgment method of digital LSI simulation result - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for determining a simulation result of a digital LSI, and
The present invention relates to a method of determining a normal operation / malfunction based on a simulation result in a high-frequency operation.

[0002]

2. Description of the Related Art Conventionally, a method shown in FIG. 3 is used to determine a simulation result of a digital LSI.

Referring to FIG. 3, a simulation result of a digital LSI at a high frequency operation indicates a normal operation /
When determining a malfunction, first, a test pattern for logic confirmation is created (step s1), and the circuit operation is confirmed by low-frequency simulation (step s2). Thereafter, the frequency is changed from a low frequency to an actual operating frequency by Δh (H
z) The simulation is sequentially performed one by one (step s3). The setup time (SetUp) of the digital flip-flop (DF / F) inside the LSI
Time) and hold time (Hold Time)
Check whether or not is satisfied (step s
4).

If this check result is satisfied (step s5), it is checked whether or not the actual operation frequency has been checked (step s6). If the actual operation frequency has been checked, the operation is normal. Is determined (step s7). If the actual operating frequency is not checked,
Step s3 is executed again.

If the check result is not satisfied in step s5, it is determined that a malfunction has occurred (step s8).

[0006]

As described above, in the conventional digital LSI simulation result determination method,
After confirming the circuit operation by low frequency simulation, the frequency is sequentially increased from low frequency to actual operating frequency, simulation is performed, and it is checked whether the setup time and hold time of the DF / F are satisfied.
Since the normal operation / malfunction is determined, it is necessary to execute the simulation a plurality of times, and there is a problem that the determination of the simulation result becomes complicated.

In addition, in the conventional digital LSI simulation result determination method, when the frequency is increased from P1 (Hz) to P2 (Hz), (1 / P1)-(1 / P2)
If> (setup time + hold time) is satisfied, even if the circuit malfunctions, no error is output in the check whether the setup time and hold time in the simulation are satisfied, and the malfunction is determined. There is a problem that is not done.

Similarly, when the clock disappears due to the time difference between T _pdr and T _{pdf at} the gate in the high frequency operation, the setup time and the hold time are satisfied even though the circuit is actually malfunctioning. There is a problem that no error is output in the check as to whether or not the operation is normal, and the operation is determined to be normal.

An object of the present invention is to provide a simple and accurate LSI.
It is an object of the present invention to provide a method for judging the normal operation / malfunction of the device.

[0010]

According to the present invention, an LSI is provided.
A first step of determining whether or not the LSI is operating properly or malfunctioning based on the simulation result of the above, and obtaining change times of all output pins of the LSI by low-frequency simulation using a test pattern; A second step of obtaining an output expected value pattern for a high frequency based on the change time, a third step of obtaining an output pattern of all the output pins based on a simulation result of the LSI at the high frequency, The value pattern and the output pattern are compared and the LSI
And a fourth step of judging whether or not is normal. A method of judging a digital LSI simulation result is obtained.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.

Referring to FIG. 1, after creating a logic confirmation test pattern (step s11), a low-frequency simulation is performed to obtain all change times of all output pins of the LSI (step s12). Using this change time, an output expected value pattern for a high frequency having one clock width of 2W ₁ (ns) is calculated (step s13). The output expected value pattern is compared with the output pattern obtained by the high frequency simulation result of one clock width 2W ₁ (ns) (step s14). If the comparison result is correct (step s15), it is determined that the operation is normal (step s15).
16). On the other hand, if the comparison result is incorrect, it is determined that a malfunction has occurred (step s17).

Here, referring also to FIG. 2, FIG.
Is simulated at a frequency of 1 clock width 2W ₀ (ns) and the input / output waveform and 1 clock width 2W ₁ (ns)
2 shows input / output waveforms when a simulation is performed at a high frequency.

Now, the X-th pattern (X is an arbitrary natural number)
At the output pin A for the signal input to the LSI.
_Assuming that the BC change time is T _pdn , this T _pdn is the output delay time of the X-th pattern at the output pin ABC.
Since the output delay time is constant regardless of the frequency, 1
_Assuming that the change pattern of the output pin ABC at the time of simulation at a high frequency of the clock width 2W ₁ (ns) is the Y-th pattern, Y is represented by Y = X + integer Int (T _pdn / W ₁ ).

In this manner, an expected output value pattern at the time of high frequency simulation with one clock width of 2W ₁ (ns) can be created for all change points of all output pins of the LSI.

[0016]

As described above, in the present invention, the output expected value pattern and the output pattern based on the simulation result are compared with each other.
There is an effect that the normal operation / malfunction of the SI can be determined.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a determination method according to the present invention.

FIG. 2 is a waveform chart for explaining calculation of an output expected value pattern;

FIG. 3 is a flowchart for explaining a conventional determination method.

[Explanation of symbols]

 s1 to s8 step s11 to s17 step

Claims (2)

(57) [Claims] 1. A method for determining whether a normal operation or a malfunction of an LSI based on a simulation result of the LSI, and obtaining change times of all output pins of the LSI by low-frequency simulation using a test pattern. A first step, a second step of obtaining an output expected value pattern for a high frequency based on the change time, and a third step of obtaining an output pattern of all the output pins based on a simulation result of the LSI at the high frequency. And a fourth step of comparing the expected output value pattern with the output pattern to determine whether the LSI is normal or not. 2. The digital LSI according to claim 1,
In the method of determining a simulation result, in the second step, the change time of a predetermined output pin for a signal given to the LSI at the X-th (X is a predetermined natural number) pattern of the test pattern is defined as T _pdn , When the change pattern of the predetermined output pin with respect to the signal input to the X-th pattern at a high frequency of 1 clock width 2W (ns) is a Y pattern, a high frequency is applied to all change points of all output pins of the LSI. An expected output value pattern during operation is obtained by Y = X + integer Int (T _pdn / W), and in the third step, the one clock width 2W (n
a method for determining a digital LSI simulation result, wherein the output pattern is obtained at a high frequency of s).