JP3163621B2 - Clock frequency correction method for wireless terminal equipment - Google Patents

Clock frequency correction method for wireless terminal equipment

Info

Publication number
JP3163621B2
JP3163621B2 JP17116390A JP17116390A JP3163621B2 JP 3163621 B2 JP3163621 B2 JP 3163621B2 JP 17116390 A JP17116390 A JP 17116390A JP 17116390 A JP17116390 A JP 17116390A JP 3163621 B2 JP3163621 B2 JP 3163621B2
Authority
JP
Japan
Prior art keywords
clock
frequency
oscillation
circuit
wireless terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP17116390A
Other languages
Japanese (ja)
Other versions
JPH0460494A (en
Inventor
幸二 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17116390A priority Critical patent/JP3163621B2/en
Publication of JPH0460494A publication Critical patent/JPH0460494A/en
Application granted granted Critical
Publication of JP3163621B2 publication Critical patent/JP3163621B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、時計機能を有する無線端末装置において、
当該機能の時刻精度を向上させるためのクロック周波数
補正方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a wireless terminal device having a clock function.
The present invention relates to a clock frequency correction method for improving the time accuracy of the function.

[従来の技術] 無線端末装置には、基準発振周波数発生回路等の発振
回路部が組込まれているが、同装置に時計機能を付加す
る場合には、それらの発振回路部とは別に、さらに時計
機能用発振回路部を独立して設ける必要がある。すなわ
ち、基準発振周波数発生回路等、無線端末装置の主動作
に必要な回路は、同装置の電源オン・オフにより作動・
停止するが、時計機能用発振回路部は、装置電源がオフ
になっても常時作動させておかなければならないからで
ある。
[Related Art] An oscillation circuit unit such as a reference oscillation frequency generation circuit is incorporated in a wireless terminal device. However, when a clock function is added to the wireless terminal device, a separate oscillation circuit unit is additionally provided. It is necessary to provide a clock function oscillation circuit unit independently. That is, the circuits necessary for the main operation of the wireless terminal device, such as the reference oscillation frequency generation circuit, are activated and deactivated by turning the power of the device on and off.
This is because, although stopped, the clock function oscillation circuit section must always be operated even when the apparatus power is turned off.

[発明が解決しようとする課題] 上述した時計機能用発振回路部は、一般に、無線端末
装置内の基準発振周波数発生回路部等に比べ発振周波数
精度の悪いものを使用し、低コスト化を図っている。例
えば、パーソナルコンピュータに実装されている時計機
能用発振回路部のクロック周波数精度は、常温で±20PP
M程度であり、一箇月に約一分の誤差を生じている。
[Problems to be Solved by the Invention] Generally, the above-described clock circuit for a clock function has a lower oscillation frequency accuracy than a reference oscillation frequency generating circuit section or the like in a wireless terminal device, thereby reducing cost. ing. For example, the clock frequency accuracy of the clock function oscillation circuit unit mounted on a personal computer is ± 20 PP at room temperature.
It is about M, and an error of about one minute occurs in one month.

本発明はこのような事情にもとづいてなされたもの
で、時計機能の時刻精度を向上させることのできる無線
端末装置のクロック周波数補正方式の提供を目的とす
る。
The present invention has been made in view of such circumstances, and has as its object to provide a clock frequency correction method for a wireless terminal device that can improve the time accuracy of a clock function.

[課題を解決するための手段] 上記目的を達成するために、請求項1記載の発明は、
基準発振周波数発生回路部、および時計機能を実現する
ための時計機能用発振回路部を内蔵した無線端末装置に
おいて、 電源オンのとき、前記無線端末装置に内蔵された基準
発振周波数発生回路部で発生するクロック周波数と、前
記基準発振周波数発生回路より発振周波数精度の低い前
記時計機能用発振回路部で発生するクロック周波数とを
比較し、その比較結果にもとづき前記時計機能発振回路
部で発生するクロック周波数を補正し、電源オフ状態で
は前記時計機能用発振回路部で発生するクロック周波数
の補正動作を停止する方式としてある。
[Means for Solving the Problems] To achieve the above object, the invention according to claim 1 is
In a wireless terminal device including a reference oscillation frequency generation circuit unit and a clock function oscillation circuit unit for realizing a clock function, when the power is turned on, the reference oscillation frequency generation circuit unit included in the wireless terminal device generates the reference oscillation frequency. The clock frequency generated in the clock function oscillation circuit section is compared with a clock frequency generated in the clock function oscillation circuit section having a lower oscillation frequency accuracy than the reference oscillation frequency generation circuit, and based on the comparison result. And in the power-off state, the operation of correcting the clock frequency generated in the clock function oscillation circuit section is stopped.

また、請求項2記載の発明は、電源オンのとき、前記
無線端末装置に内蔵された受信周波数測定回路部で発生
するクロック周波数と、前記基準発振周波数発生回路よ
り発振周波数精度の低い前記時計機能用発振回路部で発
生するクロック周波数を補正し、電源オフ状態では前記
時計機能用発振回路部で発生するクロック周波数の補正
動作を停止する方式としてある。
The invention according to claim 2 is characterized in that, when the power is turned on, the clock frequency generated by the reception frequency measurement circuit unit built in the wireless terminal device and the clock function having lower oscillation frequency accuracy than the reference oscillation frequency generation circuit. In this method, the clock frequency generated in the clock oscillation circuit is corrected, and the operation of correcting the clock frequency generated in the clock function oscillation circuit is stopped in a power-off state.

[作用] 本発明は上述の構成としたので、電源オンの状態で
は、基準発振周波数発生回路あるいは受信周波数測定回
路部で発生したクロック(以下、基準クロックというこ
ともある)の周波数により、時計機能用発振回路部で発
生したクロック(以下、被補正クロックということもあ
る)の周波数を補正するため、被補正クロック周波数の
精度が基準クロックの精度なみに向上する。
[Operation] Since the present invention has the above-described configuration, the clock function can be performed in the power-on state by using the frequency of a clock (hereinafter, also referred to as a reference clock) generated by a reference oscillation frequency generation circuit or a reception frequency measurement circuit. Since the frequency of the clock (hereinafter, also referred to as a corrected clock) generated in the oscillator circuit for correction is corrected, the accuracy of the corrected clock frequency is improved as much as the accuracy of the reference clock.

一方、電源オフの状態では、基準クロックがなくなる
ので前記補正動作を停止し、時計機能用発振回路部で発
生したクロックの精度悪化を防止している。
On the other hand, in the power-off state, since the reference clock runs out, the correction operation is stopped, and deterioration of the accuracy of the clock generated in the clock function oscillation circuit is prevented.

[実施例] 以下、本発明の実施例について図面を参照して説明す
る。
[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図は本発明の第一実施例を示すブロック図であ
る。
FIG. 1 is a block diagram showing a first embodiment of the present invention.

図面において、1は基準発振周波数発生回路部、2は
時計機能用発振回路部であり、前者の方がクロック発振
周波数の精度は高い。これら回路部1,2で発生したクロ
ック信号は、周波数比較回路部3に出力され、同回路部
3において、基準発振周波数発生回路部1で発生した基
準クロックと比較される。周波数比較回路部3では、当
該比較動作により、被補正クロックの周波数が基準クロ
ックの周波数に対してどの程度ずれているかを検出し、
その検出結果を制御信号として可変分周回路部4へ出力
する。可変分周回路部4では上記被補正クロックのずれ
分だけ時計機能用発振回路部2の出力周波数を補正し、
当該クロック信号にて時刻計数回路部5を作動させて、
時刻の計数を行なう。
In the drawing, reference numeral 1 denotes a reference oscillation frequency generation circuit, and 2 denotes an oscillation circuit for a clock function, the former having higher accuracy of the clock oscillation frequency. The clock signals generated by the circuit units 1 and 2 are output to the frequency comparison circuit unit 3 and compared with the reference clock generated by the reference oscillation frequency generation circuit unit 1 in the circuit unit 3. The frequency comparison circuit unit 3 detects, by the comparison operation, how much the frequency of the clock to be corrected deviates from the frequency of the reference clock.
The detection result is output to the variable frequency dividing circuit unit 4 as a control signal. The variable frequency dividing circuit 4 corrects the output frequency of the clock function oscillation circuit 2 by the deviation of the clock to be corrected,
By operating the time counting circuit unit 5 with the clock signal,
The time is counted.

上記一連の動作は電源オンの状態のときのみ行なう。
すなわち、電源オフ状態においては、基準発振周波数発
生回路部1からの出力がないため、被補正クロックの周
波数がそのまま誤差として検出されてしまい、正常な補
正動作を行なうことができない。そこで、電源オフのと
きは、時計機能用発振回路部2のクロック信号をそのま
ま時刻計数回路部5に出力、時刻の計数を行なう。
The above series of operations is performed only when the power is on.
That is, in the power-off state, since there is no output from the reference oscillation frequency generation circuit 1, the frequency of the clock to be corrected is directly detected as an error, and a normal correction operation cannot be performed. Therefore, when the power is off, the clock signal of the clock function oscillation circuit section 2 is output to the time counting circuit section 5 as it is to count the time.

第2図は本発明の第二実施例を示すブロック図、第3
図は同ブロック中の受信波周波数測定回路を示すブロッ
ク図である。
FIG. 2 is a block diagram showing a second embodiment of the present invention, and FIG.
The figure is a block diagram showing a received wave frequency measuring circuit in the same block.

本実施例では、無線端末装置に受信部7、および受信
波の周波数を測定するための回路部(受信波周波数測定
回路部)8を備えている。そして、受信波周波数測定回
路部8で基準クロックを発生させ、この基準クロックの
周波数と被補正クロック(時計機能用発振回路部2から
出力)の周波数とを周波数比較回路3にて比較する。周
波数比較回路3では、被補正クロックの周波数が基準ク
ロックの周波数に対してどの程度ずれているかを検出
し、その検出結果を制御信号として可変分周回路部4へ
出力する。可変分周回路部4では第一実施例と同様に時
計機能用発振回路部2の出力周波数を補正し、当該クロ
ック信号にて時刻計数回路部5を作動させて、時刻の計
数を行なう。
In the present embodiment, the wireless terminal device includes a receiving unit 7 and a circuit unit (received wave frequency measurement circuit unit) 8 for measuring the frequency of the received wave. Then, the received wave frequency measuring circuit 8 generates a reference clock, and the frequency of the reference clock is compared with the frequency of the clock to be corrected (output from the clock function oscillation circuit 2) by the frequency comparing circuit 3. The frequency comparison circuit 3 detects how much the frequency of the clock to be corrected deviates from the frequency of the reference clock, and outputs the detection result to the variable frequency dividing circuit 4 as a control signal. As in the first embodiment, the variable frequency dividing circuit 4 corrects the output frequency of the clock function oscillating circuit 2 and operates the time counting circuit 5 with the clock signal to count time.

ここで、受信波周波数測定回路部8は、第3図に示す
ような構成となっている。すなわち、入力端子11から受
信波を入力し、局部発振周波数回路部14の出力と受信波
とをミキサ12で合成し、かつ中間周波数増幅器13にて周
波数の差成分を増幅する。続いて、分周器16により増幅
信号を分周し、出力端子18から基準クロックとして出力
する。
Here, the reception wave frequency measurement circuit section 8 has a configuration as shown in FIG. That is, a received wave is input from the input terminal 11, the output of the local oscillation frequency circuit 14 and the received wave are combined by the mixer 12, and the intermediate frequency amplifier 13 amplifies the difference component of the frequency. Subsequently, the amplified signal is frequency-divided by the frequency divider 16 and output from the output terminal 18 as a reference clock.

なお、図中15はディスクリミネータ、17は復調出力端
子である。受信波の周波数は精度の高い基地局側装置で
発生しており、通常は低温から高温までの広い温度範囲
(−20℃〜+60℃)で±5PPM以下である。
In the figure, 15 is a discriminator, and 17 is a demodulation output terminal. The frequency of the received wave is generated by the base station device with high accuracy, and is usually ± 5 PPM or less in a wide temperature range from low to high (−20 ° C. to + 60 ° C.).

したがって、出力端子18から出力される基準クロック
周波数は、第2図の時計機能用発振回路部2で発生する
クロック周波数より高精度である。
Accordingly, the reference clock frequency output from the output terminal 18 is more accurate than the clock frequency generated in the clock function oscillation circuit unit 2 in FIG.

第二実施例においても、時計機能用発振回路部2から
出力したクロック周波数の補正は電源オンのときのみ行
ない、電源オフ時には当該補正動作は行なわない。
Also in the second embodiment, the correction of the clock frequency output from the clock function oscillation circuit unit 2 is performed only when the power is on, and the correction operation is not performed when the power is off.

[発明の効果] 以上説明したように本発明は、無線端末装置が電源オ
ンのとき、時計機能用発振回路部で発生するクロック周
波数を、より精度の高い基準発振周波数発生回路部から
のクロック周波数あるいは基地局等から送られてきた受
信波の周波数と比較することにより、当該時計機能用発
振回路部のクロック周波数を補正し、これにより時計精
度の向上を図ることができる効果がある。
[Effects of the Invention] As described above, according to the present invention, when the wireless terminal device is powered on, the clock frequency generated by the clock function oscillation circuit unit is changed to the clock frequency from the reference oscillation frequency generation circuit unit with higher accuracy. Alternatively, the clock frequency of the clock function oscillation circuit section is corrected by comparing with the frequency of a received wave transmitted from a base station or the like, and thereby there is an effect that clock accuracy can be improved.

【図面の簡単な説明】 第1図は本発明の第一実施例を示すブロック図、第2図
は本発明の第二実施例を示すブロック図、第3図は第二
実施例における受信波周波数測定回路を示すブロック図
である。 1:基準発振周波数発生回路部 2:時計機能発振回路部 3:周波数比較回路部 4:可変分周回路部 5:時刻計数回路部 7:受信部 8:受信波周波数測定回路部 11:入力端子 12:ミキサ 13:中間周波数増幅器 14:局部発振周波数回路部 15:ティスクリミネータ 16:分周器、17:復調出力端子 18:出力端子
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a block diagram showing a second embodiment of the present invention, and FIG. FIG. 3 is a block diagram illustrating a frequency measurement circuit. 1: Reference oscillation frequency generation circuit 2: Clock function oscillation circuit 3: Frequency comparison circuit 4: Variable frequency divider 5: Time counting circuit 7: Receiver 8: Received wave frequency measurement circuit 11: Input terminal 12: Mixer 13: Intermediate frequency amplifier 14: Local oscillation frequency circuit 15: Tiscriminator 16: Divider, 17: Demodulation output terminal 18: Output terminal

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】基準発振周波数発生回路部、および時計機
能を実現するための時計機能用発振回路部を内蔵した無
線端末装置において、 電源オンのとき、前記無線端末装置の内蔵された基準発
振周波数発生回路部で発生するクロック周波数と、前記
基準発振周波数発生回路より発振周波数精度の低い前記
時計機能用発振回路部で発生するクロック周波数とを比
較し、その比較結果にもとづき前記時計機能発振回路部
で発生するクロック周波数を補正し、 電源オフのときは、前記時計機能用発振回路部で発生す
るクロック周波数の補正動作を停止することを特徴とし
た無線端末装置のクロック周波数補正方式。
1. A wireless terminal device incorporating a reference oscillation frequency generating circuit portion and a clock function oscillation circuit portion for realizing a clock function, wherein when the power is turned on, the reference oscillation frequency built in the wireless terminal device is provided. A clock frequency generated by the clock generation circuit is compared with a clock frequency generated by the clock oscillation circuit having a lower oscillation frequency accuracy than the reference oscillation frequency generator. And correcting the clock frequency generated in the clock function oscillation circuit unit when the power is off.
【請求項2】受信周波測定回路部、および時計機能を実
現するための時計機能用発振回路部を内蔵した無線端末
装置において、 電源オンのとき、前記無線端末装置に内蔵された受信周
波数測定回路部で発生するクロック周波数と、前記基準
発振周波数発生回路より発振周波数精度の低い前記時計
機能用発振回路部で発生するクロック周波数とを比較
し、その比較結果にもとづき前記時計機能発振回路部で
発生するクロック周波数を補正し、 電源オフのときは、前記時計機能用発振回路部で発生す
るクロック周波数の補正動作を停止することを特徴とし
た無線端末装置のクロック周波数補正方式。
2. A wireless terminal device having a built-in reception frequency measurement circuit portion and a clock function oscillation circuit portion for realizing a clock function, wherein a reception frequency measurement circuit built in the wireless terminal device when the power is turned on. The clock frequency generated in the clock function oscillation circuit is compared with the clock frequency generated in the clock function oscillation circuit having a lower oscillation frequency accuracy than the reference oscillation frequency generator, and the clock frequency generated in the clock function oscillation circuit is determined based on the comparison result. A clock frequency correction method for a wireless terminal device, comprising: correcting a clock frequency to be performed, and stopping a clock frequency generated by the clock function oscillation circuit unit when the power is off.
JP17116390A 1990-06-28 1990-06-28 Clock frequency correction method for wireless terminal equipment Expired - Lifetime JP3163621B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17116390A JP3163621B2 (en) 1990-06-28 1990-06-28 Clock frequency correction method for wireless terminal equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17116390A JP3163621B2 (en) 1990-06-28 1990-06-28 Clock frequency correction method for wireless terminal equipment

Publications (2)

Publication Number Publication Date
JPH0460494A JPH0460494A (en) 1992-02-26
JP3163621B2 true JP3163621B2 (en) 2001-05-08

Family

ID=15918165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17116390A Expired - Lifetime JP3163621B2 (en) 1990-06-28 1990-06-28 Clock frequency correction method for wireless terminal equipment

Country Status (1)

Country Link
JP (1) JP3163621B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101779011B1 (en) * 2015-10-29 2017-09-18 주식회사 케이넌코리아 LED light lamp devices

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2710557B2 (en) * 1994-04-26 1998-02-10 静岡日本電気株式会社 Time correction method for radio selective calling receiver
JPH09113654A (en) * 1995-10-16 1997-05-02 Nec Ic Microcomput Syst Ltd Intermittent receiver controller
US6208292B1 (en) * 1998-09-09 2001-03-27 Qualcomm Incorporated Position location with low tolerance oscillator
JP4051840B2 (en) * 1999-05-28 2008-02-27 富士電機システムズ株式会社 Synchronizer for distributed system equipment
JP2010008294A (en) * 2008-06-27 2010-01-14 Kyocera Corp Communication device and clock compensating method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101779011B1 (en) * 2015-10-29 2017-09-18 주식회사 케이넌코리아 LED light lamp devices

Also Published As

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JPH0460494A (en) 1992-02-26

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