JP3162321B2 - Logic simulation method and computer-readable recording medium recording program for implementing the logic simulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design verification method for verifying the validity of logic of a digital circuit LSI used in a computer or the like by simulation.

[0002]

2. Description of the Related Art Prior art is described in relation to LSI design and logic simulation, how to implement logic simulation, relationship between logic simulation and real machine debugging, test data for logic simulation, and automatic generation of test data for logic simulation. Will be described.

In general, as a basic design flow when designing an LSI, first, a higher-level specification is embodied in an internal specification of the LSI, and the internal specification is logically divided into modules to determine the specification. Next, registers, selection circuits, addition and subtraction circuits, which are hardware resources for each module,
An encoding / decoding circuit is determined, and how to control them is determined. The resources and control information are described in a register transfer level description language (RTL). RTL
After correcting the grammatical error and the semantic error of the description language as appropriate, the grammatical error and the semantic error are input to a simulator that can understand the RTL language, and the description error or specification level error is corrected by logic simulation.

[0004] The unit of the logic simulation starts with a single module, a plurality of modules, a higher-level module, and a L module.
Increasingly the SI alone, a plurality of LSIs, a printed circuit board on which the LSIs are mounted, and a system. When the description by the logic simulation is no longer incorrect, the logic logic is used to synthesize the gate logic using RTL as a source language. The number of gates and gate delay or wiring delay are optimized so as to conform to the specification by the function of the tool itself and manually specified data. If necessary, the original architecture may be changed, such as changing the connection between modules or changing the transfer method between registers, so that the RTL source may be changed. In that case, the simulation is redone.

When the conditions of logic, timing, and thermal design are satisfied, an LSI maker creates an LSI mask and manufactures an LSI for the gate circuit, and performs DC at the wafer level of the LSI based on connection information and manually created data. Test / Functional operation test and AC test, after the same test after mounting on the package,
A user DC test is performed and non-defective products are sampled and shipped to users.

A user mounts the LSI on a printed circuit board and performs a test on an actual system. In this test, debugging is performed in the order of hardware test, functional test by diagnostic program, heavy load and diversified test that accelerated the test of actual use environment called system diagnostic program, and comprehensive test by operating system and application. . In the course of these tests, there are few defects in the manufacture of the LSI, problems with the attachment to the printed circuit board, defects in other components, errors in the logic design of the LSI, errors in the logic specifications, timing design errors, noise and signal waveforms. A design defect that depends on the transmission is found. In particular, with regard to defects in logic design and logic specifications, there are many things that cannot be corrected unless the inside of the LSI is changed, and it is important how to perform logic verification well. If the LSI sample is re-created many times, there is a problem that the development cost to be paid to the LSI maker and the turnaround time from the change to the sample acquisition become long.

As logic simulation methods, (1) a method of performing a gate simulation with software on an engineering workstation (2) a method of performing an RTL simulation with software on an engineering workstation (3) a gate simulation on a dedicated simulation machine (4) Pseudo realization of logic equivalent to LSI using simulation hardware using FPGA (field programmable gate array) and actual LSI
(5) It is general to take any combination of the above and emulate the operation at a fraction of the actual clock frequency instead of the above, and the usage pattern is shifting in the above order .

[0008] The gate simulation as described in the above (1) is a method which has been known for a long time as an event driven method, and its principle is introduced in a book related to CAD (Computer Aided Design), and a commercially available logic simulator uses this method. There are many basic ones. (2) is the above (1)
As modifications, there are a method in which the simulation speed is improved as shown in Japanese Patent Application Laid-Open No. 6-274564 and a method in which the operation evaluation order is given a level under the restriction that the circuit to be simulated is a synchronous circuit. (3)
Is a special-purpose computer with an architecture suitable for logic simulation, one that optimizes the structure of instructions, data and addresses, one that optimizes pipeline processing,
Some use parallel processing. JP-A-6-96152 is one example. In (4), as shown in the conventional example of JP-A-6-160482, the operation of the circuit to be simulated is realized using an FPGA with a fraction of the actual clock.

From the viewpoint of how to implement logic verification and system debugging: (1) A method in which logic verification is limited to a simple LSI simulation, and the emphasis is placed on how quickly the LSI is manufactured based on the results of actual machine debugging. (2) A method in which a considerable part of the system level operation is performed in the logic simulation to relatively shorten the actual machine debug period. (3) Minimize the logic simulation, and
A method of finding a defect by an operation close to the actual use environment using the method (4) using PGA. There is.

Test data used for logic simulation generally takes the following form depending on the scale of a circuit to be simulated. (1) Matching of expected value of output data according to combination of input data of combinational circuit (2) Change of output data when clock and input data are given in time series to sequential circuit (3) Operation By giving data and control signals together with a clock to a logical block having the above meaning, signal exchange with another logical block is partially realized, and the output response of the logical block is inspected. (4) LSI On the other hand, by providing data and a control signal together with a clock, signal exchange with another logic block is partially realized, and the output response of the logic block is inspected.

(5) Mixed with other LSIs and peripheral circuits,
By providing data and control signals together with the clock, signal exchange with other logic blocks is partially realized, and the output response of the logic blocks is inspected. (6) Mixed with other LSI and peripheral circuit simulation models In this state, a register or an operation command of the peripheral circuit is set and the peripheral circuit is started up. As a result, the data to be verified and the control signal are indirectly applied to the LSI to be verified, thereby enabling the verification of the circuit to be verified and other LSIs and the like. Check the protocol operation with the peripheral circuit. The result inspection method is LSI
Check of the response signal waveform of the above, and the reception response value of the peripheral circuit is stored and inspected after the simulation, LS
Check the value of the I internal register after simulation, etc.

(7) A function as a computer is provided in a state of being mixed with an actual simulation model or a simplified simulation model of another LSI, main memory, I / O circuit, and a diagnostic program, an operating system, and an application program are provided. The data is loaded into the main memory and the operation of the entire computer is performed. The programs to be loaded are limited to those that can be used efficiently in simulations, such as those in which operations such as I / O are partially removed, those in which only portions that can be processed are cut out, and those in which operations are frequently repeated are removed. . In the case of a diagnostic program, automatic comparison can be performed with expected values. In the case of another program, it is determined whether the normal operation can be performed by means such as the hardware and the program not hanging, the program ending, and comparing the data on the I / O or the main storage of the execution result of the program as an expected value. .

As described above, there is the following tendency as the scale of the circuit to be simulated is increased. (A) Test data becomes objective, and shifts from careless mistakes in logic design to defect detection due to specification errors. (B) Generally, the productivity of test data is high. (C) Cause analysis becomes more difficult. (D) Simple defects in control depending on data and address patterns are difficult to find. (E) The specific gravity of the test content shifts from the test intended by the designer to a more objective test. (F) The coverage by the test becomes difficult to understand. (G) The rate at which a defect can be detected with respect to the number of clocks is greatly reduced. (H) The productivity of test data of a circuit "contrived to speed up the operation" is reduced.

As shown in the above (6), the method of making test data using an actual program is based on the above-mentioned FPGA.
This is a method that is often used in emulation, but depends on the coverage of a diagnostic program or the like.
In particular, a program called a system diagnostic program uses a test with an increased multiplicity and exhausts an operation pattern due to an external factor such as variation in I / O operation. As a result, an operation under an actual operating system is performed for a very short time. However, the effect of emulation cannot be expected due to differences in the test environment.

In the actual machine test by prototyping,
Turnaround time from defect analysis to correction is L
This is a major problem in the SI development process. In the emulation method, the coverage cannot be secured as much as the actual machine test, but the problem of the turnaround time including the difficulty of analysis remains. This is because it involves trial and error work such as how to go back to the time when the cause occurs from the state detected as inconsistency after an enormous number of clocks and find a point in time when the operation becomes erratic. Therefore, it is likely that considerable problems will be detected by the following automated test data using simulation, and that final tests will be performed on actual equipment tests and emulation tests.

[0016] On the other hand, as automation of test data used for the simulation, 6B-3 "Test program automatic generation tool" MTS "
As described in “Development of T” and 6B-4 “System Level Verification Using Automatic Test Program Generation Tool“ MTST ””, a simulation environment is constructed by sandwiching the LSI to be tested and the circuit to be tested. There is also a method of exhausting a bus transaction pattern between a parameter specified by a random number, a specified bus request, and a request interval.

In addition, 4 of the 53rd National Convention of IPSJ
F-07 "Pentium Pro SMP BridgeChip Set Large-Scale Logic Verification Technology" discloses use of operations including secondary cache control for the tertiary cache of the circuit to be verified, confirmation of data consistency and data value Have been. However, the algorithm for determining the expected value by mixing the operation of the tertiary cache level and the operation of the secondary cache level, the initial setting method therefor, and the method of determining the expected value when the same address is mutually accessed are determined by the presence or absence of the function. Not disclosed.

FIG. 9 shows the information processing system of the 50th National Convention of the Information Processing Society of Japan.
B-4 "Test program automatic generation tool" MTST "
Is a diagram showing the structure of a conventional test data automatic generation tool shown in "System Level Verification by Test". In FIG. 9, reference numeral 51 denotes an LSI to be tested, 2 denotes a circuit to be tested, 6
Is a test generation unit, 54 is a unit that dynamically captures and drives signals while interfacing with other circuits during simulation execution, and 8 is a bus whose operation state and differences are visible to the outside.

Next, the operation of the conventional example will be described. First, a circuit operation that does not depend on test generation will be described. FIG.
Then, a memory read access request is sent from the processor 2a to the N-level cache 1a together with the address via the processor bus 8a. If the N-th cache 1a hits, a response and data are returned for the transaction, and the operation ends. If the N-th cache 1a also misses, the N-th cache 1a is issued to the memory 1b via the system bus 8b. The memory 1b returns a response and data to the N-th cache 1a via the system bus 8b.
Returns the response and data to For data, valid timing is indicated by a DRDY signal indicating the presence of data.

FIG. 11 shows a data transfer when the data is in the M (modify) state in the MESI state in the MESI state instead of the memory in response to the memory read request from the I / O model. A memory read request and an address are issued from the I / O model 2b to the bus 8c, and the bus bridge 1c receives this and sends it to the system bus 8b. The memory 1b prepares the main storage data and prepares to send it to the bus 8c, and the N-level cache 1a
Wait for a snoop signal HITM from Nth cache 1
"a" pulls the cache, recognizes that the address is in the M state in the Nth cache, and reads "memory data is old".
Assert a snoop signal HITM, assert a response signal, and
Send a signal on the system bus to invalidate that line in the Nth cache.

The memory 1b sees the assertion of the snoop signal and cancels the transmission on the system bus, receives the response signal, captures the data when the DRDY signal is asserted, and updates the data back to the main memory. The bus bridge 1c receives the response signal and receives the DRD
The data when the Y signal is asserted is captured.
At the same time as the Nth cache is invalidated, the request and the address for making the processor 2a invalidate the cache line are sent to the bus 8a. Note that, in this example, for simplicity of explanation, the description is based on the assumption that the N-1st cache in the processor is a write-through system and the Nth cache is a write-back system.

FIG. 12 shows a connection example of the system bus signals used in the above description, and FIG. 13 shows the relationship between the signals. Although the description is omitted in this example, there is a separate signal for arbitrating the bus access right. As a result of the arbitration, the LSIs on the buses 8a to 8c, which have obtained the right to use the bus,
Signal REQ indicating request type and request validity
Is driven together with the address ADDR. From the address and the type of request, the LSI having the N-th cache refers to the contents of the cache and determines whether or not the cache has the latest data in the M state from the main memory. The LSI having the function of the memory performs read start of the memory data or preparation for writing by looking at the address and the type of the request. The LSI having the cache function notifies the memory whether or not it is in the M state by the HITM signal within a fixed cycle from the request. The memory drives the RESP signal which is a response by seeing the HITM signal as a result of the cache snoop. The data transfer is driven by the memory or the M-state cache LSI. At that time, DRDY indicating the significance of the data is driven. In the example of FIG. 13, the first bus transaction indicates reading from the memory, and the next bus transaction indicates reading from the cache.

Recent designs, such as this example, employ a pipelined architecture for bus operation. FIG.
In the case of a design that implements a four-stage pipeline using separate signals for request, snoop, response, and data transfer as in the example of 3, and has flexibility in the drive timing of the snoop, response, and data transfer signals. The condition of operation on the bus becomes enormous. Specifically, in addition to the combination of the signal values and the timing,
In the busy state and the cache state.

Next, an example of generating test data will be described. An example will be described in which the targets of the test are combined for two consecutive transactions on the system bus. (1) For the first transaction on the bus, select the LSI that issues the request and the request from the conditions manually specified. The address is determined using a random number.
At this time, if part of the address has a special meaning in operation, manual designation data may be used. (2) Next, to generate the transaction,
The request of another bus connected to the SI and the cache state of the LSI are determined. If there are a plurality of realization methods, the method is selected by using a random number. (3) Next, a response value on the system bus is determined.
If the value is specified within a range that does not conflict with the request, the value is adopted. If the value conflicts, a warning is issued or the value is adjusted to a value that does not conflict.

(4) A snoop value is determined by a random number within a range not inconsistent with the response value and the request. (5) Initial values of the cache and the memory are determined by random numbers based on the snoop value. If the request is a write request, determine the value to be stored in the buffer. (6) Calculate the cache memory, memory, and buffer values at the end of the transaction from the above values. (7) The second transaction is determined in the same manner as (1) to (6). However, a random number is selected so that the cache line (a cache management unit and also referred to as a block) does not completely match. Otherwise, the response value cannot be predicted depending on the timing. 8) The interval between request signals on the system bus is manually specified or determined by random numbers. In order to realize this interval, the delay of the bus 8a to the bus 8b, the bus 8
c, the delay of the bus 8b is calculated, and the difference is calculated by the DRV.
It is used as a wait time for either x or DRVy.

The above is the processing of the test generator. Before starting the test, the adapter unit sets the request code, the address, the waiting time until the request is issued for the DRVs 1 to 4, and also sets the initial values of the memory and the cache. Although not shown in the drawing, the test control unit activates the generation unit, and after the generation is completed, performs reset and setting via the adapter unit. Next, the test control unit generates a clock, and continues to generate a clock via the adapter unit until each DRV has no waiting state and is idle and becomes idle in the circuit under test. When this waiting state is completed, the test control unit checks whether the expected value determined by the test generation unit matches the expected value.
Check the values of the memory, cache, and DRV buffers.

It is difficult to determine and implement the snoop timing and response timing on the system bus, and it can be realized only by giving a considerable operation restriction, which causes a decrease in test coverage. However, when the bus connected to the non-test target circuit is to be tested, the test can be performed by setting a response delay value in the non-test target model for which the noop timing and the response timing have been determined. A test that causes an operation conflict in the circuit under test sandwiched between two buses can be implemented in a similar manner to the above method, but the timing control is easily affected by the detailed design conditions of the circuit under test. In reality, it cannot be calculated easily, so only trial and error and rough timing control can be expected.

Next, 4 of the 53rd National Convention of the Information Processing Society of Japan
F-07 “Pentium Pro SMP BridgeChip Set Large-Scale Logic Verification Technique”, ie, bus operation at the Nth cache level and N-1 cache level operation for the Nth cache included in the circuit under test The method of realizing various operating conditions more spontaneously by using the above will be described. It is disclosed that a test shown in FIG. 14 is automatically generated for the following test items using random numbers. (1) Type of operation to be generated on the bus (2) Interval between operations on the same bus (3) Response interval between operations on the same bus (4) Contention between upper and lower buses (5) MESI of tertiary cache memory State Also, items to check the test result are (1) Value stored in cache / main memory and (2) Data consistency.

The above information processing society 53rd national convention 4F
In the method disclosed in -07, since the Nth level bus request is naturally generated from the (N-1) th level access, each model corresponds to the operation instead of the test generation unit, and the generation tool can be easily created. However, there is an improvement in that the operation can be executed for the same address, but the following points are disadvantageous compared to the method disclosed in 6B-4 of the 50th National Convention. (1) It is difficult to control so that the request is closed by the N-1st operation and a request appears on the Nth bus. (2) Since the N-th cache is used by the (N-1) -th operation, inconsistency occurs if the cache is explicitly specified in the N-th bus access operation that is issued in the same test. . Thus, an Nth bus operation that can be more directly tested loses its advantages.

(3) In the final data value confirmation at the completion of the simulation, even if there is a defect during the operation, the confirmation of the result is insufficient. (4) Even if an error is detected when the simulation is completed, it takes a long time to analyze, and it takes time to distinguish an error in a non-test target circuit or an error in test data from a defect in the test target circuit. (5) If an attempt is made to save the simulation time until the operating conditions are realized by performing the initial setting of the N-th cache and the N-first cache, it is difficult to generate a test so as to maintain the cache inclusion relation. There is a problem that the test effect is weakened, for example, the restrictions are increased, and the initial settings performed are evicted by another bus transaction, so that the number of clocks in one test is increased to avoid them, and the initial state of the cache is increased. Is used in such a way that the processor repeats the loading and replacement of data into the cache by itself starting from the invalid state after the reset, so that the test efficiency is reduced.

[0031]

Since the conventional logic simulation method is configured as described above, there are the following problems. (1) If the conditions are made almost random, the operations will be averaged out, and unless a specific condition occurs, the part that does not operate will not be activated, and as a result, a condition that increases the coverage of circuit verification cannot be generated. Therefore, if the number of manual designations is increased, inconsistency between the designated conditions is increased. If the conditions are manually specified finely while avoiding inconsistent conditions, the problem of coverage is alleviated, but test omissions are more likely to occur. (2) When a combination of a plurality of bus transactions can be handled, the test generation algorithm is complicated to satisfy the condition, the convergence of the algorithm itself is poor, and the external specification of the circuit to be tested is invisible. The number of operations dependent on the logic design increases, and the test generator is frequently revised. (3) It takes time to distinguish between a defect in the test generation algorithm and a defect in the circuit under test, and when both have a defect, the turnaround of the defect detection is poor.

(4) It is desirable to prepare a plurality of test generation algorithms and select them as appropriate to control the test coverage so as not to lower the test coverage. However, it is difficult to grasp the causal relationship, and there are many trial and error elements, which is actually quite difficult. (5) As a result, the number of detected failures is lower and the effect of automation is lower than the total number of days required to change the creation of the generation tool. (6) It is difficult to share and develop the generation tool with many people. (7) The control of the timing is complicated and there are many trial and error factors. (8) The test is not effective for the one whose expected value changes when the timing changes, such as verification of the same address.

The present invention has been made to solve the above problems, and has the following objects. (1) The non-verification target circuit operates within each closed operation specification without observing the whole system operation, and operates basically with independent parameters. Realized as a model that has a dependent operation relationship with the peripheral circuit or the circuit to be verified only by information, simplifying the development of the model, simultaneous development by multiple people, increasing the independence of specifications, and shortening the development period And reduce the total number of development days. (2) To prevent a reduction in test coverage by causing an objective and spontaneous interaction between non-verified circuits connected to a circuit to be verified without using a complicated algorithm. . (3) In addition to the above, requests on the bus to average coverage from the viewpoint of activation of the circuit to be verified,
Make it possible to limit addresses and the like and specify their frequency.

(4) Since the objectivity is impaired if the command is generated at the bus command level connected to the circuit to be verified, N is different from the N-level cache corresponding to the bus level.
The specification of the condition generation algorithm is not performed, for example, such that the access of the primary cache level is mixed and the request is indirectly output to the bus as a result to improve the objectivity. Address management is performed so that inconsistency due to coexistence does not occur. (5) Since the timing control is performed automatically, the non-verification target circuit has a completely automatic response for the bus protocol with other circuits connected via the bus, and basically the shortest number of clocks from the causal signal. Logic is set up so that it responds with a delay value, and a delay value is provided so as to respond by adding a delay of the specified number of clocks to the shortest clock number. By responding according to the slowest combination, the controllability of the timing is improved, and malfunction does not occur due to inconsistency in designation.

(6) In order to prevent the operation delay from being unpredictable due to the matching of the addresses and the bus operation order being disturbed due to the retry of the bus transaction, making it difficult to generate expected values, The same effect can be obtained by setting the final value of the main memory or the cache memory as the expected value, and checking the intermediate value of the data of the main memory or the cache memory with the final value without checking the value. (7) Usually, a large number of clocks are required to reach a random stable state in order to realize a spontaneous operation randomness, but this state is realized at high speed and the number of clocks is reduced. (8) Inspection of the final value of the main memory alone usually lowers the test coverage significantly, but complements the reduction. (9) The management of data at the same address is reliably and simplified, the test constraints are reduced, and the test coverage is expanded. (10) Improve the reproducibility of tests that are problematic in automatic tests using random numbers. (11) Enhanced error check and inconsistency check functions to reduce errors in test data, errors in the non-verification target circuit, and defects in the verification target circuit at the time of occurrence and reduce the time for analysis and analysis. I will provide a.

[0036]

According to the present invention, there is provided a logic simulation method comprising the steps of: MESI (Modified, ESI);
xclosed, shared, invalid
Attended), there are four cache states.
A simulation model including a cache system including a MESI state which is a write-back type cache in which the N-th cache includes the N-th primary cache, a test generation unit for generating test data, and a test data included in the generated test data A monitor unit for resetting and setting the simulation model, controlling clock supply and stopping, and comparing expected values after completion of simulation for each test and determining test results in accordance with instructions. Specify the state values, set the data values for the above simulation model as initial values at the beginning of each test so that operation errors can be detected according to the state of the cache, and compare their final values with expected values at the end of the test. Of the circuit to be verified It is intended to confirm the validity of the work.

When the Nth cache is in the state E or the state S, a different data value is set in the Nth cache from the same address as that of the Nth cache in the main memory, and a bypass instruction is tested.

Further, the above-mentioned N-th cache is in the state E
Alternatively, in the state S, a data value different from that on the same address as that of the main memory of the N-th cache is set in the main memory to test access without bypassing the cache.

Further, MSI (Modify)
d, Shared, Invalidated)
Write-back type with up to three cache states
The MSI state, which is a cache of
A simulation model composed of a cache system in which the next cache includes an N-1 primary cache; a test generation unit for generating test data; resetting and internal setting of the simulation model and clock supply control in accordance with instructions included in the generated test data; A monitor unit for stopping control, comparing expected values after completion of simulation for each test, and judging test results is provided. Operating conditions and cache state values as operations used for verification are specified, and data values for the simulation model are cached. At the beginning of each test, initial values are set so that an operation error can be detected according to the state, and at the end of the test, the final values are compared with expected values to confirm the validity of the operation of the circuit to be verified.

When the (N-1) th cache is in the state M, a data value different from the data value in the state M is set on each of the same addresses in the Nth cache and the main memory.

Further, the N-th cache is in the state S
At this time, a data value different from that on the same address as that of the N-th cache in the main memory is set in the N-th cache and a bypass instruction is tested.

[0042] In addition, the N-order cache gas Tate S
At this time, a data value different from that on the same address as that of the main memory of the N-th cache is set in the main memory to test access without bypassing the cache.

Furthermore, a bus to which an agent for driving a request and a response is connected, a simulation model including a bus monitor connected to the bus for checking a bus protocol, a test generation unit for generating test data, A monitor unit that resets and sets the simulation model, controls clock supply and stops, and compares expected values after completion of simulation for each test and determines test results in accordance with the instructions included in the performed test data. Specifies the operating conditions as, those inconsistencies errors middle bus protocol test data values for the simulation model is set as an initial value at the beginning of each test to verify the validity of the operation as an expected value that there are no It is.

The bus monitor checks the bus transaction of each bus and, for the bus protocol, matches the bus arbitration result with the request issuing agent, inconsistency in the request code and address range, inconsistency in the request code and data transfer length, undefined It checks whether there is any of these protocol violations, which are not code values, and for which a response whose response cannot be separated, and notifies the monitor unit when a violation is detected, and then interrupts the simulation by the monitor unit.

Further, the bus monitor checks the bus transactions of each bus and inconsistencies between the shake hand signals and the pipeline between N bus transactions and N bus bus transactions which have already been issued for those bus transactions. Check for any of the following: stage overtaking, response signal timeout, detached bus transaction response transaction omission, detached response transaction overtaking original transaction, overflow of each pipeline stage, protocol violation, The simulation is interrupted by the monitor unit after notifying the monitor unit when a violation is detected.

When a plurality of agents simultaneously drive different values for the signals of each bus with respect to the buses, the bus monitor checks the signal values on the simulation model for undefined values or abnormal signal strengths. After notification to the monitor unit at the time of detection, the simulation is interrupted by the monitor unit.

Further, the bus monitor checks the presence or absence of a code error by checking the switch setting when a redundant code such as a parity or an ECC check code is added to each bus signal, and notifies the monitor unit when a code error is detected. The simulation is interrupted by the monitor unit.

Also, a counter circuit for counting the number of cycles between signals is connected to the simulation model, and the history of the number of cycles of the signal is recorded in transaction units. Is taken out and compared with the expected value.

Further, a counting circuit for counting the number of transactions is connected to the simulation model, a history of the number of transactions is recorded, and at the end of the test, the monitor section takes out the accumulated history and compares it with an expected value. .

In addition to the above-mentioned simulation model, there is provided an additional circuit dedicated to simulation for performing an error check. The additional circuit dedicated to simulation includes a circuit for identifying an improper state in which the operation of the agent is not idle or a flag in the circuit of the agent. It has a circuit for detecting an improper state in which a register is set, and notifies the monitor section that the operation of the agent is in an improper state at the end of the test, and then interrupts the simulation by the monitor section.

Further, at the end of the test, the monitor unit determines that the agent is in an invalid state.

Further, a simulation model composed of a bus connecting between the circuit to be verified and the non-verification circuit, a test generation unit for generating test data, and a simulation model of the simulation model according to instructions included in the generated test data. A monitor unit for reset and internal settings, clock supply control and stop control, and comparison of expected values after completion of simulation for each test and test result determination, specifies operating conditions as operations used for verification, and data for the simulation model. Set the value as the initial value at the beginning of each test and verify the above during the test execution
The validity of the circuit to be verified is confirmed by the absence of an error indicating a circuit failure .

Further, the circuit to be verified has a flag capable of determining the content of the error, and the monitor section ignores or resets the set state of the flag so as not to malfunction during and immediately after the reset operation of the circuit to be verified. The simulation is interrupted when the type of the flag is set.

In addition to the above simulation model, there is provided an additional circuit dedicated to simulation for performing an error check, and when an error is detected, the monitor is notified and then the simulation is interrupted by the monitor.

Furthermore, MESI (Modify)
d, Exclusive, Shared, Inva
The state of the cache, called
MES that is a write-back cache to state
I-state or MSI (Modified, Share)
d, Invalidated)
Write-back cache with up to three states
A cache system in which the Nth cache includes the N-1st cache, the agent driving the request and response,
A bus connecting the cache system and the agent, a simulation model including a bus monitor connected to the bus and checking a conflict between a bus protocol and a cache state, a test generation unit for generating test data, A monitor unit that performs reset and internal setting of the simulation model, clock supply control and stop control, comparison of expected values after completion of simulation for each test, and determination of test results in accordance with instructions included in the test data. Specify the operating conditions, set the data value for the simulation model as an initial value at the beginning of each test, and make sure that there is no conflict between the cache state detected by the bus monitor and the bus protocol during the test or at the end of the test. It confirms the legitimacy of the operation of the verification circuit as waiting value.

The bus monitor checks the bus transaction of each bus, and for the bus protocol, matches the bus arbitration result with the request issuing agent, inconsistency between the request code and the address range, inconsistency between the request code and the data transfer length, and undefined. A logic simulation method in which a transaction response that is not a code value and whose response cannot be separated, checks for any of these protocol violations, notifies the monitor unit when a violation is detected, and interrupts the simulation by the monitor unit. The bus monitor checks the bus transactions of each bus, checks for a conflict between the cache status value at the time of issuing the bus request source and the request code of the bus request for those bus transactions, and monitors the bus when a conflict is detected. After notification to the coater unit, it is intended to interrupt the simulation by the monitor unit.

Further, the bus monitor checks the bus transactions of each bus, and checks for inconsistency between the cache status value of the bus transaction and the request code of the bus request after a predetermined time from the end of the bus request, for the bus transactions. The simulation is interrupted by the monitor unit after the notification to the monitor unit.

The bus monitor checks the bus transactions of each bus, responds to the bus request for the bus transaction, responds to the snoop result of another agent on the same bus, and caches the request source of the bus request. The inconsistency with the status value is checked, and when the inconsistency is detected, the monitor is notified and the simulation is interrupted by the monitor.

Further, the bus monitor checks the bus transaction of each bus and sends a response defining the final operation of the bus transaction corresponding to the request to a snoop result of another agent on the same bus or a request issuing source. The inconsistency is checked from the cache state value of the above, and when the inconsistency is detected, the monitor is notified and then the simulation is interrupted by the monitor.

Also, a simulation model composed of a bus connecting between the circuit to be verified and the non-verification target circuit, a test generation unit for generating test data, and a simulation model of the simulation model in accordance with instructions included in the generated test data. A monitor unit that performs reset processing, internal setting of the circuit to be verified, clock supply control and stop control, comparison of expected values after simulation for each test, and determination of test results, and specifies operating conditions as operations used for verification. A logic simulation method for setting a data value for the simulation model as an initial value at the beginning of each test and comparing the final value with an expected value at the end of the test to confirm the validity of the operation of the circuit to be verified. Reset the target circuit and the non-verification target circuit for each test. And performs the door processing.

Further, for the reset processing requiring a large number of clocks in the reset processing of the circuit to be verified, a switch that does not perform repetitive processing is provided in the circuit to be verified, or the value of the counter of the repetitive circuit of the circuit to be verified is set to the above value. The monitor section is forcibly changed and a part of the reset processing is performed by the monitor section.

The flags and registers in the circuit to be verified, which are set by the operation sequence using the clock after the reset processing, are set to arbitrary values by the monitor unit.

Further, when the circuit to be verified has an N-order cache, the data value of the N-order cache and the state value of the cache are set to arbitrary values by the monitor unit to initialize the initial state. To set.

When the circuit to be verified has an N-th order cache and the N-th order cache includes an N-th order cache in a processor connected to the bus, the data value of the N-th order cache is The initial state is set by setting the cache state value to an arbitrary value by the monitor unit.

Further, a circuit to be verified having an N-order cache, a circuit to be verified having no cache, a processor which is a circuit to be verified and has a cache of N-1 or less, a main memory which is a circuit to be verified and A main storage control device for controlling main storage, a simulation model including a bus connecting the circuit to be verified with the processor and the main storage control device, a test generation unit for generating test data, A monitor unit that resets the simulation model, sets internal settings of the circuit to be verified, controls clock supply and stops, and compares expected values after completion of simulation for each test and determines test results according to instructions included in the test data;
Designate the operating conditions as the operation used for verification, set the data value for the above simulation model as an initial value at the beginning of each test, compare those final values with the expected value at the end of the test, and compare the final value with the expected value. In the logic simulation method for checking validity, it is preferable that the N-th cache includes the N-l-th cache and that the protocol order is changed when the data write order to the processor appears on the bus. Under the permitted condition, the selection of the address where the write access is performed a plurality of times is separated into a non-shared address area that can be used only once and a shared address area that can be used multiple times, and the non-shared address area is already registered. Is determined not to be selected, and the shared address area is assigned to the non-shared address area. Tested product to select an address that does not, for non-shared address region at the end of the study compared the final value of the cache, the shared address space is not conducted comparison identifying the cache.

Each time the non-shared address area and the shared address area are generated, an address is registered in a table, and the distinction between the non-shared address area and the shared address area is determined on the table.

Further, the non-shared address area and the shared address area are distinguished between shared and non-shared by the bit pattern of the address, or a processor number or a value associated with the processor number is used to generate the non-shared address. It is.

The address is managed by a bit pattern or a range of values constituted by a plurality of bits so that the index value of the N-th cache is exclusive to the index value of the N-first cache. .

Further, each of the N-th caches has a first table and holds a non-shared address so that the index value of the N-th cache is exclusive with respect to the N-first cache. The cache has a second table and a third table, the second table holds a non-shared address, the third table holds a shared address,
If a non-shared address is used, an address having an index value that does not exist in any of those tables is selected, and if a shared address is used, an address having an index value that does not exist in the third table or any of the above tables is selected. Select an address and place the selected address in the third
Are stored and managed in a table.

The address of the read-only or non-change area for the shared address and the address of the changeable area by writing are determined so as to be uniquely determined from the bit pattern of the address, and the address of the request issued by the processor is determined. After that, the type of request is determined by determining whether the area accessed from those addresses is a read-only or non-changeable area or another changeable area, and at the end of the test, the final value of the cache for the read-only or non-changeable area Are compared and the changeable area is not compared.

Further, under the condition that the protocol order is allowed to be changed when the data write order of the processor appears on the bus, different commands of the same processor match the bit width of the bus. At this address, the final value of the cache is compared without writing different data to the same address.

Further, the above processor has a memory write command in a unit of a bit width of 1 / K of the bit width of the data bus.

Further, when the same processor accesses the same cache line with the read or write command to the (N-1) th cache, the address to be accessed is selected only once. To avoid addresses that have already been used.

When the processor issues a request to access the same cache line address, the address range to be written by each processor has a write command in the unit of a bus width as an address matching the bit width of the bus. This is to compare the final value of the cache without writing the same data in units of bus width.

Furthermore, the address range to be written by each of the processors has a bit width of 1 / K of the bit width of the data bus.

Further, when the processor verifies the consistency with the N-level cache of the circuit to be verified by using a request for accessing the N-1 level cache or the N-second level cache, each of the shared addresses is A data value after executing a request is managed for each processor, and a table that can hold a plurality of combinations of cache line addresses related to the shared address and data values constituting the line is used. Each time the data value is generated, the data value is updated and a test is performed. At the end of the test, the status values of the main memory and all the caches are checked, and if valid, the data values are compared.

Further, when the verification target circuit rejects the bus transaction issued from the non-verification target circuit and makes a retry request for prompting the reissue of the request, the non-verification target circuit performs the retry requested transaction. Is requeued at the end of a transaction already queued.

Also, when detecting the contents of the request code issued by the non-verification target circuit or the serialization designation before issuing the next transaction to be issued, it is confirmed that the response of the verification target circuit is not a retry request. Issues a request for the next transaction.

Further, a circuit to be verified having an N-order cache, a circuit to be verified having no cache, a processor which is a circuit to be verified and has a cache of N-1 or less, and a main memory which is a circuit not to be verified. And a main memory control device for controlling the main memory, a bus for connecting the circuit to be verified with the processor and the main memory control device, and a bus monitor connected to this bus for checking a bus protocol, A simulation model having a delay operation setting and a delay operation circuit of a bus protocol in the non-verification target circuit or the bus monitor, a test generation unit that generates test data including an operation delay of the bus protocol of the bus, and the generated test data Resets the simulation model according to the instructions contained in It has a monitor unit that performs unit setting, clock supply control, stop control, comparison of expected values after completion of simulation for each test, and judgment of test results, specifies operating conditions as operations used for verification, and sets data values for the simulation model. At the beginning of each test, it is set as an initial value, and at the end of the test, the final value is compared with an expected value to confirm the validity of the operation of the circuit to be verified.

The circuit to be verified operates in response to a request from the processor to be verified and the internal state of the circuit to be verified is determined in response to a previously received request, and a new request is received. And a new internal state by a combination of the internal state and the internal state,
When a request is generated from the processor by an access command to the primary cache, the request from the processor to the bus is indirectly delayed.

Further, as a command delay condition of the processor, a command designating a delay between commands is inserted, or until the signal value of the bus or a change in the signal value reaches the designated condition, the processor may execute N-1. This delays access to the next cache.

A bus command queue is provided between the N-1 level cache of the processor and the bus,
In the access command, a delay target, a delay condition, and the number of delay cycles are designated in the bus command queue without designating a delay, and the request is delayed when the request is issued on the bus.

Further, after the circuit to be verified issues a request to the bus, the circuit other than the circuit to be verified receives a delayed response from the agent due to the queuing operation of the agents other than the circuit to be verified into the buffer and the overflow state. When a request is issued in response to a signal that suppresses a request depending on the state of the buffer, the buffer size of the agent is set smaller than the buffer size actually used, and the response timing and the request suppression timing are changed.

When the function for setting the buffer size is provided on the simulation model, the function is used. When the function is not provided, the function is set at the time of simulation.

Further, when the circuit to be verified returns a response to a request from the first agent other than the simulation model from the first agent or the second circuit, the circuit to be verified returns a response to the request. The condition for instructing the issuer or the second agent to delay the response cycle is when the queue of the bus pipeline defined by the bus protocol is equal to or greater than a preset value or equal to or less than a preset value. .

When the circuit to be verified returns a response from a request issuing source or a second agent to a request from the first agent other than the simulation model, and the circuit to be verified returns a response, When instructing the original or the second agent to delay the response cycle, the delay operation is applied to a predetermined number of transactions counted from the start of the test on the bus.

Further, when the circuit to be verified receives a response from the request issuing source or the second agent in response to a request from the first agent other than the simulation model, and the circuit to be verified returns a response, When instructing the issuer or the second agent to delay the response cycle, the delay operation is applied when the addresses of the transactions on the bus match.

While the circuit to be verified is processing the first signal on the bus, an agent other than the circuit to be verified waits for a predetermined number of cycles for the second signal on the bus. Drive that signal in the first cycle that satisfies the protocol.

Further, while the circuit to be verified connected to the plurality of buses is processing the first signal on the first bus, an agent other than the circuit to be verified changes the second signal on the second bus. On the other hand, the signal is driven in the first cycle which satisfies the protocol of the signal after waiting a preset number of cycles.

When the circuit to be verified operates by receiving a signal of another agent on the simulation model, all the values that can be expressed by the number of bits of the signal value of the agent are individually or grouped. , The number of cycles for delaying the driving of the signal of the agent is individually designated.

Further, when the circuit to be verified operates upon receiving a request from another agent on the simulation model, when the address of the request issued by the agent matches a preset address, the agent The request is issued after a preset number of cycles.

The operating conditions of the agent other than the circuit to be verified and the signal delay conditions on the bus can be set stepwise so that the first condition is applied and then the second condition is applied. It is.

Further, the bus monitor records the history of signals in transaction units and displays the history at the end of the test or during the test.

Further, an error signal is injected from the non-verification target circuit onto the bus or an error report signal on the bus is driven to cause the verification target circuit or another agent on the simulation model to perform a retry operation. Things.

Further, MESI (Modify)
d, Exclusive, Shared, Inva
The state of the cache, called
MES that is a write-back cache to state
I-state or MSI (Modified, Share)
d, Invalidated)
Write-back cache with up to three states
, A circuit to be verified having an N-order cache, a circuit to be verified having no cache, a processor to be a non-verified circuit, a processor having a cache of N-1 or less, and a circuit not to be verified. A main memory and a main memory controller that controls the main memory, from a bus that connects the circuit to be verified with the processor and the main memory controller and controls the circuit to be verified from outside and investigates the result process A simulation model to be configured, a test generation unit for generating test data, resetting of the simulation model according to an instruction included in the generated test data, internal setting of the circuit to be verified, clock supply control and stop control, and simulation for each test Equipped with a monitor that compares expected values after completion and judges test results. Determined by a combination of specified conditions by a random number and manually operating conditions as operation using the,
A data value for the simulation model is set as an initial value at the beginning of each test, and at the end of the test, the final value is compared with an expected value to confirm the validity of the operation of the circuit to be verified.

Further, when the N-order cache includes the N-first-order cache, and the circuit to be verified operates by receiving a signal of another agent on the simulation model, the operation of the circuit to be verified is performed. The number of cycles to be delayed is determined according to random numbers based on a preset distribution table.

Further, a plurality of the distribution tables are provided, and a distribution table is designated for each delay element.

When the processor performs verification of the circuit to be verified by accessing the N-1 primary cache with read and write commands, an initial value of the N cache is determined by a random number, and In this case, the initial state of the N-1 level cache that can be taken is selected by a random number.

Further, when a request is issued from the processor to the bus, the type of the request is selected by a random number, and the request value is determined according to a random number based on a preset distribution table.

When the processor responds to the bus with a snoop result of the cache included in the processor in response to the request on the bus, the snoop value as the response value is based on a preset distribution table. It is determined according to a random number.

Further, when the non-verification target circuit responds to the request on the bus, the response value indicates whether the request can be accepted, whether or not there is a data transfer, or whether there is a data transfer path or an error. Response The response value is determined according to random numbers based on a preset distribution table.

When a random number is used to determine the index of the cache at the target address of the request issued from within the processor and to determine the way to check the final state of the cache, an identification symbol is assigned to the index and the way that can be allocated. Are determined according to random numbers from the identification symbols excluding the already assigned identification symbols.

Further, when the circuit to be verified operates upon receiving a signal of another agent on the simulation model with respect to the bus, a command or address determined by the circuit to be verified or a response value or delay is determined. A value uniquely determined from the random number is adopted as the cycle number, and the random number is managed or commonly managed by the monitor unit.

The random number is generated by using a random number generation routine managed by the monitor unit.

Further, the random number seed is left as log data of the test result.

Further, a random number generated during the execution of the simulation and a routine identifier using the random number are stored.

Further, the random numbers are generated in advance and stored as data in a file.

A circuit to be verified having an N-order cache, a circuit to be verified having no cache, a processor which is a circuit to be verified and has a cache of N-1 or less, and a main memory which is a circuit not to be verified include: A main storage control device for controlling main storage, a simulation model including a bus connecting the circuit to be verified with the processor and the main storage control device, a test generation unit for generating test data, A monitor unit for resetting the simulation model, setting internal settings of the circuit to be verified, controlling clock supply and stopping, and comparing expected values after completion of simulation for each test and determining test results in accordance with instructions included in the test data; Specify the operating conditions for the operation used for Controls the usage status of entries, controls the usage status of cache entries after clock supply, and the generation of addresses and commands that determine entries, and is unlikely to occur stochastically from addresses or commands determined by uniform random number generation A data value is generated so that an event occurs with a high probability, and a data value for the simulation model is set as an initial value at the beginning of each test, and at the end of the test, the final value is compared with an expected value. This is to confirm the validity of the operation.

Further, when the N-th cache is the N-1
An index of the cache among addresses used as requests by the processor or another agent connected to the circuit to be verified, wherein the processor accesses the (N-1) th cache by read and write commands, and Is determined, and the address is selected by a random number within the limited range.

Further, of the addresses used as requests by the other agents, the type of address bit pattern composed of bits higher than the bit used for the index of the cache is limited, and the address is determined by a random number from the restricted ones. Is to select.

Further, the above-mentioned circuit to be verified has an N-order set associative type cache, and the number of usable ways of the cache or the availability of each way is selected and set.

Further, a command is issued by the processor from the processor to forcibly invalidate the contents of the cache or write back to the main memory, and the circuit to be verified adds or subtracts the internal counter sequentially to invalidate the contents of the cache. When processing the conversion or write-back operation, when the value of the counter reaches a preset value, the value of the counter is forcibly changed to omit the simulation and restrict the use of the omitted address. It is.

Further, the monitor unit or the simulation model substitutes invalidation or write-back for the omitted address by forcibly changing the value of the counter without advancing the clock.

[0114]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 shows a system configuration diagram of a simulator (not shown) for implementing a logic simulation method according to the first embodiment of the present invention. All the components in this block diagram are realized by software, and employ a software simulation model. Reference numeral 1 denotes a bridge circuit model to be verified, which includes a bridge circuit 1a including an N-level cache 1c,
It comprises an N-level cache 1c, a bridge circuit 1b in which its control circuit is separated, and a bridge circuit 1d not including a cache. Reference numeral 2 denotes a processor model including a cache of order N-1 or lower which is not a verification target, reference numeral 3 denotes a main memory model which is not a verification target circuit, reference numeral 4 denotes a main storage control device model, and reference numeral 5 denotes an input / output processor which is not a verification target circuit. , A test generation unit for generating test data, and a reset, an internal setting of a circuit, a clock supply control, a stop control, and a simulation for each test according to an instruction included in the generated test data. A monitor unit 8 for comparing the expected value after completion and judging the test result connects the circuit under test 1, the processor 2, the main memory control device 4, and the I / O processor 5, and performs the verification from outside. A bus 9 for controlling the target circuit 1 and examining the process of the result. A bus monitor which counts and verifies events and events between transactions and has a function of driving an error value to a signal on the bus 8. A bus monitor 10 observes an internal signal of a circuit to be verified and does not exist in an actual product. Is an additional circuit dedicated to simulation that exists only at the time of simulation and performs circuit operations for simulation.

This embodiment is a case where a multi-level (N-th) cache memory is realized, and is described as “(N + 1) -level storage” when the main memory 3 is included. Also,
The N-level cache in this example is MESI (Modified, E
It is premised on a cache of a write-back type having up to four cache states called xcluseived, Shared, and Invalidated. As a method of realizing a multi-level cache, an m-th cache and a k-th cache (k is 1
Is assumed to be in the relationship shown in Table 1 below, that is, "there is an inclusive relationship". When invalidating the m-th cache for replacement, the k-th cache is invalidated forcibly. Shall be performed. In addition to the MESI state, MSI (Modified, Shared, Invalidate)
There is also a cache called d) with up to three cache states, which differs from the MESI state only in that there is no E state, and is selectively used depending on use conditions.

[0116]

[Table 1]

FIGS. 2 and 3 are diagrams for explaining the cache system in the MESI state. FIG. 2 shows the hierarchical structure of the memory in the cache system. The main memory 3, the memory 11 of the bridge 1, and the processor 2 The manner in which the data is stored in the memories 12 and 13 is displayed in black. FIG. 3A shows data stored in two cache lines A and B for each cache line indicating the same address for each hierarchy. FIG. 3B illustrates the inclusion relationship between data stored in the cache lines A and B.

In FIG. 2 and FIG. 3, the cache line A, which is the storage address, is the main memory and the N-th cache.
The bridge 1a including the 11a and the bridge 1b including the N-th cache 11b have correct data A respectively. The N-1 primary storage in the processor 2 is such that the N-1 primary cache 12a, which is inclusive with 11a, is valid, but 13a, which is lower than 12a, has no data and is invalid. 13b shows an example in which each data A is valid. Six of these 3, 11a, 12a, 11b, 12b, and 13b all show the S state. On the other hand, with respect to the cache line B, when the N-secondary cache 13a in the processor 2 is in the M state, it is held as the M state in the upper caches 12a and 11a including the N-secondary cache 13a and does not exist in any other caches and main memories. do not do. Also, as shown in FIG.
In the dirty state, the data C on 12a and 11a is "old" and has no meaning.

Based on FIG. 1, test generation, circuit initialization,
The operation of the first embodiment will be described in the order of test monitoring during operation and termination of simulation. First, as shown in FIG. 1, test generation has functions such as bus operation control, timing control, allocation control, expected value generation / confirmation control, timeout control, random number control, and generation control. The bus operation control determines a request on the bus, a snoop response, a response response, and conditions such as which agent drives those responses and requests. Here, the agent is also called a "transmitting / receiving station" of the bus, and refers to a device, a module, a circuit, or the like that is connected to the bus and issues a request or responds to the request. Specifically, the bridge 1, the processor 2, the main memory 3, the main memory control device 4, the I / O processor 5, and the bus monitor 9 correspond to the simulation model of FIG.

The timing control controls the selection of the delay time of each signal and the constraint relationship of the order and time interval between the signals.
The delay value is managed for each type of request / snoop response / response response, the time between signals over different transactions is determined, and the time between signals over different buses is determined. The assignment control determines which MESI state value is assigned to the cache line, whether the address is duplicated or inconsistent with the already assigned address, whether there is no conflict between the request and the initial state, the index part of the cache (the cache memory set is Duplicate and empty management of the determined address bits), empty management of the initial state of the cache way, and initial setting of the way in consideration of replacement are performed. The expected value generation and confirmation control
Judgment of whether the expected value can be determined by generation conditions or not, generation of expected value that can be determined independently without depending on other transactions, history of other transactions, usage of addresses, and time interval from previous transaction Perform a decision process based on the table information.

In the timeout control, the timeout is detected by assuming a shorter cycle number during the simulation. Therefore, the timeout detection is suppressed or the timeout value is extended depending on the timing control. Random number control controls the use of random numbers to maintain the reproducibility of random number seeds, which are the numbers on which random numbers are generated, and the random number values generated from the seeds, in order to ensure the reproducibility of the test. Is performed, and random numbers are generated for parameters that are dependent conditions that do not achieve the purpose if random numbers are used individually. The generation control determines the number of transactions and the number of clocks to be generated in a test (a set of reset, initialization, simulation, and comparison of the results is called a test) along with other conditions, and determines the number of tests to be generated. The number of generations is changed, the generation conditions are sequentially changed, and the control of changing the random number seed between tests is performed. These processes have a dependency relationship with each other, and the priority changes according to a condition externally specified at the time of generation, and the control application order and the application algorithm change.

Next, a simple example of test generation will be described. In the generation control, the maximum value of the number of clocks and the number of bus transactions are determined from parameters specified externally. In the bus operation control, a probability distribution of each request and a probability distribution of an existing response determined for each request are calculated from externally designated parameters. The request determined by mapping the value obtained from the uniform random numbers to the above distribution. Further, the snoop response and the response response are determined from the distribution table for each request. Specifically, the relative frequency of each signal value is normalized, and the range that each signal value can take is from 0 to 1.
Then, a signal value (request, response, etc.) corresponding to the range specified in the table is obtained from a uniform random number from 0 to 1 from the table. In the example of FIG. 6, if the first random number value is 0.370, B that is 0.25 or more and less than 0.60 is selected as a request from the “request distribution definition”. "Response response distribution definition" from the next random value 0.28
Response value X is selected from the following, and from the next random number value 0.887, "when the value is other than X and A" in the "snoop response distribution definition"
The snoop value n is selected from the table row that satisfies the above condition. The same applies to the case where the following table is created in advance and a comprehensive probability table is obtained by one random number.

[0123]

[Table 2]

Next, the initial state of the cache is determined. The state value of the N-order cache that can be taken for the already determined request is determined from random numbers according to the probability distribution. Further, N-1 within a range not inconsistent with the state value of the N-th cache.
Similarly, the state value of the next cache is determined by a random number according to the probability distribution.

Next, an address and a way to be initialized in the cache are determined. If the state value, address, and way of the cache are separately determined by random numbers, they may not be allocated inconsistently with the conditions obtained for another transaction. A simple way to avoid this situation is to remember the cache information you have already allocated, and when it is determined that it is "used", repeat the random number and repeat until a free space is found. In addition, when an address is obtained by using a random number, the index portion of the cache is restricted so that the index does not overlap with the index of the address used in the generation of the Nth level request and the generation of the (N-1) th level request. A simple example is a cache line size of 32
In B, when the N-1st cache is 64 KB × 4 and the Nth cache is 1 MB × 4, the bits of the address index are 15 to 5 and 19 to 5 respectively. For example, it may be determined that the request is used for the (N-1) th level request. If the N-th level access does not affect the N-1st cache at all, use of any of the bits 19 to 16 for this selection condition widens the range of selection of the N-1th cache.

Next, the state value of the (N−1) -th order cache belonging to another processor connected to the same bus is determined within a range that does not contradict the state value of the N-order cache including the request issuing source and the response response / snoop response value. Choose an address to match. In addition, the N-th cache that does not include the request issuing source and the N-first cache of the processor connected thereto determine the state value of the cache so as not to contradict the N-cache determined in advance. As for the data value, basically all bits may be determined by random numbers.

Next, in addition to the above-mentioned transaction focusing on the bus, generation is performed by N-1 or N-second level access. Determine the storage access address. The N-th level cache index value forming a part of the address is selected so that the index of the N-th cache does not overlap with the N-1 and N-second cache indexes selected here, as described above. The exclusive control may be determined based on the range of the index value or the specific bit value, and the number of transactions used in one test is generally several percent or less of the number of indexes, so that no condition can be found by selection. The above N-1
When verifying the bus operation connected to the N-level cache and the N-level cache operation by issuing a request in the processor 2 to the next cache, a part of the bit of the address of the request issued by each processor 2 It is also possible to generate an address as a value that can be associated with a number or a processor number.

Next, the command of the address to be used for the N-1 or N-second order storage access is determined. Next, the cache initial state of the address used in the N-1 or N-2 order storage access is determined within a range not inconsistent with the command. In the case of the command of the (N−2) th level, the commands are selected in the order of the (N−2) th order, the (N−1) th order, and the Nth order so that there is no contradiction in the inclusion relation. Because the order of execution of commands at this level on the system bus is unpredictable,
A simple method inserts a bit value depending on the value of the processor number having no random number element into a part of the address, and independently determines the initial value of the cache in each transaction. These addresses are called non-shared addresses. A simple example of determining that a non-shared address is exclusive to a shared address is non-shared if a specific bit of the address is 0, 1
If so, it is determined to be shared, and the Nth / N-1th order bits and the processor number bits which are already used are separated. As described above, under the condition that the order of writing the data to the processor 2 appears on the bus 8 and the order of the protocol is allowed to be changed, the selection of the address where the write access is performed a plurality of times is once. It is divided into a non-shared address area that can be used only and a shared address area that can be used multiple times, and it is determined not to select an address that has already been registered for the non-shared address area. A test is generated so as to select an address that does not correspond to the shared address area. At the end of the test, the final value of the cache is compared for the non-shared address area, and the cache-specific comparison is not performed for the shared address area.

An address used for the N-1 or N-2 order storage access and a condition for moving M data between the processors 2 are generated. These addresses are called shared addresses and determine how many such cache lines are used in the test. For writing to the shared address, the byte position to be written is determined according to the processor number and the information indicating the number of times of writing in the same processor. For example, if the cache line is 64 bytes and there are eight processors 2 in the system and the unit of write access to the same line is 1 byte, 1 / K of the bit width of the bus as a short address is 64 bytes /
(8 × 1 byte) = 8, and 8 per processor 2
Write access is allowed up to times. The write data is simplified and determined as processor number × 8 + access number + bits 13 to 6 of the line address. If the access unit is 64 bits of the bus width, it means one time per processor 2.

Although it is easy to distinguish between a shared address and a non-shared address, movement between processors 2 is unlikely to occur stochastically unless the number of shared addresses is considerably reduced. Therefore, the number h of the shared addresses is determined first, and h addresses are previously stored in the table, and the modulo of the random number h is obtained as an entry number in the table. Request generation for a shared address may be performed separately from request generation for a non-shared address, and the order may be changed later so that the processing order is not biased. The generation by the address and the generation of the shared address may be performed in parallel.
The initial state of the shared address cache is the entire system,
The N-th order, the N-th order, and the N-th order cache are determined in this order.

Requests are assigned to the processor 2 or the I / O processor 5 that issues the request, in the order in which they are generated, at which addresses are stored in the instruction storage in the processor 2 or the I / O processor 5. When the request A corresponding to the instruction is "retry-response" for prompting a retry on the bus, the processor 2 reissues the request A to which the retry response has been issued before issuing the bus request B corresponding to the next instruction. Insert a "serialization" instruction between A and B to guarantee order and operate as a whole without inconsistency, or insert "serialization mode start" before A and "serialization mode end" before B The request A is defined as an “instruction requiring serialization processing”. When neither of these is specified, a model of the processor 2 is created so that a processing request is added to the end of the instruction execution queue at the time of executing a simulation, and no special processing is performed at the time of generation. N-1 for no serialization
Since the replacement of the next cache cannot be predicted and the expected value that specified the cache way cannot be generated,
Although it is limited to the expected value for the data value, there is an advantage that various operations can be realized. Both are appropriately selected and used.

The delay processing accompanying the generation of the request includes an N-1 level cache or an N-2 level cache which may generate an instruction or bus request indicating the bus request itself stored in the instruction of the processor 2 or the I / O processor 5. An instruction indicating a delay is inserted before the cache-level memory access instruction. The instructions include waiting for a fixed cycle, waiting for a specified number of cycles, waiting until the specified queue of the pipeline phase queue on the bus 8 becomes equal to or less than a specified value, another specification for which the processor 2 is not connected. Wait until the specified queue of the pipeline phase queue of the bus becomes less than the specified value, count the number of requests that are transactions on the bus 8 and wait until the number reaches the specified value. Another designated bus 8 to which no processor is connected
, And waits until the number reaches the specified value, compares the address corresponding to the request issued on the bus 8 with the specified address, waits for a match, and the processor 2 is connected. A complicated condition can be specified by setting those instructions continuously, such as comparing the address corresponding to the request on another specified bus 8 with the specified address and waiting until they match. Further, during processing of the first signal on the bus 8 as the first bus connected to the circuit to be verified 1, an agent other than the circuit to be verified 1 is connected to a second bus other than the first bus. It is also possible to wait for a preset number of cycles for the second signal, and then set a delay condition for driving the signal when the first cycle that satisfies the signal protocol arrives.

[0133] The designation of "bus parking", which is to be used preferentially in the bus arbitration (bus arbitration), which is the pre-operation of the bus request, can also be performed by designating the start and end with the same command or the bus parking command. Specify the number of bus requests issued after which bus parking is released.

In the delay processing accompanying the request generation, in addition to specifying the delay processing in the instruction storage of the processor 2 or the I / O processor 5 as described above, the delay processing is directly specified in a register outside the instruction storage for each test. , There is also a function to apply the instruction when the instruction occurs as a bus request. Unlike the above method, this function can be applied to requests appearing on the bus 8 without fail, and delay control can be performed more directly. On the other hand, it is necessary to always read data. When the number increases, it is necessary to hold many setting registers, and the model becomes large and complicated. The contents that can be specified are the same as those specified by the above instructions, but the start and end conditions are limited to the start of the test.

More specifically, every bus request waits for a fixed number of cycles, every bus request waits for a specified number of cycles, and counts the number of requests issued on the bus 8 to match only the specified number of bus requests. Wait for the specified number of cycles, wait for the specified number of cycles if the address of the request issued on the bus 8 matches the specified address, and specify the specified queue of the pipeline phase queue on the bus 8 below the specified value Always waits until the specified queue of the pipeline phase queue of another specified bus 8 to which the processor 2 is not connected is equal to or less than the specified value.
Counts the number of requests on the bus 8 and always waits until the number reaches the specified value. Counts the number of requests on another specified bus 8 to which the processor 2 is not connected, and sets the number to the specified value. , The address corresponding to the request on the bus 8 is compared with the specified address, and the system waits until the addresses match. The address corresponding to the request on another specified bus to which the processor 2 is not connected is Comparing the specified addresses and waiting until they match, the number of delay cycles is a maximum of the specified number and a random number based on the specified distribution, etc. Conditions can be specified.

In order to associate a similar condition with another request, information is added or a combination of cooperation with other conditions is determined and defined as separate conditions. In addition, the "bus parking" designation, which continues to be used preferentially in the bus arbitration (bus arbitration) that is the pre-operation of the bus request, can be specified by specifying the start and end by specifying the address and the number of buses, or by bus parking Specify that how many bus requests are issued after the application and that the bus parking is released.

The delay designation to the bus snoop is performed by embedding it in the register of the processor 2 or the I / O processor 5 for each test. The specification method is to count the requests on the bus 8 and, if the number matches the specified value, wait for the specified number of cycles (or the minimum number of response units in the bus protocol) to respond. If the address of the request matches the specified address, it waits for the specified number of cycles (or the minimum number of response units in the bus protocol) and responds. If the request issuing agent on the bus 8 matches the specified agent number, specify it. When the request code indicating the operation of the request on the bus 8 that responds after waiting for the specified number of cycles (or the minimum number of response units according to the bus protocol) matches the specified code, the specified number of cycles (or the bus protocol) The lowest number of response units) wait for a response, the specified queue of pipeline phase queues on the bus is less than or equal to the specified value Made to respond to wait then specified number of cycles or minimum number of response units on the bus Terms) wait till, the number of delay cycles there is such a random number that is based to the maximum Toshikatsu specified the specified number distribution. The distribution is usually based on the distribution table already described.

The response indicating the end operation of the bus 8 is delayed by embedding it in the main memory control device 4 or the register of the processor for each test. The specification method is to count the requests on the bus 8 and, if the number matches the specified value, wait for the specified number of cycles (or the minimum number of response units in the bus protocol) to respond. If the address of the request matches the specified address, it waits for the specified number of cycles (or the minimum number of response units in the bus protocol) and responds. If the request issuing agent on the bus 8 matches the specified agent number, specify it. When the request code indicating the operation of the request on the bus 8 that responds after waiting for the specified number of cycles (or the minimum number of response units in the bus protocol) matches the specified code, the specified number of cycles (or in the bus protocol) Waits for a response, waits for a response, and the specified queue of the pipeline phase queue on the bus 8 is equal to or less than the specified value. And then waits for the specified number of cycles (or the minimum number of response units in the bus protocol) and responds. This is the drive data as seen by the user and responds until the first data can be easily read from the request source. Delay the response, wait for a specified number of cycles after the first data has been driven for the received data as seen from the request source and write data as seen from the self, respond with the written data as seen from the request originator For example, a response is made after waiting for a specified number of cycles since the last data of the received data is driven, and the number of delay cycles is a random number based on a specified distribution with the specified number being maximized. When the circuit 1 to be verified operates upon receiving a signal of another agent on the simulation model, all values that can be represented by the number of bits of the signal value of the agent are individually or grouped. By individually designating the number of cycles for delaying the driving of the signal of the agent, the operation of the verification target circuit 1 can be delayed.

The data transfer delay of the request issuer is specified by setting it in a register (not shown) individually provided in the processor 2 or the I / O processor 5. The specification method is to drive after a fixed number of cycles from the fastest timing defined by the bus protocol. For example, the number of delay cycles to be driven is such that the specified number is maximized and a random number based on the specified distribution is used.

When the main memory control device 4 or the I / O processor 5 returns data in response to a read request, the delay cycle is inserted for the fastest timing determined on the bus protocol by the processor 2 or the I / O processor. Is specified by setting in the register that each has. The method of designation is as follows: the number of cycles relative to the “response response”, and when the address of the request to be transferred is equal to the designated address, the system waits for the designated number of cycles to drive. If the request issuing agent matches the designated agent number, the device waits for a specified number of cycles, and if the request code indicating the operation of the request on the bus 8 matches the specified code, the device waits for the specified number of cycles to drive. The number of delay cycles is set at the maximum value of the designated number, and is driven after waiting for the number of cycles calculated by random numbers based on the designated distribution.

Since the processor 2 has M data in the (N−1) -th order cache in response to the request on the bus 8, the data is transferred to the bus 8 instead of the N-th order cache of the bridge 1.
At the time of the "write-back" process of sending data upward, the insertion of the number of delay cycles with respect to the fastest timing specified on the bus protocol is designated by setting the register which the processor 2 has individually. The designation method is to specify a fixed number of cycles for each processor 2, count the number of “write-back processes” on the bus 8, and wait for the specified number of cycles when the number matches the specified value to drive the bus 8.
If the address of the "write back" process matches the specified address, it will wait for the specified number of cycles to drive. The number of delay cycles is the maximum number specified, and the number of cycles calculated from random numbers based on the specified distribution Wait and drive.

When the main memory control device 4 or the I / O processor receives and processes read or write processing, it performs an address request code
There is a “request suppression signal” that stores a requesting agent number or the like in a buffer, but suppresses a new request due to the requested operation, processing speed, or another process. The conditions for driving the signal are set in the registers of the main storage controller 4 and the I / O processor 5 for each test. The setting method is to drive when the read buffer overflows (or may overflow) for a read request, to drive when the write buffer overflows (or to overflow) for a write request, or to read. Make the size of the buffer a specified size smaller than the size of the model, make the size of the write buffer smaller than the size of the model, and drive it when the address of the request on the bus matches the specified address. Separately specifies the buffer size corresponding to the end condition in order to have hysteresis characteristics without making the threshold values of drive start and drive end the same, calculated from random numbers based on the specified distribution with the specified number maximum and maximum Buffer size is smaller than the buffer size actually used Driven and, irrespective of the value is greater than (or less than) the specified value determined from random use state of the buffer during driving, and the like.

In addition to the above, the driving condition of the “request suppression signal” by the bus monitor 9 to be set by setting it in a register (not shown) in the bus monitor 9 is specified. When the designated queue of the pipeline phase queue on the bus 8 is equal to or greater than the designated value, the drive is performed until the designated queue becomes equal to or less than the designated value. Or when it is small).

For an Nth cache level bus operation, the expected value is determined by the contents at the time of generation of the bus request. Specifically, in the write instruction from the processor 2 to the main memory 3, the address and data value initially set in the buffer in the processor 2 correspond to the address and data value in the main memory 3, and some bits of the bus width When writing only, the byte position indicated by the write byte information initialized in the processor 2 is to be compared. In the write operation from the processor 2 to the I / O processor 5, the target to be inspected is I
The same is true except for buffer storage in the / O processor 5. In the read instruction from the main memory 3, the data value initially set in the main memory 3 corresponding to the address specified in the buffer in the processor 2 is stored in the buffer in the processor 2.
-Check that the data is stored in the L1 cache. In this case, it is difficult to predict which way has entered in the inspection of the N-th cache, and all the ways are designated as search targets. In the read operation from the processor 2 to the I / O processor 5, it is checked that the data is stored in the buffer in the processor 2.

In the operation at the level of the (N-1) th cache level or lower, the result remains at the moment when the operation is performed, but cannot be directly checked after that due to the influence of other operations. Specifically, a read operation is performed on the N-1st cache, the N-1st cache makes a miss, accesses the Nth cache, and also makes a miss, and the main memory 3
, And even if data is once stored in the Nth and N-1st caches, it may disappear from the cache as a replacement target by a later operation. Therefore, the buffer in the processor 2 in which the result of the read operation is stored is set as the inspection target, and the cache is not set as the inspection target. In the write operation to the N-1 primary cache in the processor 2, data is read into the N-1 primary cache once and the value of the buffer of the processor 2 is written into the cache. The data is written back to the cache and written back to the main memory 3.

Accordingly, the monitor unit 7 is provided with a process for inspecting “the value of data viewed from the world of the program”, and while judging the state of each cache, the contents of the main memory 3 or the cache having the correct data are expected. Compare with value. At that time, if an instruction to rewrite the same cache line as a whole is issued by each processor 2 or is issued a plurality of times even in the same processor, only the result of the last executed instruction is checked, so the "word" to be rewritten in instruction units And bytes are changed, and the value is set as the expected value.
There are a method of merging all the bit information of the same line and checking at once, and a method of using a byte position mask or instructing a word-by-word comparison while avoiding the complexity of expected value generation.

The comparison of the expected value is generated based on the above idea,
For the monitor unit 7, the comparison target (which cache or buffer), comparison target address (cache address, buffer address), accompanying information (cache way, etc.), its value (cache state value or data value) ), An expected value composed of mask information is given. Also, a reference number at the time of generation is given as analysis information at the time of mismatch, and the number is left in the analysis list.

In the test of the error function, the bus monitor 9 and the register in the circuit 1 to be verified are to be inspected, and instructions are given in the same manner as described above.

Next, the execution of the simulation will be described. The simulator is started separately from the generation of the test data described above.
The connection information between the gates of the non-verification target circuit, the operation description of the non-verification target circuit, the operation description of the monitor unit 7, and the connection information indicating these relationships are read to construct data in the simulator. The test generator 6 is a process which is expressed by a simulator operation description and is performed as a logic simulation, another software process which does not use a simulator, and which is expressed by a simulator operation description but operates on another computer, and operates on a different computer. It is configured to be able to take any one of the methods of synchronizing with the simulation in intercommunication.

After the initialization of the simulator itself is completed, the initial value of the signal of each circuit is evaluated, and after that, the control is transferred to the monitor unit 7. The monitor unit 7 first performs an initialization process common to each test. A reset is supplied to all circuits, a process that takes a long time for initialization like the value of the RAM in the main memory 3, a reset or initialization process that requires a large number of clocks for initialization, a reset and power-on for the circuit to be verified 1 When there is a distinction between resets, there are power-on reset processing, random number initialization processing, and initialization processing such as test pass status management.

Next, the monitor section 7 reads the test information.
Specifically, read the list of files separated for each test,
It is an operation such as reading a file specified indirectly in the list. A file describing a test according to the data is opened, an instruction to the monitor unit is stored in a memory array (not shown) in the monitor unit 7, and after the file is closed, the following execution is performed and the next test is performed. . Tests are performed until all tests have been executed, the number of test failures exceeds a certain threshold value, or an interrupt condition such as when a fatal error is detected is detected, or an end condition due to an external factor such as an end time is encountered. Keep running.

At the beginning of the test, a reset process is performed. Basically, the monitor unit 7 generates a reset signal and performs the reset signal over a plurality of cycles. It is desirable that the reset does not depend on the operation history of other tests.Therefore, reset the non-verified circuit and the verified circuit, and fail in the previous test to reset a small part of the circuit regardless of the simulation model state. Except to be initialized. However, if the verification target circuit 1 includes a circuit that initializes over a long period of time using a counter, it requires a much larger number of clock cycles than the number of cycles required for the original test, which takes a long simulation time.

For the purpose of avoiding this, as shown in FIG. 7, the output signal 11 of the counter in the circuit 1 to be verified is output from the monitor unit 7 when the match condition is generated with the match detection circuit 12 in the circuit dedicated to simulation. As shown in the timing example at the lower left of FIG. 7, the counter value is forcibly changed to another value in the middle by using the coincidence detection circuit 12 forcibly changing the data input value 14 of the counter from the signal 13 (in this case, 25 at 2
In place of 3), the reset processing is realized with a small number of cycles. Further, since initialization corresponding to 3 to 252 in this example is not performed, the value of the corresponding register or the like in the operation description started by the monitor unit 7 or the coincidence detection circuit 12 is not consumed without using the clock. Initialize to Further, the initial state can be realized at high speed by setting the flags and registers in the circuit under verification 1 which are set by the operation sequence using the clock after the reset processing to arbitrary values by the monitor unit 7. It is also possible.

At the beginning of the test, as a part of the reset process, the register and the memory of the non-verification target circuit are initialized within a single cycle or within a clock of several cycles. A buffer for storing data and a response received by the processor 2 as a non-verification target circuit from the bus 8 is also initialized.

Next, the data of the main memory 3, the address and the state value of the (N-1) -th primary cache, and the address and the state value of the N-th cache selected as the initial values by the test generator 6 are individually set. If the state value of the N-1st cache and the Nth cache is “S state” or “E state”, the same value as the main memory 3 is set. When the N-1st cache is in the "M state", a correct value is set in the N-1st cache and erroneous data is intentionally set in the Nth cache and the main memory 3. When the N-1st cache is other than the "M state" and the Nth cache is the "M state", only the main memory 3 is set to erroneous data. These “wrong data” do not mean errors in parity or ECC data, but mean “data patterns are different”.

N instead of N-1st level storage access
In the test for directly issuing the next level bus command, N
When the next cache is in the “S or E state”, the N main cache 3 is accessed by intentionally setting the main memory 3 to an incorrect state.
For example, by setting the main memory 3 correctly and setting erroneous data in the N-th cache and testing a cache bypass instruction, a data value that is intentionally different depending on the purpose is set to facilitate detection of an operation failure. When the state value of the N-th cache is "I state", the address can be set intentionally to test whether the state is correctly reflected. The set as described above is stored in the storage level, location, cache way, address, state, The data is specified individually or in an integrated expression. The monitor unit 7 directly converts the data structure or a file into a data structure of the simulator once, decodes the information to be set in order, and determines a set target and a value to be set. The monitor unit 7 calls an access routine prepared for each object to be set, and the access routine sets a specified value to a variable on the simulator corresponding to the storage.

Processors 2 and I as Non-verification Target Circuits
/ O processor 5 has an N-th storage level command, N-
The primary-level commands, trigger conditions indicating their issuance timing, and delay information are set. This information is created by the test generator 6 in a series of data or a format in which an address and data are paired, and is set via an access routine.

The snoop response, response response, and the like determined by the test generator 6 are set in the non-verification target circuit and the bus monitor 9 via the access routine together with the response delay value and the application condition or trigger condition. If not set, the default value is used.

The bus monitor 9 is set with various timeout values determined by default and the values when the error condition of the bus signal is changed for each test. As the test end detection condition, a variable in the monitor unit 7 is set.

As described above, the setting of the initial condition in addition to the reset value is completed, and the monitoring operation of the simulation is started. The monitor unit 7 instructs “operation start”. This instruction may be issued directly by the test generator 6 or may be started implicitly. From this “operation start” to “end condition detection” or “interruption condition detection”, the monitor unit 7 outputs a signal of the bus monitor 9, an abnormal condition detection signal added to the test target circuit 1, and an abnormal condition driven by the non-verification target circuit. Continue to supply the clock while monitoring the detection signal. As for the end condition, the monitor unit 7 determines the “end state” output from the non-verification target circuit, and the non-verification target circuit and the state machine of the verification target circuit 1 enter an idle state, and the results of all operations are reflected in the memory. After that, the clock is stopped by the "end condition".

The bus monitor 9 performs an error check as shown in FIG. That is, the rules between signals in each transaction specified by the bus protocol are checked. For example, in FIG. 4, the minimum interval of the drive timing between the two signals, the maximum value of the interval between the two signals, the check 20 of the order of driving the signals, and the like. Also, in one transaction and another transaction,
Check the spacing between identical signals 21, the spacing between different signals. The check 22 for the inconsistency between the cache state at the time of issuing the request source and the request code is performed by the bus monitor 9 calling the function of the simulation monitor based on the address received from the bus and the signal indicating the source at the time of receiving the request. Check the cache state of the request source and if an inconsistency is found, an error occurs. The bus monitor 9 checks the bus transaction of each bus 8 and matches the bus arbitration result with the request issuing agent for the bus protocol, inconsistency in request code and address range, inconsistency in request code and data transfer length, undefined code. A check is made to determine whether any of these protocol violations, which is not a value, and a response whose response cannot be separated, or any of these protocol violations, is notified to the monitor unit 7 when a violation is detected, and then the monitor unit 7 interrupts the simulation.

Further, the bus monitor 9 checks the bus transactions of each bus 8, and finds inconsistencies between the shake hand signals between the N bus transactions and the bus transactions that have already been issued for these bus transactions. Checks for any of the following: pipeline overtaking, response signal timeout, detached bus transaction response transaction omission, detached response transaction overtaking original transaction, overflow of each pipeline stage, protocol violation Then, after the violation is detected, the monitor 7 is notified and then the simulation is interrupted by the monitor 7. Also,
After saving the bus request and receiving the end of the bus transaction, after waiting for a fixed cycle as a fixed time, check the cache state of the request issuer by calling the simulation monitor function as shown in 23 and if there is an inconsistency, an error And If a snoop response or a response such as 24 or 25 is received on the bus, the request code or a response inconsistent with the request code and the cache state at the time of issuing the request source is regarded as an error. Also, the signal on the bus is sampled at a predetermined clock edge as a stable timing, and "1",
If the value is “undefined value” expressed by a ternary simulation consisting of “0” and “undefined value”, an error is generated as indicated by 26.
Similarly, a high impedance value is regarded as an error when the signal is sampled as a meaningful signal value. Further, when a plurality of agents simultaneously drive different values for the signals on each bus 8 to the buses, the bus monitor 9 checks the signal values on the simulation model for indefinite values or abnormal signal strengths. After notifying the monitor unit 7 at the time of detection, the monitor unit 7 interrupts the simulation.

For a signal having a redundant bit such as a parity or an ECC code, the signal is sampled in a meaningful cycle and at a clock edge, and if the data is invalid data, a check 27 is performed to determine an error. Such error check conditions are set to be individually suppressed at the time of generation at the time of “error processing” verification. Also, when there is a possibility that the timeout value is insufficient with the specified value, the test generation unit 6 appropriately sets the timeout value. Also, after an error in the previous test, the state may remain at the start of the next test, so these errors are detected during the period from the start of the test to the end of reset plus a fixed cycle. Is suppressed by the bus monitor 9 by a signal from the simulation monitor. The detected error is transmitted to the monitor unit 7 as an abnormal condition, and the monitor unit 7 interrupts the simulation.

Also, as shown in FIG. 5, when the monitor unit 7 checks the error detection signal 30 provided in the circuit under test 1 every cycle and reaches a value indicating an error, or when the signal indicates an “undefined value”. The test is aborted as an unexpected error when When testing for error detection, check is suppressed for each LSI driven by the error signal, and only unexpected errors are picked up as abnormal conditions. The verification target circuit 1 includes a flag that can determine the content of the error.
The monitor unit has means for ignoring or resetting the set state of the flag so as not to malfunction during the reset operation of the circuit under test 1 and immediately after the reset operation. When the type of the flag is set, a simulation is performed. Interrupt.

As shown in FIG. 5, an additional circuit dedicated to simulation 10 as an error check circuit which is not originally included in the circuit under test 1 is added to the outside to find inconsistencies in operation. Specifically, there are inconsistent conditions such as a flag register and an illegal transition state of a state machine. In addition, a signal (not shown) indicating “test completed” is received from the monitor unit 7, all designated flags in the circuit under verification 1 are checked, and it is checked that the circuit has returned to the idle state. Then, the simulation is interrupted by the monitor unit 7. Here, the monitor unit 7 may check all of the designated flags in the circuit under verification 1 to check that it has returned to the idle state.

Thus, the monitor operation is completed, and the inspection of the result of the test is started. The values of the register, buffer, cache, and main memory 3 specified by the test generator 6 are checked. As for the cache, the result of the execution of the command at the Nth level is specified by the way and the state value is compared in detail. As for the result of the execution of the (N-1) th level command, if the state is S or E, the data value is compared for all the caches using the address as a key. In the case of M, the data value is checked only for the lowest cache having the M state, and the data values of the other caches having the M state are not compared. As for the main memory, the data value is compared if the Nth order is other than the M state. For the above comparison, if the mask is designated by the test generation unit 6, an AND operation is performed between the mask value and the value to be compared, if not, and whether the comparison value matches the comparison value if there is no designation is checked. If they do not match, that fact is output to a file and the error count for each test is incremented by one.

Even if there is no error and there is no inconsistency in cache and memory values, there is a problem that "performance is reduced". This may cause an error in the retry or other conditions and cause unnecessary movement. If such a defect is detected, the bus monitor 9 counts the number of transactions on the bus 8 and calculates this value. Compare with expected value. In addition, even if the number of transactions is the same, extra operations may occur at the level of the number of clock cycles and the performance may be degraded. The number of cycles is counted, read at the end of the simulation, and compared with the expected value.

If the end of the test simulation is based on "abnormal condition detection" instead of "end condition", the detection source outputs the fact to the file via the monitor unit 7, while the monitor unit 7 increments the error count by +1.

As described above, the execution of one test is completed. In the test management of the monitor unit 7, the pass / fail of the test is recognized by looking at the error count. Is incremented by 1, and when the result exceeds a predetermined value, the execution of the next test is stopped and the entire test is terminated. If not, proceed to the next test. When all tests are completed, the simulator is notified and the simulation is completed.

Embodiment 2 In the internal system of the simulator for performing the logic simulation method shown in FIG. 1, the test generation unit 6 performs various controls such as management of shared addresses and non-shared addresses, management of shared addresses, and management of final data values. In order to perform unified processing, information on all used cache line addresses is stored in a table, and when a new request for a non-shared address is generated, an address that is not in the table is selected, and a new request for a shared address and a new address is selected. Select an address that does not exist in the table at the time of generation, select an arbitrary address from the group of addresses existing in the table when generating a new request for an existing address with a shared address, and write a value to the entry on the table for a write request Will be updated.

Further, although the test coverage is slightly lowered,
For the shared address, a command that is a write-related but does not change the value may be prepared in the processor as a request, and the determination of the expected value of the data may be simplified and tested. In that case, if the operation does not hang, the purpose of the test can be almost achieved. That is, the address of the read-only area for the shared address is determined so as to be uniquely determined from the bit pattern of the address, and after the address of the request issued by the processor 2 is determined, the area accessed from those addresses is the read-only area or The type of the request is determined by determining whether the area is a changeable area other than the above.

Further, although the test coverage slightly decreases,
By prohibiting requests from the same processor to the same address in the same test for shared addresses,
Complexity such as control of serialization of instruction operation is eliminated, and test generation is simplified.

In order to enable the mixture of the access of the N-th cache level and the access of the N-1th cache level, the test generation unit 6 exclusively sets the address bits corresponding to the index value of the N-th cache in each access. However, this is not a simple distinction as in the first embodiment, but a table is provided for each of the access address of the Nth cache level and the access address of the N-1th cache level. All bits or a portion corresponding to an index may be recorded in a table, and an address may be selected such that an index value generated by another access is not used. Also, instead of these two types of tables, make a table containing several types of information, check if the address selected by random numbers does not collide with the index already used for other access, and reselect it if it collides But it is good.

When a signal on the bus 8 is delayed, various conditions cannot be generated unless the behavior of a signal serving as a delay element changes with time. A plurality of fine-grained conditions as described in the first embodiment may be individually specified for the same signal. By doing so, it is possible to efficiently generate a test in which the timing is variously varied around a certain condition where other conditions are fixed. In addition, the verification target circuit 1
The operating conditions of the agents other than the above and the delay condition of the signal on the bus 8 can be set stepwise so that the first condition is applied and then the second condition is applied, so that the test under more various conditions can be performed. Can be implemented.

Although the delay value used in the test generator 6 is basically used by designating a random number and a distribution constant, a plurality of random number distribution tables may be provided for a certain delay item. One example may be to increase the probability of plausible behavior tailored to real-world behavior, even within a single test. There are two elements, for example, requests are r1 and r2, snoops are s1 and s2, and if the frequency is determined individually for each, it will be 50%, but r1 / s1 is 40
%, R2 / s2 is 40%, r1 / s2 is 10%, r2 /
Even if s1 is set to 10%, unless the combination can be specified, all of them are biased unless they are set to 50%. As a result, the specific gravity becomes 25%, 25%, 25%, and 25%. It is wasteful.

Therefore, if the random number distribution can be defined under individually customized conditions, the generation becomes complicated, but the simulation efficiency is improved. The same applies to the random number of the delay value used by the simulation model at the time of executing the simulation without specifying it in the test generator 6. The second point is
Test generation and simulation are performed while switching a plurality of random number distributions prepared for each test. It is a function necessary for a method of licking uniformly, rather than sequentially performing multiple conditions that specify test conditions, as soon as one of the errors occurs when you want to make a pass / fail judgment It is effective when you want to interrupt the test and is effective when you want to know the result as soon as possible.

When the circuit 1 to be verified uses a cache of the set associative system and performs pipeline processing, the control of the coincidence of the addresses becomes complicated and an address or an index corresponding to the index of the RAM of the cache tag for determining the set is determined. A part of the same accesses interfere with each other to cause a problem, and the operation is often deliberately deliberately deliberately processed, and thus behaves differently from other conditions. Further, in order to cause a cache line replacement operation, it is necessary to increase the frequency of access to the same set. Although the actual probability is a probability of 1/100 to 1 / tens of thousands, it is empirically known that it occupies more than half of the verification condition in terms of the difficulty of operation. Therefore, in order to improve the probability of verification, the index value is limited, and the index value is determined using random numbers.

For example, when the index of the tag RAM is 16 bits, if 20 bus transactions are generated per test, the probability that the transaction of the same index appears in the same test is approximately 20 /.
65536, which occurs only once in 3,000 pieces, and the probability of mutual influence is close to zero. Therefore, if the number of index values used in the test is limited to 10, the same index will appear twice on average per test. Further, considering the timing conditions that affect the operation, about 1/3 of the index matching conditions Can be made. As a specific processing at the time of generation, the index values are limited to 0 to 4 and 65531 to 65535, and are limited to 10 bits.
Is fixed to 010101010110 of a binary number and limited to 16 which can be generated from the remaining 4 bits.
Individuals are selected, registered on a table, and which of them is selected is further determined by a random number. In this way, the bit pattern of the address that determines the index of the cache among the addresses used as requests by the processor or the other agent connected to the circuit to be verified is limited, and the address is selected by a random number within the limited range. Thus, a complicated operation corresponding to each set can be realized with a high probability. Further, the type of the address bit pattern in the upper part of the cache index may be limited.

It is also assumed that simply limiting the index value may cause an excessively high index matching operation ratio to be biased. At this time, the operation is diversified by instructing the test generation unit 6 in advance on the probability of index match and mismatch, and selecting a restricted index value only during match control.

In addition, when a shared address is selected as described in the first embodiment, if a random number is simply used, an address match cannot be stochastically generated. Therefore, if the pattern of the upper part of the address is restricted in accordance with the restriction of the index, the probability of accessing the same address is dramatically increased.
The method of restriction is to fix the bit pattern of most bits, to reduce the range of the value represented by the bits, to obtain the bit pattern of the upper address part of the address by a limited number of random numbers in advance, and to use any of the random numbers Decide.
In addition, all bits of the shared address are determined in advance by a limited number without performing independently of index control,
It is possible to control the frequency more directly by first determining which address is to be generated according to the frequency of the shared address or the non-shared address by using a random number, and selecting a shared address from among predetermined ones.

Further, if an attempt is made to verify cache line replacement processing or access immediately after eviction by replacement, a set-associative cache having four or more ways has a low replacement frequency and is not suitable for testing. Therefore, the frequency of occurrence is increased by limiting the number of ways to two or one using the way reduction function of the non-verification target circuit or the verification target circuit. If a degeneration function is provided for each line instead of for each way, it may be used. Increasing the replacement frequency by selecting the number of ways that can operate in this manner is also effective in improving test coverage including probability.

As transactions appearing on the bus 8, all transactions in the cache are invalidated, and all entries in the cache are written back to the main memory 3 for all entries in the M state. Need a number. In such an operation, if the operation for one entry is verified in the single operation, the other operations are the same. In terms of combination with other transactions, if the first processing, the last processing, and the intermediate processing are realized, coverage can be achieved as verification, but processing all entries takes a lot of time, and this processing and There is a problem that a coverage omission which does not verify a combination condition of other processing remains. Therefore, the value added to the output signal 41 of the counter changing the position of the entry in the circuit to be verified shown in FIG. 8 is monitored, and when the value becomes 4, the next value of the counter becomes 65532. , The counter value is forcibly set to 65531, and 0, 1, 2, 3, 65532, 655
Only eight entries of 33, 65534, and 65535 are to be verified and the simulation is omitted. At this time, the use of addresses is restricted so that cache entries corresponding to index values 4 to 65531 are generated so as not to be filled or are not compared. By doing so, coverage can be expanded in a short time.

In addition, the above-mentioned restriction, that is, generation or non-comparison of a cache entry corresponding to a skipped index may be relaxed. More specifically, a determination is made as to whether the cache is in state M with respect to the entry skipped by the counter. In the state M, it is determined whether the N-order cache is correct or the N-1st cache is correct. Then, the monitor 7 writes the data to the main memory 3 and invalidates the N-th and N-th primary caches for the entries skipped by the counter without consuming the clock. By doing so, it is possible to remove the restriction and prevent a decrease in coverage due to the restriction.

In the test generator 6, the address and the cache
When the way is determined by subtracting a random number, when the bit value that determines a part of the cache index, way, and other addresses corresponding to the obtained value is already “used”, as in the first embodiment, “empty” Instead of continuing to pull the random number until finding "," manage the number of "free" in the table that can manage the index, way, etc. by the identification symbol, and decrement by 1 each time it is used, and always grasp the remaining free The value corresponding to% of the random number value may be calculated with the entire vacancy as 100%. Specifically, counting is performed while skipping the used value, and a corresponding count value is obtained. The number of ways is 8,
An example in which ways 0 and 2 have already been used is as follows.

Assuming that the result of calculating the random number value is 0.42,
6 × 0.42 = 2.5
It becomes 2, and the third empty one (think of 1 origin) will be used. As the used table is counted from way 0 to way 7 to see if it has been used, the count becomes 0 because way 0 is used.
As it is, way 1 is empty and thus 1 is used, and way 2 is already used because it is already used. Here, the value to be assigned is 2.52, which corresponds to the count value 3. Therefore, way 4 is selected.

Using such a method, a solution is obtained in a fixed processing time without unnecessarily drawing random numbers, and the generation processing time is determined. This method has the effect of shortening the generation processing time, especially when conditions that limit the number of addresses to be used are used and the number of bus transactions executed in one test is large. Similar processing is performed on the index and other bits.

Conventionally, it is possible to determine various parameters by using random numbers and find the defect by simulation, in the same manner as the effect of debugging a logical defect on a real machine. At that time, the test data that normally operates is discarded, and the test data that causes the operation failure is left for a reproduction test. However, even if the generation and execution are automatically repeated, test data of operation failure accumulates, and if the analysis work cannot be completed in time, the data amount of the disk increases. In order to improve it, "Generation instruction information" is a routine that uses random numbers that do not include random number elements.
If the "random number information" used is left in the simulation execution log, it can be reproduced. For this purpose, the “number of random numbers” generated before setting the seed and before generating the test may be left in the log. Further, the random number obtained at the beginning of each test may be reset as a new “random number seed”, and the random number may be generated after recording the value in a log. By doing so, test data can be reproduced based on the data.

In the case of performing a simulation using random numbers, if detailed conditions for operation delays and values are determined at the time of test generation and the simulation model receives and implements them as data, it is easy to understand in terms of analysis, but has poor function expandability. Therefore, if each agent in the simulation model calls and uses a random number without permission, it becomes easier, but it becomes difficult to reproduce the test. Specifically, in the event-based evaluation at the same time, if the operation of each agent or simulator is slightly changed, the actual evaluation order of the simulator is often not guaranteed, and it is difficult to reproduce. Then, the monitor unit 7 manages the random numbers collectively, and the agent who wants to use the random numbers calls the function of the monitor unit 7 to receive the random numbers, and the monitor unit 7 performs the serialization of the events and generates the random numbers without the adverse effect. be able to. A random number generation routine is used for the random number generation. Alternatively, the test generation unit 6 may create a random number table in advance before simulation without the monitor unit 7 generating random numbers, and the monitor unit 7 may manage only pointers to the table.

If a data file in which random numbers are tabulated is prepared and random numbers are not generated at the time of simulation, the random numbers change depending on the computer, operating system, and library on which the simulator operates, thereby avoiding the problem that the random numbers cannot be reproduced. There is also an advantage that can be done. In addition, random numbers are stored as data in a file. A random number is converted into a data file, and only some of the random numbers are changed manually or with a simple tool based on test data that has detected a malfunction. Can be comprehensively tested, so that manual testing can be easily enhanced.

When the random number is collectively managed by the monitor unit 7, the user of the random number and a routine using the random number and the random number value are recorded as a log for the random number, thereby checking the random number bias or checking the random number. It is possible to easily debug a mistake in the use of a program. Also, when determining whether errors occur in the simulation model due to the revision of the simulation model, etc., the same test is performed in addition to the filing of the random number data, and the final value after simulation matches. If the logs of the random numbers are confirmed to be the same, it is possible to easily confirm the maintenance of equivalent functions without functional deterioration and to judge the difference in operation due to correction, and to maintain the quality of the simulation model.

Each bus 8 has a buffer corresponding to each bus transaction and a field corresponding to a pipeline phase. While monitoring the signal operation on the bus 8, it is determined which transaction the signal belongs to. Stores the signal value, the relative clock number from reset indicating the time at which the event occurred, and the clock number difference from the shortest response timing. Stores data values. Then, at the start of the test, initialize a plurality of pointers corresponding to the pipeline phase of that table,
When each signal changes, the pointer of the pipeline phase is incremented by 1, and when an error occurs in the test, the data of all entries is dumped to the simulation log.

In this way, when the final data in the main memory 3 or the cache has a comparison error with the expected value, the data value of the cache line address is looked up for each transaction, and the result of any transaction It is possible to ascertain whether the data has gone out of order or which bus transaction has gone wrong because the result of the bus transaction cannot be reflected in the bus transaction. Further, even in the case of a contradiction error that does not result in a data comparison error, the operation of the transaction that triggered the operation failure can be specified, and the analysis work is accelerated. In particular, in the case of a pipeline bus, without such a function, it is necessary to look at the signal waveform over all clocks from the time of reset to the occurrence of a malfunction, and the effect is great.

For hardware performing complicated operations,
Factors such as retries can often occur with high probability under conditions that are unlikely to occur in normal operation. Therefore, such a condition is generated by driving an error signal for prompting a retry process with a certain kind of error or forcibly driving a retry response with a bus transaction response response.

The logic simulation method according to the present invention described above uses a magnetic tape, CD, F
It can be stored in a portable recording medium such as a D sheet.

[0195]

As described above, the logic simulation method according to the present invention provides a simulation model environment in which the bus request operation of the Nth cache level and the N-1st cache level request connected to the circuit to be verified can be executed in a mixed manner. Since it is configured to perform verification using various parameters based on random numbers, the following effects can be obtained.

By using the error check circuit, the coverage for detecting a malfunction can be expanded.

Further, the non-shared address which can be easily determined only once and the shared address which can be accessed a plurality of times are managed separately, so that the coverage of the non-shared address is expanded.

Further, by using N-1 primary cache level requests with few restrictions on test generation of shared addresses and managing the address bits corresponding to the cache index, mutual interference with the Nth cache level requests occurs. Test coverage was not reduced.

Further, since the access to the same address can be determined by checking the final value of the data, the test coverage for the same address is improved.

Furthermore, by giving various conditions to the delay operation of various response signals including the request operation, the test conditions are diversified, and the controllability can be improved even though the test is generated using random numbers.

The random numbers used for the bus operation, cache state, and signal delay are individually specified by the random number distribution or by controlling the range of address bits specific to the cache. As a result, the efficiency of the test using random numbers can be improved.

Furthermore, the simulation time can be reduced by controlling the circuit to be verified so as to skip the reset and time-consuming processing, and by causing the monitor unit to perform the initial setting of the cache which has been performed for the condition setting. did it.

Further, by enabling the reproduction of random numbers and adding an analysis support function, it is easy to isolate a defect and expand the test to the same test as the analysis work.

[Brief description of the drawings]

FIG. 1 is a circuit to be verified, a circuit to be verified, a bus having a significant meaning in a verification operation, a cache memory, a main memory, and a bus scattered on each circuit, which constitute a simulation model according to Embodiment 1 of the present invention. FIG. 4 is a connection relationship diagram showing a monitor, a test generation unit, and a monitor unit.

FIG. 2 is a block diagram showing an inclusion relationship of caches at each level on a simulation model according to Embodiment 1 of the present invention;

FIG. 3 is a block diagram showing a setting example for increasing test coverage in a simulation of a cache at each level on a simulation model according to the first embodiment of the present invention;

FIG. 4 is a diagram illustrating a bus signal on a simulation model according to the first embodiment of the present invention, in which a bus signal protocol violation, a signal protocol violation (or inconsistency) between bus transactions, a bus request and a cache state corresponding to the address thereof. Inconsistency, inconsistency between cache state and request after completion of bus transaction, inconsistency between bus snoop response and other signals and states, inconsistency between bus end response and other signals or states, expressed by simulator at sample timing FIG. 9 is an explanatory diagram showing an operation of checking whether there is an abnormal state such as an undefined state other than 0 or 1 and a signal having a redundant code being an incorrect value state.

FIG. 5 shows an error detection signal originally included in the circuit to be verified on the simulation model according to the first embodiment of the present invention, which is added to the circuit to be verified in which the simulation monitor monitors the signal and sets the stop condition. FIG. 11 is a block diagram illustrating a method of stopping a simulation based on a result of an inconsistency check circuit or a flag idle check circuit that does not actually exist.

FIG. 6 is a classification diagram showing control of a probability distribution when a request is generated on a simulation model according to the first embodiment of the present invention. FIG.

FIG. 7 is a timing chart showing a circuit added exclusively for simulation in order to reduce the number of reset processing cycles on the simulation model in the first embodiment of the present invention, and a timing chart showing the operation thereof.

FIG. 8 is a timing chart showing a circuit and a monitor unit added exclusively for simulation in order to reduce the number of write-back processing cycles of the N-th cache on the simulation model according to the first embodiment of the present invention, and the operation of the monitor unit; FIG.

FIG. 9 is a configuration diagram showing an entire simulation model of a circuit to be verified, a peripheral circuit not to be verified, and a test generation unit in the conventional example.

FIG. 10 illustrates a conventional bus bridge.
FIG. 9 is a block diagram showing a state in which a cache miss request from a processor returns data to the processor via an N-level cache via a main storage control device.

FIG. 11 illustrates a conventional bus bridge.
FIG. 11 is a diagram showing a state in which data corresponding to reading of main storage data from an I / O is present in an N-level cache, and the data is used instead of the main storage data and cache data in the processor is invalidated.

FIG. 12 illustrates a conventional bus bridge.
FIG. 2 is a relationship diagram showing an example of signals used between circuits connected to a bus and connections.

FIG. 13 illustrates a conventional bus bridge.
FIG. 5 is a timing chart showing an example of operation timing of signals used between circuits connected to a bus.

FIG. 14 is a diagram illustrating an entire simulation model of a test target circuit, a peripheral circuit that is a non-verification target circuit, and a test generation unit in a conventional example.

[Explanation of symbols]

1 circuit to be verified, 2 processor, 3 main memory, 4
Main memory controller, 6 test generator, 7 monitor, 8
Bus, 9 bus monitor, 10 additional circuit dedicated to simulation.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-28668 (JP, A) JP-A-7-271834 (JP, A) JP-A-5-94492 (JP, A) JP-A-3-28 138774 (JP, A) JP-A-6-236293 (JP, A) JP-A-6-59939 (JP, A) JP-A-5-174097 (JP, A) JP-A-9-190379 (JP, A) JP-A-10-105463 (JP, A) "System-level large-scale logic simulation method", Mitsubishi Electric Technical Report, February 1996, Vol. 70, No. 2, p. 11-16 (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 11/22-11/277 G06F 17/50 G01R 31/28-31/30 CSDB (Japan Patent Office)

Claims (88)

(57) [Claims] 1. MESI (Modified, Excl)
used, shared, invalidate
Lad up to four cache states called d)
A simulation model composed of a cache system in which an N-level cache includes an N-1 level cache, a MESI state which is a cache of a write-back type, a test generation unit for generating test data, and an instruction included in the generated test data. It has a monitor unit that resets and sets internal settings of the simulation model, controls clock supply and stops, and compares expected values after completion of simulation for each test and determines test results. Specify the data value for the above simulation model as an initial value at the beginning of each test so that an operation error can be detected according to the state of the cache. Behavior of Logic simulation method characterized by confirming the skilled sex. 2. The method according to claim 1, wherein when the N-th cache is in the state E or S, a different data value is set in the N-th cache from the same address as that of the N-th cache in the main memory, and a bypass instruction is tested. Claim 1
The described logic simulation method. 3. When the N-level cache is in the state E or S, a data value different from that on the same address as the main memory of the N-level cache is set in the main memory, and an access which does not bypass the cache is tested. 2. The logic simulation method according to claim 1, wherein: 4. An MSI (Modified, Share)
d, Invalidated)
Write-back cache with up to three states
, A simulation model comprising a cache system in which the N-th cache includes the N-th primary cache, a test generation unit for generating test data, and a reset of the simulation model in accordance with an instruction included in the generated test data And a monitor unit for performing internal settings, clock supply control and stop control, and comparing expected values after completion of simulation for each test and determining test results, and specifying operating conditions and cache state values as operations used for verification, The data value for the simulation model is set as an initial value at the beginning of each test so that an operation error can be detected according to the state of the cache. At the end of the test, the final value is compared with the expected value and the operation of the circuit under test is verified. The characteristic is to confirm the nature Logic simulation how. 5. A data value different from the data value of the state M is set on each of the same addresses of the N-th cache and the main memory when the N-1st cache is in the state M. The logic simulation method according to claim 1. 6. The bypass instruction is set by setting a data value different from that on the same address as that of the N-th cache of the main memory in the N-th cache when the N-th cache is in the state S. 5. The logic simulation method according to item 4. 7. characterized in that test access not bypass the cache and set the different data values from the N-th order cache gas Tate on the main memory in the same address of the N-th order cache to the main memory when S The logic simulation method according to claim 4, wherein 8. A bus to which an agent for driving a request and a response is connected, a simulation model including a bus monitor connected to the bus for checking a bus protocol, a test generation unit for generating test data, A monitor unit that performs reset and internal setting of the simulation model, clock supply control and stop control, comparison of expected values after completion of simulation for each test, and determination of test results in accordance with instructions included in the test data, and an operation used for verification. Specifies the operating conditions, that conflict error in the middle of the bus protocol of test data values for the simulation model is set as an initial value at the beginning of each test to verify the validity of the operation as an expected value that there are no Characteristic logic simulation method Law. 9. The bus monitor checks a bus transaction of each bus, and for the bus protocol, matches the bus arbitration result with the request issuing agent, inconsistency in request code and address range, inconsistency in request code and data transfer length, undefined. Checks whether any of these protocol violations is a transaction response whose response is not a code value and whose response cannot be separated, notifies the monitor unit when a violation is detected, and then interrupts the simulation by the monitor unit. The logic simulation method according to claim 8, wherein: 10. The bus monitor checks the bus transactions of each bus and inconsistencies between the shake hand signals and the pipeline between N bus transactions and N bus bus transactions which have already been issued for those bus transactions. Stage overtaking, response signal timeout, detached bus transaction response transaction omission, original transaction overtaking by detached response transaction, overflow of each pipeline stage,
10. The logic simulation method according to claim 9, wherein the presence or absence of any of these protocol violations is checked, and when a violation is detected, the monitor is notified and then the simulation is interrupted by the monitor. 11. The bus monitor checks an undefined value or an abnormal signal strength from a signal value on the simulation model when a plurality of agents simultaneously drive different values for the signals on each bus to the bus. 9. The logic simulation method according to claim 8, wherein after the detection is notified to the monitor unit, the simulation is interrupted by the monitor unit. 12. The bus monitor checks the presence or absence of a code error by checking the switch setting when a redundant code such as a parity or an ECC check code is added to each bus signal, and notifies the monitor unit when a code error is detected. 9. The logic simulation method according to claim 8, wherein the simulation is interrupted by the monitor unit. 13. A circuit for counting the number of cycles between signals is connected to the simulation model, and a history of the number of cycles of the signal is recorded in transaction units.
9. The logic simulation method according to claim 8, wherein at the end of the test, the monitor retrieves the accumulated history and compares it with an expected value. 14. The simulation model according to claim 1, wherein a counting circuit for counting the number of transactions is connected, a history of the number of transactions is recorded, and at the end of the test, the monitor section takes out the accumulated history and compares it with an expected value. The logic simulation method according to claim 8, wherein 15. An additional circuit dedicated to simulation for performing an error check separately from the simulation model, wherein the additional circuit dedicated to simulation includes a circuit for identifying an improper state in which the operation of the agent is not idle or a flag in the circuit of the agent. A circuit for detecting an improper state in which a register is set, wherein when the test ends, the monitor section notifies the monitor section that the operation of the agent is in an improper state, and then the monitor section interrupts the simulation. Logic simulation method described in 8 16. The logic simulation method according to claim 15, wherein at the end of the test, the monitor unit determines that the agent is in an invalid state. 17. A simulation model comprising a bus connecting between a circuit to be verified and a circuit not to be verified, a test generator for generating test data, A monitor unit that performs reset and internal setting, clock supply control and stop control, and comparison of expected values after completion of simulation for each test and test result determination,
Specifies the operating conditions of the operation using the verification, the verification circuit data value during the set test run as an initial value at the beginning of each test for the simulation model
A logic simulation method characterized by confirming the validity of the circuit to be verified by not generating an error indicating a failure of the logic circuit. 18. The circuit to be verified has a flag capable of determining the content of an error, and the monitor ignores or resets the set state of the flag so as not to malfunction during and immediately after a reset operation of the circuit to be verified. 18. The logic simulation method according to claim 17, further comprising means for performing a simulation, wherein the simulation is interrupted when the type of the flag is set. 19. The logic simulation according to claim 17, further comprising an additional circuit dedicated to simulation for performing an error check separately from the simulation model, wherein when an error is detected, the monitor is notified and the simulation is interrupted by the monitor. Method 20. MESI (Modified, Exc)
used, shared, invalidat
ed) up to four cache states
MESI state or MSI (Modified, Shared, Inv) which is a write-back type cache
The state of the cache, referred to as
MS that is a write-back cache up to 3 states
A cache system including an I-state and an N-level cache including an N-1 level cache, an agent for driving a request and a response, a bus connecting the cache system and the agent,
A simulation model comprising a bus monitor connected to this bus for checking a conflict between a bus protocol and a cache state, a test generation unit for generating test data, and resetting the simulation model in accordance with an instruction included in the generated test data A monitor unit for performing internal settings, clock supply control and stop control, and comparing expected values after completion of simulation for each test and determining test results, specifying operating conditions as operations used for verification, and data values for the simulation model. Is set as an initial value at the beginning of each test. The feature is to check Logic simulation how. 21. The bus monitor checks a bus transaction of each bus, and for the bus protocol, matches the bus arbitration result with the request issuing agent, inconsistency in request code and address range, inconsistency in request code and data transfer length, undefined. A logic simulation method in which a transaction response that is not a code value and whose response cannot be separated, checks for any of these protocol violations, notifies the monitor unit when a violation is detected, and interrupts the simulation by the monitor unit. The bus monitor checks the bus transactions of each bus, and checks for inconsistencies between the cache status value at the time of issuing the bus request source and the request code of the bus request for those bus transactions.
3. The simulation is interrupted by the monitor unit after notifying the monitor unit when inconsistency is detected.
0 logic simulation method 22. The bus monitor checks the bus transactions of each bus, and checks for inconsistencies between the cache status value of the bus transactions and the request code of the bus request after a fixed time from the end of the bus request, for the bus transactions. 21. The logic simulation method according to claim 20, wherein the simulation is interrupted by the monitor after the notification to the monitor at the time. 23. The bus monitor checks bus transactions of each bus, responds to the bus request with respect to the bus transaction, responds to a snoop result of another agent on the same bus, and caches the request source of the bus request. 21. The logic simulation method according to claim 20, wherein the inconsistency with the state value is checked, and when the inconsistency is detected, the monitor is notified and the simulation is interrupted by the monitor. 24. The bus monitor checks a bus transaction of each bus and sends a response defining the final operation of the bus transaction corresponding to the request to a snoop result of another agent on the same bus or a request issuing source. 21. The logic simulation method according to claim 20, wherein a contradiction is checked based on the cache state value, and when the contradiction is detected, the monitor is notified and the simulation is suspended by the monitor. 25. A simulation model comprising a bus connecting between a circuit to be verified and a circuit not to be verified, a test generation unit for generating test data, and a simulation model of the simulation model according to an instruction included in the generated test data. A monitor unit that performs reset processing, internal setting of the circuit to be verified, clock supply control and stop control, comparison of expected values after simulation for each test, and determination of test results, specifies operating conditions as operations used for verification. A logic simulation method for setting a data value for the simulation model as an initial value at the beginning of each test and comparing the final value with an expected value at the end of the test to confirm the validity of the operation of the circuit to be verified. Reset the target circuit and the above non-verification target circuit for each test A logic simulation method comprising performing processing. 26. A reset processing which requires a large number of clocks in the reset processing of the circuit to be verified, a switch which does not perform repetitive processing is provided in the circuit to be verified, or the value of the counter of the repetitive circuit of the circuit to be verified is set to 26. The logic simulation method according to claim 25, wherein a forcible change is performed by a monitor, and a part of the reset processing is performed by the monitor. 27. The flag according to claim 25, wherein a flag or a register in the circuit to be verified and set by an operation sequence using a clock after reset processing is set to an arbitrary value by the monitor unit. Logic simulation method. 28. When the circuit to be verified has an N-order cache, an initial state is set by setting the data value of the N-order cache and the state value of the cache to arbitrary values by the monitor unit. 26. The logic simulation method according to claim 25, further comprising: 29. When the circuit to be verified includes an N-th order cache and the N-th order cache includes an N-1st order cache in a processor connected to the bus, the N-th order cache is included in the N-th order cache.
26. The logic simulation method according to claim 25, wherein the initial state is set by setting the data value and the cache state value of the primary cache to arbitrary values by the monitor unit. 30. A circuit to be verified having an Nth-order cache, a circuit to be verified having no cache, a processor having a non-verification target and having a cache of N-1 or less, and a main memory being a non-verification target circuit. A main memory control device for controlling main memory, a simulation model including a bus connecting the circuit to be verified with the processor and the main memory control device, a test generation unit for generating test data, A monitor unit for resetting the simulation model, setting internal settings of the circuit to be verified, controlling clock supply and stopping, and comparing expected values after completion of simulation for each test and determining test results according to instructions included in the test data; Specify the operating conditions for the operation to be used for In the logic simulation method for setting a data value to be performed as an initial value at the beginning of each test and comparing the final value with an expected value at the end of the test to confirm the validity of the operation of the circuit to be verified, Selection of an address that includes the N-1 level cache and that allows a plurality of write accesses to be performed on condition that the protocol order is changed when the data write order to the processor appears on the bus Is divided into a non-shared address area that can be used only once and a shared address area that can be used multiple times. For the non-shared address area, it is determined not to select an already registered address. A test is generated to select an address that does not fall into the non-shared address area, and the non-shared address area is For logic simulation method for comparing the final value of the cache, characterized in that the shared address space does not perform comparison identifying the cache. 31. Each time the non-shared address area and the shared address area are generated, an address is registered in a table, and a distinction between the non-shared address area and the shared address area is determined on the table. Item 30. The logic simulation method according to Item 30, 32. A method according to claim 32, wherein said non-shared address area and said shared address area are distinguished between shared and non-shared by a bit pattern of an address, or a processor number or a value associated with the processor number is used to generate a non-shared address. 31. The logic simulation method according to claim 30, wherein: 33. The first request issuance in the processor for the N-1st cache and the second request issuance to the bus are directly allowed ignoring the N-1th cache, and the first request is issued. 31. The logic simulation method according to claim 30, wherein an address is managed such that an index value of an N-1 level cache for the request of the second request is exclusive of an index value of an N level cache for the second request. . 34. An address is managed by a bit pattern or a range of values constituted by a plurality of bits so that the index value of the N-th cache is exclusive to the index value of the N-1th cache. The logic simulation method according to claim 33, wherein 35. Each N-th cache has a first table and holds a non-shared address so that the index value of the N-th cache is exclusive to the N-1 primary cache. The cache has a second table and a third table, the second table holds a non-shared address, the third table holds a shared address, and if a non-shared address is used, it exists in any of those tables. An address having an index value not to be selected is selected, and when a shared address is used, an address having an index value not present in the third table or any of the above tables is selected, and the selected address is stored in the third table. 4. The method of claim 3, wherein
3. The logic simulation method according to 3. 36. The address of a read-only or non-changeable area for the shared address and the address of a changeable area by writing are determined so as to be uniquely determined from the bit pattern of the address, and the address of a request issued by the processor is determined. After that, the type of request is determined by determining whether the area accessed from those addresses is a read-only or non-changeable area or another changeable area. At the end of the test, the final value of the cache for the read-only or non-changeable area 31. The logic simulation method according to claim 30, wherein the comparison is made and the changeable area is not compared. 37. Under the condition that the order of protocol writing is changed when the data writing order of the processor appears on the bus, different commands of the same processor match the bit width of the bus. 37. The logic simulation method according to claim 36, wherein the final value of the cache is compared without writing different data to the same address. 38. The logic simulation method according to claim 36, wherein said processor has a memory write command in a unit of a bit width of 1 / K of a bit width of a data bus. 39. When the processor accesses the same cache line from the same processor with a read or write command to the (N−1) th cache, the address to be accessed can be selected only once. 37. The logic simulation method according to claim 36, wherein an address which has already been used is avoided by limiting the number of addresses. 40. When the processor issues a request for accessing the same cache line address, the address range to be written by each processor has a write command in the unit of a bus width as an address matching the bit width of the bus. 37. The logic simulation method according to claim 36, wherein the final value of the cache is compared without writing the same data in units of bus width. 41. The logic simulation method according to claim 36, wherein an address range to be written by each processor has a bit width of 1 / K of a bit width of a data bus. 42. When the processor verifies the consistency with the N-level cache of the circuit to be verified using a request for accessing the N-1 level cache or the N-second level cache, each of the shared addresses is Manages data values after request execution for each processor,
Using a table capable of holding a plurality of combinations of the cache line address related to the shared address and the data value constituting the line, updating and testing the data value each time a write request transaction is generated during test generation, 37. The logic simulation method according to claim 36, wherein the data values are compared if the status values of the main memory and all the caches are valid at the end of the test. 43. When the circuit to be verified rejects a bus transaction issued from the circuit to be verified and makes a retry request for prompting reissuing of the request, the circuit to be verified does not execute the transaction requested to be retried. 31. The logic simulation method according to claim 30, further comprising: requeueing at the end of the transaction already queued. 44. When the content of the request code issued by the non-verification target circuit or the serialization designation is detected before issuing the next transaction to be issued, it is confirmed that the response of the verification target circuit is not a retry request. 44. The logic simulation method according to claim 43, wherein a request for the next transaction is issued from. 45. A circuit to be verified having an N-order cache, a circuit to be verified having no cache, a processor which is a circuit to be verified and has a cache of N-1 or less, and a main memory which is a circuit to be verified. A main memory control device for controlling a main memory, a bus connecting the circuit to be verified with the processor and the main memory control device, and a bus monitor connected to the bus for checking a bus protocol, A simulation model having a delay operation setting and a delay operation circuit of a bus protocol in a non-verification target circuit or the bus monitor, a test generation unit that generates test data including an operation delay of the bus protocol of the bus, According to the instructions included, reset the simulation model and set the internal A monitor unit for clock supply control and stop control, comparison of expected values after completion of simulation for each test, and determination of test results is specified, operating conditions as operations used for verification are specified, and data values for the simulation model are set for each test. A logic simulation method comprising first setting initial values and comparing the final values with expected values at the end of a test to confirm the validity of the operation of the circuit to be verified. 46. The verification target circuit operates in response to a request from the non-verification target processor, and the verification target circuit determines an internal state corresponding to a previously received request and receives a new request. And a new internal state by a combination of the internal state and the internal state,
46. The logic simulation method according to claim 45, wherein when a request is issued from the processor by an access command to the primary cache, the request from the processor to the bus is indirectly delayed. 47. As a command delay condition of the processor, a command indicating a delay is inserted between commands, or a signal value of the bus or a change in the signal value becomes N-1 from the processor until the designated condition is reached. 47. The access to the next cache is delayed.
The described logic simulation method. 48. A bus command queue is provided between the (N−1) th level cache of the processor and the bus, and the bus command queue is specified by the access command without specifying a delay.
47. The logic simulation method according to claim 46, wherein a delay target, a delay condition, and a delay cycle number are designated in the command queue, and the delay is performed when a request is issued on the bus. 49. After the circuit to be verified issues a request to the bus, a queuing operation of an agent other than the circuit to be verified into a buffer and a delayed response from the agent due to an overflow state of the buffer are performed. 47. When issuing a request in response to a signal for suppressing a request depending on the state of the request, the buffer size of the agent is set smaller than the buffer size actually used, and the response timing and the request suppression timing are changed. The described logic simulation method. 50. The logic according to claim 49, wherein when the function for setting the buffer size is provided on the simulation model, the function is used, and when the function is not provided, the function is set at the time of simulation. Simulation method. 51. When the circuit to be verified receives a response from the request source or the second agent to the request from the first agent other than the simulation model, the circuit to be verified returns a response.
The condition for instructing the request issuer or the second agent to delay the response cycle is when the queue of the bus pipeline defined by the bus protocol is equal to or greater than a preset value or equal to or less than a preset value. The logic simulation method according to claim 45, wherein: 52. When the circuit to be verified receives a response from a request issuing source or a second agent in response to a request from a first agent other than the simulation model, and the circuit to be verified returns a response, the request issuance 46. The method according to claim 45, wherein when instructing the former or the second agent to delay the response cycle, the delay operation is applied to a predetermined number of transactions counted from the start of the test on the bus. Logic simulation method. 53. When the circuit to be verified receives a response from a request issuing source or a second agent to a request from a first agent other than the simulation model and returns a response, the circuit to be verified issues the request. 46. The logic simulation method according to claim 45, wherein when instructing the former or said second agent to delay the response cycle, a delay operation is applied when the addresses of the transactions on the bus match. 54. While the circuit to be verified is processing the first signal on the bus, an agent other than the circuit to be verified waits a predetermined number of cycles for the second signal on the bus. The logic simulation method according to claim 45, wherein the signal is driven in the first cycle satisfying the protocol. 55. While the circuit to be verified connected to the plurality of buses is processing the first signal on the first bus, an agent other than the circuit to be verified changes the second signal on the second bus. 46. The logic simulation method according to claim 45, wherein the signal is driven in the first cycle that satisfies the protocol of the signal after waiting for a preset number of cycles. 56. When the circuit to be verified operates by receiving a signal of another agent on the simulation model, all values that can be represented by the number of bits of the signal value of the agent are individually or grouped. 46. The logic simulation method according to claim 45, wherein the number of cycles for delaying the driving of the signal of the agent is individually designated for each of. 57. When the circuit to be verified operates upon receiving a request from another agent on the simulation model, when the address of the request issued by the agent matches a preset address, the agent The logic simulation method according to claim 45, wherein the request is issued after a set number of cycles. 58. An operating condition of the agent other than the circuit to be verified and a delay condition of a signal on the bus are first.
58. The method according to claim 46, wherein the second condition is applied after the first condition is applied.
The logic simulation method according to any one of the above. 59. The logic simulation method according to claim 45, wherein the bus monitor records a signal history in transaction units and displays the history at the end of the test or during the test. 60. Inject an error signal from the non-verification target circuit onto the bus or drive an error report signal on the bus to cause the verification target circuit or another agent on the simulation model to perform a retry operation. The logic simulation method according to claim 45, wherein: 61. MESI (Modified, Exc)
used, shared, invalidat
ed) up to four cache states
MESI state or MSI (Modified, Shared, Inv) which is a write-back type cache
The state of the cache, referred to as
MS that is a write-back cache up to 3 states
A circuit to be verified having an N-level cache constituted by an I state, a circuit to be verified having no cache,
A processor which is a non-verification target circuit and has a cache of order N-1 or less; a main storage which is a non-verification target circuit; and a main memory control device which controls the main memory; a verification target circuit, the processor and the main memory control device A simulation model composed of a bus for externally controlling the circuit to be verified and examining the result process, a test generation unit for generating test data, and an instruction included in the generated test data. A monitor unit for resetting the simulation model, setting the internal settings of the circuit to be verified, controlling clock supply and stopping, and comparing the expected value after the simulation is completed for each test and determining the test result. Determined by a combination of random numbers and manually specified conditions, Logic simulation method characterized by the data value to validate the operation of the comparison by the verification circuit with an expected value to their final values at the end of the set as the initial value testing at the beginning of each test. 62. When the Nth level cache includes the N-1st level cache, and the circuit to be verified operates by receiving a signal of another agent on the simulation model, the signal on the agent or on the bus 62. The logic simulation method according to claim 61, wherein the number of cycles for delaying the driving of the signal is determined according to a random number based on a distribution table set in advance. 63. The logic simulation method according to claim 62, wherein a plurality of the distribution tables are provided, and a distribution table is designated for each delay element. 64. When the processor verifies the circuit to be verified by accessing the (N−1) th cache with a read and write command,
62. The logic simulation method according to claim 61, wherein an initial value of the next cache is determined by a random number, and an initial state of the (N-1) th cache that can be taken for the value is selected by a random number. 65. When issuing a request from the processor to the bus, the type of the request is selected by a random number, and the request value is determined according to a random number based on a preset distribution table. 63. The logic simulation method according to claim 61. 66. When the processor responds to the bus with a snoop result of a cache included in the processor in response to a request on the bus, the response snoop value is based on a preset distribution table. 62. The logic simulation method according to claim 61, wherein the logic simulation is determined according to a random number. 67. A response value when the non-verification target circuit responds to the request on the bus to indicate whether or not to accept the request, whether or not to transfer data, or to indicate whether or not there is a data transfer path or an error. The logic simulation method according to claim 61, wherein the response value is determined according to a random number based on a preset distribution table. 68. When a random number is used for determining an index of a cache at a target address of a request issued from within the processor and for determining a way for checking the final state of the cache, an identification symbol is assigned to the index and the way which can be allocated. 62. The logic simulation method according to claim 61, wherein the determination is made in accordance with a random number from the identification symbol excluding the identification symbol already assigned. 69. A command or address determined by the non-verified circuit or a response value or a delay cycle when the circuit under verification operates on the bus by receiving a signal of another agent on the simulation model. 62. The logic simulation method according to claim 61, wherein a value uniquely determined from a random number is adopted as the number, and the random number is managed or commonly managed by the monitor unit. 70. The logic simulation method according to claim 69, wherein a random number generation routine managed by said monitor unit is used for generating said random number. 71. The logic simulation method according to claim 69, wherein said random number seed is left as log data of a test result. 72. The logic simulation method according to claim 69, wherein a random number generated during execution of the simulation and a routine identifier using the random number are stored. 73. The method according to claim 69, wherein the random number is generated in advance and stored as data in a file.
The described logic simulation method. 74. A circuit to be verified having an N-order cache, a circuit to be verified having no cache, a processor being a circuit to be verified and having a cache of N-1 or less, and a main memory being a circuit not to be verified. A main storage control device for controlling main storage, a simulation model including a bus connecting the circuit to be verified with the processor and the main storage control device, a test generation unit for generating test data, A monitor unit for resetting the simulation model, setting internal settings of the circuit to be verified, controlling clock supply and stopping, and comparing expected values after completion of simulation for each test and determining test results in accordance with instructions included in the test data; Specify the operating conditions for the operation used for Control the usage of the entry, control the usage of the cache entry after the clock is supplied, and control the generation of addresses and commands that determine the entry. A data value is generated so that an event occurs with a high probability, and a data value for the simulation model is set as an initial value at the beginning of each test, and at the end of the test, the final value is compared with an expected value. A logic simulation method characterized by confirming the validity of an operation. 75. The Nth level cache includes the N-1st level cache, wherein the processor accesses the N-1st level cache by read and write commands and is connected to the processor or the circuit to be verified. 8. The method according to claim 7, wherein a bit pattern of an address for determining an index of a cache among addresses used as requests by another agent is limited, and an address is selected by a random number within the limited range.
5. The logic simulation method according to item 4. 76. The type of an address bit pattern composed of bits higher than the bit used for the index of the cache in the address used as a request by the other agent, and the address is selected by a random number from the restricted one. 8. The method of claim 7, wherein
5. The logic simulation method according to item 4. 77. The method according to claim 74, wherein the circuit to be verified has an N-order set associative cache, and the number of usable ways of the cache or the availability of each way is selected and set. The described logic simulation method. 78. A command is issued by the processor from the processor to forcibly invalidate the contents of the cache or write back to the main memory, and the circuit to be verified adds or subtracts an internal counter sequentially to invalidate the cache. When processing the conversion or write-back operation, when the value of the counter reaches a preset value, the value of the counter is forcibly changed, thereby omitting the simulation and restricting the use of the omitted address. 75. The logic simulation method according to claim 74, wherein: 79. The monitor unit or the simulation model substitutes invalidation or write back of an address omitted by forcibly changing the value of the counter without advancing a clock. 78. The logic simulation method according to 78. 80. MESI (Modified, Exc
used, shared, invalidat
ed) up to four cache states
MESI state or MSI (Modified, Shared, Inv) which is a write-back type cache
The state of the cache, referred to as
MS that is a write-back cache up to 3 states
A simulation model composed of a cache system composed of an I state and an Nth cache including an N-1th cache; a test generation unit for generating test data; resetting and internal operation of the simulation model in accordance with instructions included in the generated test data A monitor unit for setting, clock supply control, stop control, comparison of expected values after completion of simulation for each test, and determination of test results, designating operating conditions and cache state values as operations used for verification, At the beginning of each test as an initial value so that an operation error can be detected according to the cache state, and compare the final value with the expected value at the end of the test to verify the correctness of the operation of the circuit to be verified. Logic simulation method to check A computer-readable recording medium a program for realizing. 81. A bus to which an agent for driving a request and a response is connected, a simulation model comprising a bus monitor connected to the bus and for checking a bus protocol, a test generation unit for generating test data, A monitor unit that performs reset and internal setting of the simulation model, clock supply control and stop control, comparison of expected values after completion of simulation for each test, and determination of test results in accordance with instructions included in the test data, and an operation used for verification. Specifies the operating conditions, correctness of operation and conflict errors middle bus protocol test data values for the simulation model is set as an initial value at the beginning of each test NYCO as year <br/> waiting value Check the logic simulation method realized Computer readable recording medium recording the order of the program. 82. A simulation model comprising a bus connecting between a circuit to be verified and a circuit not to be verified, a test generation unit for generating test data, and a simulation model according to an instruction included in the generated test data. A monitor unit that performs reset and internal setting, clock supply control and stop control, and comparison of expected values after completion of simulation for each test and test result determination,
Specifies the operating conditions of the operation using the verification, the verification circuit data value during the set test run as an initial value at the beginning of each test for the simulation model
A computer-readable recording medium storing a program for realizing a logic simulation method for confirming the validity of the circuit to be verified by not generating an error indicating a failure of the computer. 83. MESI (Modified, Exc
used, shared, invalidat
ed) up to four cache states
MESI state or MSI (Modified, Shared, Inv) which is a write-back type cache
The state of the cache, referred to as
MS that is a write-back cache up to 3 states
A cache system including an I-state and an N-level cache including an N-1 level cache, an agent for driving a request and a response, a bus connecting the cache system and the agent,
A simulation model comprising a bus monitor connected to this bus for checking a conflict between a bus protocol and a state of a cache; a test generation unit for generating test data; resetting the simulation model in accordance with an instruction included in the generated test data And a monitor unit for performing internal settings, clock supply control and stop control, and comparing expected values after completion of simulation for each test and determining test results, designating operating conditions as operations used for verification, and data values for the simulation model. Is set as an initial value at the beginning of each test, and during the test or at the end of the test, the validity of the operation of the circuit to be verified is assumed to be an expected value with no inconsistency between the cache state detected by the bus monitor and the bus protocol. Logic simulation to check A computer-readable recording medium a program for realizing the Deployment method. 84. A simulation model comprising a bus connecting between a circuit to be verified and a circuit not to be verified, a test generation unit for generating test data, and a simulation model according to an instruction included in the generated test data. A monitor unit that performs reset processing, internal setting of the circuit to be verified, clock supply control and stop control, comparison of expected values after simulation for each test, and determination of test results, and specifies operating conditions as operations used for verification. A logic simulation method for setting a data value for the simulation model as an initial value at the beginning of each test and comparing the final value with an expected value at the end of the test to confirm the validity of the operation of the circuit to be verified. Reset the target circuit and the above non-verification target circuit for each test A computer-readable storage medium storing a program for realizing a logic simulation method characterized by performing processing. 85. A circuit to be verified having an Nth-order cache, a circuit to be verified having no cache, a processor being a non-verification target circuit and having a cache of N-1 or less, a main memory being a non-verification target circuit, A main storage control device for controlling main storage, a simulation model including a bus connecting the circuit to be verified with the processor and the main storage control device, a test generation unit for generating test data, A monitor unit for resetting the simulation model, setting internal settings of the circuit to be verified, controlling clock supply and stopping, and comparing expected values after completion of simulation for each test and determining test results in accordance with instructions included in the test data; Specify the operating conditions for the operation to be used for In the logic simulation method for setting a data value to be performed as an initial value at the beginning of each test and comparing the final value with an expected value at the end of the test to confirm the validity of the operation of the circuit to be verified, Selection of an address that includes the N-1 level cache and that allows a plurality of write accesses to be performed on condition that the protocol order is changed when the data write order to the processor appears on the bus Is divided into a non-shared address area that can be used only once and a shared address area that can be used multiple times. For the non-shared address area, it is determined not to select an already registered address. A test is generated to select an address that does not fall into the non-shared address area, and the non-shared address area is For comparing the final value of the cache, and computer readable recording medium a program for realizing the logic simulation method characterized by the shared address space it does not perform comparison identifying the cache. 86. A circuit to be verified having an N-order cache, a circuit to be verified having no cache, a processor which is a circuit to be verified and has a cache of N-1 or less, and a main memory which is a circuit not to be verified. A main memory control device for controlling a main memory, a bus connecting the circuit to be verified with the processor and the main memory control device, and a bus monitor connected to the bus for checking a bus protocol, A simulation model having a delay operation setting and a delay operation circuit of a bus protocol in a non-verification target circuit or the bus monitor, a test generation unit that generates test data including an operation delay of the bus protocol of the bus, According to the instructions included, reset the simulation model and set the internal A monitor unit for clock supply control and stop control, comparison of expected values after completion of simulation for each test, and determination of test results is specified, operating conditions as operations used for verification are specified, and data values for the simulation model are set for each test. At the end of the test, a program for realizing a logic simulation method characterized by setting as initial values and comparing the final values with expected values at the end of the test to confirm the validity of the operation of the circuit to be verified is recorded. Computer readable recording medium. 87. MESI (Modified, Exc.
used, shared, invalidat
ed) up to four cache states
MESI state or MSI (Modified, Shared, Inv) which is a write-back type cache
The state of the cache, referred to as
MS that is a write-back cache up to 3 states
A circuit to be verified having an N-level cache constituted by an I state, a circuit to be verified having no cache,
A processor which is a non-verification target circuit and has a cache of order N-1 or less; a main storage which is a non-verification target circuit; and a main memory control device which controls the main memory; a verification target circuit, the processor and the main memory control device A simulation model composed of a bus for externally controlling the circuit to be verified and examining the result process, a test generation unit for generating test data, and an instruction included in the generated test data. A monitor unit for resetting the simulation model, setting the internal settings of the circuit to be verified, controlling clock supply and stopping, and comparing the expected value after the simulation is completed for each test and determining the test result. Determined by a combination of random numbers and manually specified conditions, At the beginning of each test, the data values to be set are set as initial values, and at the end of the test, the final values are compared with expected values, and a program for realizing a logic simulation method for confirming the validity of the operation of the circuit to be verified is prepared. A computer-readable recording medium that has been recorded. 88. A circuit to be verified having an N-level cache, a circuit to be verified having no cache, a processor being a circuit to be verified and having a cache of N-1 or less, and a main memory being a circuit not to be verified. A main storage control device for controlling main storage, a simulation model including a bus connecting the circuit to be verified with the processor and the main storage control device, a test generation unit for generating test data, A monitor unit for resetting the simulation model, setting internal settings of the circuit to be verified, controlling clock supply and stopping, and comparing expected values after completion of simulation for each test and determining test results in accordance with instructions included in the test data; Specify the operating conditions for the operation used for Control the usage of the entry, control the usage of the cache entry after the clock is supplied, and control the generation of addresses and commands that determine the entry. A data value is generated so that an event occurs with a high probability, and a data value for the simulation model is set as an initial value at the beginning of each test, and at the end of the test, the final value is compared with an expected value. A computer-readable storage medium storing a program for realizing a logic simulation method for confirming the validity of an operation.