JP3161833B2 - Active trap circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active trap circuit effective for being incorporated in an integrated circuit.

[0002]

2. Description of the Related Art FIG.
The circuit shown in FIG. That is, the input terminal 1
Low-pass filter (LPF) 2 and high-pass filter (H
PF) 3. The outputs of the low-pass filter 2 and the high-pass filter 3 are added by an adder 4 and output from an output terminal 5.
Is derived to As a result, components located between the low band and the high band can be dropped.

FIG. 3 (B) shows a specific configuration example of the low-pass filter 2, FIG. 3 (C) shows a specific configuration example of the high-pass filter 3, and FIG. 3 (D) shows a specific example of the adder 4. It is a structural example.

In FIG. 3B, an input terminal 11 is connected to a base of a transistor Q11 via a resistor R11 and to an emitter and an output terminal 12 of a transistor Q12 via a capacitor C11. The collectors of the transistors Q11 and Q12 are connected to a power supply line, and the respective emitters are grounded via current sources i11 and i12, respectively. The emitter of transistor Q11 is connected to the base of transistor Q12 via resistor R12. The base of the transistor Q12 is grounded via the capacitor C12.

[0005] The transfer function of the above circuit will be obtained. now,
Assuming that the signals at each node are A (S), B (S) and C (S) as shown in the figure, B (S) = [(1 / SC11) / {R11 + (1 / SC11)}] A (S) + [R11 / {R11 + (1 / SC11)}] C (S) = {A (S) + SC11R11C (S)} / (1 + SC11R11) (1) C (S) = [(1 / SC12) / {R12 + (1 / SC12)｝] B (S) = B (S) / (1 + SC12R12) (2) When B (S) is deleted and rearranged from equations (1) and (2), C (S) / A ( S) = 1 / (1 + SC12R12 + S 2 C11C12R11R12) = (1 / C11C12R11R12) / {S 2 + (1 / C11R11) S + (1 / C11C12R11R12)} ... (3) the sharpness of the filter Q, the cutoff angular frequency Assuming that ω0, the low-pass filter is generally expressed by the following equation.

C (S) / A (S) = ω0 ² / ｛S ² + (ω0 / Q) + ω0 ² (4) By comparing each coefficient of equations (3) and (4), ω0 = 1 / (C11C12R11R12) ^1/2 (5) Q = (C11R11 / C12R12) ^1/2 (6) Thus, the circuit of FIG. 3B has the characteristics of a low-pass filter, and its transfer function is as shown in equation (3).

FIG. 3C shows a specific configuration example of the high-pass filter 2.

The input terminal 21 is connected to the base of the transistor Q21 via the capacitor C21 and to the emitter of the transistor Q22 and the output terminal 22 via the resistor R21. The collectors of the transistors Q21 and Q22 are connected to a power supply line, and the respective emitters are grounded via current sources i21 and i22. The emitter of transistor Q21 is connected to the base of transistor Q22 via capacitor C22. The base of the transistor Q22 is grounded via a resistor R22 and connected to a power supply line via a resistor R23.

The transfer function of the above circuit will be obtained. As shown in the figure, the signals at each node are represented by A '(S), B' (S),
Let C '(S).

B ′ (S) = [(1 / SC21) / {R21 + (1 / SC21)}] C ′ (S) + [R21 / {R21 + (1 / SC21)}] A ′ (S) = { C ′ (S) + SC21R21A ′ (S)｝ / (1 + SC21R21) (7) Since the power supply VCC is equivalent to being grounded in terms of AC, the combined resistance of the resistors R22 and R23 is (parallel connection). From) R24 = R22R23 / (R22 + R23) C '(S) = [R24 / {R24 + (1 / SC22)}] B (S) = SC22R24B (S) / (1 + SC22R24) (8) (7) and rearranging erases the B (S) from (8), C '(S) / a ' (S) = S 2 C21C22R21R22 / (1 + jωC21R21 + S 2 C21C22R21R22) = S 2 / {S 2 + (1 / C22R22 ) S + (1 / C21C22R21R22)｝ (9) The sharpness of the filter is Q ′, and the cutoff angular frequency is ω0 ′.
In general, a high-pass filter is expressed by the following equation.

C ′ (S) / A ′ (S) = S ² / {S ² + (ω 0 / Q) S + ω 0 ² } (10) Comparing each coefficient of the equations (9) and (10) Ω0 ′ = 1 / (C21C22R21R22) ^1/2 (11) Q ′ = (C22R22 / C21R21) ^1/2 (12) Thus, the circuit of FIG. 3C has the characteristics of a high-pass filter, and its transfer function is as shown in equation (9).

FIG. 3D shows an example of a specific configuration of the adder 4.

The first input terminal 31 is connected to the base of the transistor Q31. The collector of the transistor Q31 is connected to the power supply line, and the emitter is connected to the collector of the transistor Q32 via the resistor R31 and to the collector of the transistor Q33 via the resistor R32. Second input terminal 32 is connected to the base of transistor Q32. The emitters of the transistors Q32 and Q33 are connected via a resistor R33, and are grounded via current sources i31 and i32, respectively. The output terminal 33 is derived from the collector of the transistor Q33. A constant bias potential is applied to the base of the transistor Q33.

Looking at the addition path in the adder 4,
Each of the two inputs is a path indicated by a dotted line. First, looking at the input Vin1 of the first system, the relationship between the input and output AC components is as follows.
Since the constant voltage source V1 is grounded in terms of AC, Vout = (R32 / R33) (Vin1-V1) = (R32 / R33) Vin1 (13) From this equation, Vout and Vin1 have the same phase.

Next, looking at the input Vin2 of the second path, the relationship between the input and output AC components is that the signal at the base terminal of the transistor Q32 and the emitter signal are in phase, so that Vout and Vin2
Are in phase. Therefore, Vout = Vin1 + Vin2.

As described above, when the transfer function of the trap circuit is obtained, A (S) C of the equation (3) is obtained.
(S) corresponds to X (S) and V (S) in FIG. 3 (A), and A ′ (S) C ′ (S) in equation (10) corresponds to X (S) in FIG. S)
, W (S).

[0017] Therefore (3), (4) from the equation, V (S) = [( 1 / C11C12R11R12) / {S 2 + (1 / C11R11) S + (1 / C11C12R11R12)}] · X (S) = [Ω0 ² / {S ² + (ω 0 / Q) S + ω 0 ² }] X (S) (14) Also, from equations (9) and (10), W (S) = [S ² / ｛S ² + (1) / C22R22) S + (1 / C21C22R21R22)}] × X (S) = [S 2 / {S 2 + (ω0 '/ Q') S + ω0 '2}] X (S) ... (15) Thus, as a trap circuit Is added by the adder 4 to the V (S) component... (14) and the W (S) component... (15), so that Y (S) = [ω0 ² / ｛ S ² + (ω 0 / Q) S + ω 0 ² ｝] + [S ² / {S ² + (ω 0 ′ / Q ′) S + ω 0 ′ ² }] (16) Here, ω 0 of the expressions (14) and (15) = ω0 ', Q = Q' if conditions are satisfied for, Y (S) = (S ^{+ Ω0 2) / {S 2} + (ω0 / Q) S + ω0 2} ... (17) is obtained, the circuit of FIG. 3 (A) may have the characteristics of the trap circuit.

From the above, the problems of the above circuit are that the circuit configuration is complicated, that is, the number of elements is large, and (1)
In order to obtain the expression (7), the ω0 and Q of the low-pass filter and the high-pass filter are equal, and the expressions (14) and (15) become equal.
A condition called an expression is required, and a circuit system is required to realize this. Also, a low-pass filter from the input,
It is necessary to equalize the gains of the two paths, that is, the path of the adder, the high-pass filter from the input, and the path of the adder, which is difficult in design.

[0019]

As described above, the circuit configuration is complicated, and there are many restrictions, which are disadvantageous in terms of design and cost.

An object of the present invention is to provide an active trap circuit which has a simple circuit configuration, is suitable for incorporating an integrated circuit, and is advantageous in terms of design and cost.

[0021]

According to the present invention, a two-input terminal is provided.
A circuit having one output terminal. When a predetermined potential is applied to one input terminal and an input signal is applied to the other input terminal, a low-pass filter characteristic is exhibited in a predetermined band, and a signal corresponding to the characteristic is output to the output terminal. 3 terminals for outputting, applying a predetermined potential to the other input terminal and applying an input signal to the one input terminal, exhibiting a high-pass filter characteristic in a predetermined band, and outputting a signal corresponding to the characteristic to the output terminal. An active trap circuit configured by a combination of circuit units, wherein a signal supplied to a signal input terminal is supplied to the other input terminal,
A first 3-terminal circuit unit predetermined potential to the one input terminal to output an output signal to the output terminal is supplied, the signal supplied to said input terminal said supplied to one input terminal of the other A second three-terminal circuit unit for supplying a predetermined potential to an input terminal and outputting an output signal to an output terminal; and an output of the first three-terminal circuit unit being supplied to the other input terminal and the second three terminal An output of the circuit unit is supplied to the one input terminal, an output is supplied to a signal output terminal, and the
And a third three-terminal circuit unit that is supplied as the predetermined potential to the other input terminal of the second three-terminal circuit unit.

[0022]

According to the above-mentioned means, the three-terminal circuit unit comprises:
One and the input terminal side resistor, and the capacitance of the other input terminal side, in order to be realized by a simple circuit composed of a buffer for extracting an output connection point of the resistor and capacitor, can the overall arrangement be simplified integrated It is suitable for incorporation of circuits, and is advantageous in terms of design and cost.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A is a block diagram of an embodiment of the present invention. The input terminal 41 is connected to the first input terminal in of the first three-terminal circuit unit 51 via the first amplifier 42.
Connected to 1. The input terminal 41 is connected to the second input terminal in2 of the second three-terminal circuit unit 52 via the second amplifier 43. A predetermined voltage V1 is applied to the first input terminal in1 of the second three-terminal circuit unit 52. Output terminal ou of first three-terminal circuit unit 51
t is the first input terminal in of the third three-terminal circuit unit 53
The output terminal out of the second three-terminal circuit unit 52 is connected to the second input terminal in2 of the third three-terminal circuit unit 53. First three-terminal circuit unit 5
One second input terminal in2 and a third three-terminal circuit unit 53
Are connected to each other and to the output terminal 44.

Here, the first, second, and third three-terminal circuit units 51, 52, and 53 have the same configuration, apply a predetermined potential to the second input terminal in2, and apply an input signal to the first input terminal in1. When given, a low-pass filter characteristic is exhibited in a predetermined band,
When a predetermined potential is applied to the first input terminal in1 and an input signal is applied to the second input terminal in2, a high-pass filter characteristic is exhibited in a predetermined band. As a specific configuration, for example, a configuration as illustrated in FIG. That is, the resistor 61 is connected in series to the first input terminal in1, the capacitor 62 is connected in series to the second input terminal in2, and the connection point of the resistor 61 and the capacitor 62 is:
It is connected to an output terminal out via a buffer circuit 63. As shown in FIG. 1C, the buffer circuit has a simple configuration in which the base of the transistor Q1 is input, the collector is connected to the power supply line, the emitter is connected to the output terminal, and the current source is connected.

This three-terminal circuit unit has a second input terminal
When a predetermined potential is applied to in2 and an input signal is applied to the first input terminal in1, the transfer function becomes G (S) = (1 / SC) / (R +
(1 / SC)) = 1 / (1 + SCR), and has a low-pass filter characteristic.

When a predetermined potential is applied to the first input terminal in1 and an input signal is applied to the second input terminal in2, the transfer function becomes G (S) = R / (R + (1 / SC)) = SCR / (1
+ SCR) and has a high-pass filter characteristic. Therefore, in the case of the circuit configuration of FIG. 1A, the first three-terminal circuit unit 51 forms a low-pass filter, the second three-terminal circuit unit 52 forms a high-pass filter, and the third three-terminal circuit The unit 53 functions as a combining unit.

FIG. 2 is a circuit specifically showing FIG. 1A. The resistances of the three-terminal circuit units 51, 52, and 53 are represented by R1, R2, and R3, and the capacitances are represented by C1, C2, and C3.
3 and buffer circuits BF1, BF2, BF3
Indicated by. Now, the amplifier 42 multiplies the input X (S) by m,
The amplifier 43 amplifies n times. The inputs of the buffer circuits BF1 and BF2 are V (S) and W (S), respectively.
And the output appearing at the output terminal 44 is defined as Y (S) to determine the transfer function of the trap circuit.

V (S) = [(1 / SC1) / {R1 + (1 / SC1)}] mX (S) + [R1 / {R1 + (1 / SC1)}] Y (S) = mX ( S) / (1 + SC1 R1) + {SC1 R1 / (1 + SC1 R1)} Y (S) (18) W (S) = R2 / {R2 + (1 / SC2)} nX (S) = { SC2R2 / (1 + SC2R2)｝ nX (S) (19) Y (S) = [(1 / SC3) / {R3 + (1 / SC3)}] V (S) + [R3 / ｛R3 + (1 / SC3)}] W (S) = {1 / (1 + SC3R3)} V (S) + {SC3R3 / (1 + SC3R3)} W (S) (20) (18), When V (S) and W (S) are eliminated from the equations (19) and (20), Y (S) = {1 / (1 + SC3R3)}. [{M / (1 + SC1R1)} X (S) + {SC1 R1 / (1 + SC1 R1)} Y (S)] + [S 2 C2 C3 R2 R3 / {(1+ SC2 R2) (1+ SC3 R3)}] X (S) n ... (21) becomes And rearranging the where C1 = C2, R1 = R2, Y (S) / X (S) = (m + S 2 C1 C3 R1 R3 n) / (1+ SC3 R3 + S 2 C1 C3 R1 R3) ... (22) becomes , The numerator = 0, the characteristics of the trap circuit can be obtained.

Even if the input section of the buffer circuit BF3 is used as the output terminal of the trap circuit, the same signal as Y (S) can be obtained, so that the buffer circuit BF3 is not always necessary.

According to the above-described embodiment, the simple configuration 3
Since the terminal circuit unit is used, the number of elements is small and the whole circuit configuration is extremely simple. Also, the design conditions are those that can be easily realized inside the IC, that is, C1
= C2, R1 = R2, which is advantageous in terms of design and cost.

[0032]

As described above, according to the present invention,
The circuit configuration is simple and suitable for incorporating an integrated circuit.
A circuit which is advantageous in terms of cost can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram and a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing the block diagram of FIG. 1 in more detail;

FIG. 3 is a diagram showing a configuration example and a specific circuit example of an active trap circuit.

[Explanation of symbols]

42, 43 ... amplifier, 51, 52, 53 ... three-terminal circuit unit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-55-76955 (JP, A) JP-A-57-63922 (JP, A) JP-A-53-20748 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H03H 11/04

Claims (2)

(57) [Claims] 1. A circuit having two input terminals and one output terminal. When a predetermined potential is applied to one input terminal and an input signal is applied to the other input terminal, a low-pass filter characteristic is exhibited in a predetermined band and output. When a signal corresponding to the characteristic is output to the input terminal, a predetermined potential is applied to the other input terminal, and an input signal is applied to the one input terminal, a high-pass filter characteristic is exhibited in a predetermined band, and the characteristic is output to the output terminal. An active trap circuit comprising a combination of a three-terminal circuit unit that outputs a signal according to the following: a signal supplied to a signal input terminal is supplied to the other input terminal, and a predetermined signal is supplied to the one input terminal. a first 3-terminal circuit unit in which the potential outputs the output signal to the output terminal is supplied, a predetermined potential supplying supplied to an input terminal of the other to the input end signal of the one supplied to the input terminal Output to output end A second three-terminal circuit unit that outputs a signal; an output of the first three-terminal circuit unit is supplied to the other input terminal; and an output of the second three-terminal circuit unit is supplied to the one input terminal. And a third three-terminal circuit unit whose output is supplied to the signal output terminal and which is supplied as the predetermined potential to the other input terminal of the second three-terminal circuit unit. Trap circuit. 2. The three-terminal circuit unit, wherein a first input terminal connects a resistor in series, a second input terminal connects a capacitor in series, and a connection point between the resistor and the capacitor is an output terminal via a buffer circuit. 2. The active type and lap circuit according to claim 1, wherein the active type and the lapping circuit are connected to each other.