JP3156767B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device for a multi-level memory cell.

[0002]

2. Description of the Related Art The prior art of this type of semiconductor memory device includes, for example,
national Solid-State Circuits Conference, ISSCC)
Some are reported on the 75 pages of the proceedings. The semiconductor memory device is intended for high integration of a dynamic semiconductor memory device. For example, if a power supply voltage is Vint, four potentials (Vint, Vint,
2 / 3Vint, 1 / 3int, GND) as shown in FIG.
It operates in accordance with 2-bit data of 1 ',' 10 ',' 01 ', and' 00 '.

FIG. 8 shows a circuit configuration of a memory cell array section and a sense amplifier section of a first example of a conventional semiconductor memory device (see FIG. 1, page 75 of the above-mentioned proceedings, Japanese Patent Application No. 8-083242). FIG. The circuit shown in FIG. 8 shows the configuration of one bit line line pair (BL, BLB). The bit line pair (BL, BLB) is divided into two sections A, B in the transfer gate SWT controlled by the control signal line TG, and the section A side is the upper bit bit line pair (BL1, BL1B), section The B side is a lower-order bit line pair (BL2, BL2
B). Sense amplifier circuits SA1 and SA2 are connected to these divided bit line pairs, respectively.
A coupling capacitance Cc is connected between each bit line pair. The bit line pair (BL1, BL1
The ratio between the parasitic capacitance Cb1 generated in B) and the parasitic capacitance Cb2 generated in the bit line pair (BL2, BL2B) on the section B side is set to 2: 1. FIG. 9 shows a specific circuit configuration for realizing such settings.

In FIG. 9, each bit line pair (BL, BL
B) exists across the memory cell array units 100 and 101 adjacent to each other in the region of the sense amplifier circuit unit 102 across the sense amplifier circuits SA1 and SA2, and each of the memory cell array units 100 and 101 is provided with a transfer gate CTG.
Each is separated into two by U and CTGL.
When the memory cell MC is accessed, the bit line pair (B
L1, BL1B) becomes the upper bit line, and the bit line pair (BL2, BL2B) becomes the lower bit line. Thus, the memory cell array units 100 and 101 are connected to the control signal line CT.
In a circuit divided into two by GU and CTGL, at the time of access, the control signal line CTGU is set to a high active level, the control signal line CTGL is set to a low-in active level, and the parasitic capacitance of the upper bit line pair (BL1, BL1B) is set. The ratio between Cb1 and the parasitic capacitance Cb2 of the lower bit line pair (BL2, BL2B) is set to 2: 1.

FIG. 10 is a diagram showing operation waveforms at the time of reading (including a restore operation) in the circuit shown in FIG. Hereinafter, the read operation of the above-described circuit will be specifically described with reference to FIG. Here, 2/3 Vint information is stored in the memory cell MC of FIG.
The description will be made on the assumption that the information is read.

In the period until time t1, bit line pair BL, B
LB is precharged to 1/2 Vint. Further, during this period, since the control signal line TG is at the high active level, the transfer gate SWT conducts,
Section A and section B are electrically connected.

At time t1, bit line pair (BL, BLB)
Is stopped, and the memory cell array in which the upper bit line pair and the lower bit line pair are present is determined by the address input. At this time, the control signal line CTGU for dividing the memory cell array on the side of the upper bit line pair into two.
Remains at the high active level, but the control signal line CTG divides the memory cell array on the lower bit line pair side into two.
L falls to the low-in active level. At this time, since the control signal line TG is at the high active level, the bit line pair on the section A side and the bit line pair on the section B side are in an electrically connected state.

At the subsequent time t2, the word line WL selected by the address input signal becomes a high active level, and 2/3 Vint, which is the information of the memory cell MC, becomes the bit line B.
Output to L. At this time, the potential of the bit line BL changes from the precharged potential by a very small potential ΔV, and becomes (（Vint + ΔV). For example, the memory cell MC
Is Vint, 1 / 3Vint, 0, the potential of the bit line BL is (1 / 2Vint + 3ΔV), (1 / 2Vint−ΔV),
(1 / 2Vint-3ΔV).

At time t3, when the gate selection signal line TG is set to the low-in active level and the transfer gate SWT is turned off, the section A and the section B are electrically separated. As a result, the bit line BL
Is divided into a bit line BL1 and a bit line BL2, and the bit line BLB is divided into a bit line BL1B and a bit line BL2B.

At the subsequent time t4, the sense amplifier activation signal SAE1 is set to the high active level, and the section A
, The sense amplifier circuit SA1 amplifies the potential difference between the pair of bit lines BL1 and BL1B, and the amplification causes the potential of the bit line BL1 to become Vi.
nt, the potential of the bit line BL1B becomes GND. At this time,
Due to the coupling capacitance Cc, the potential of the bit line BL2B rises by ΔVc with the rise of the potential of the bit line BL1, and the potential of the bit line BL2 rises to the bit line BL1B.
Drops by ΔVc with the potential drop of. That is, the potential of the bit line BL2 is (1 / 2Vint + ΔV−ΔVc), and the potential of the bit line BL2B is (1 / 2Vint + ΔVc).

Here, when the ratio between the coupling capacitance Cc and the memory cell capacitor Cs is adjusted so that ΔVc = ΔV, the bit lines corresponding to the four information of 0, 1 / 3Vint, 2 / 3Vint, and Vint are obtained. The potential difference between the pair (BL2, BL2B) is Δ
V and equal. This potential difference is determined by the bit line pair BL1, B2 before amplification by the sense amplifier circuit SA1.
It is also equal to the minimum value ΔV of the potential difference of L1B.

At the subsequent time t5, the sense amplifier activation signal SAE2 is set to the high active level, and the section B
, The sense amplifier circuit SA2 amplifies the potential difference between the pair of bit lines (BL2, BL2B), and the amplification causes the potential of the bit line BL2 to be GND and the potential of the bit line BL2B to be Vint. Become.

At the subsequent time t6, when the sense amplifier activation signals SAE1 and SAE2 go to the low-inactive level and the sense amplifier circuits SA1 and SA2 are inactivated, the bit line pairs (BL1, BL1B), (BL2, BL
2B) are both in a high impedance state.

At time t7, when the control signal line TG goes high, the transfer gate S
WT conducts, which causes section A and section B
Are equal in potential. Parasitic capacitance Cb1 of bit line pair BL1 and BL1B of section A and section B
The ratio of the parasitic capacitance Cb2 of the bit line pair (BL2, BL2B) is set to 2: 1.
1, the potential of BL2 is Vrest = (2Cb × Vint + Cb × 0) / (2Cb + Cb) = 2 / 3Vint, which is equal to the potential stored in the memory cell MC before reading. During the period from time t5 to t6, the memory cell M
This potential is written into C again.

Thereafter, at time t8, the selected word line WL goes low. Time t7 to t
In the period of 8, data is written again to the data memory cell MC. Then, at time t9, the control signal line CTGL rises to the high active level, and thereafter, the precharge operation of the bit line pair (BL, BLB) is performed, and the read operation ends.

Although the data read operation has been described above, the description of the data write operation will be omitted.

FIG. 11 is a circuit diagram of a memory cell array section and a sense amplifier section in a second example of a conventional semiconductor memory device (see FIG. 2, page 75 of the above-mentioned proceedings, Japanese Patent Application No. 8-352635). FIG. 3 is a diagram showing one set of main bit line pairs. FIG.
In FIG. 1, a portion SSA surrounded by a dotted line is a sub-sense amplifier circuit. The bit line pairs are hierarchized into complementary main bit line pairs and sub bit line pairs, and one main bit line pair includes one main sense amplifier circuit MSA and a plurality of sub sense amplifier circuits SSA. Is connected.

FIG. 12 is a circuit diagram of the circuit shown in FIG.
An operation waveform at the time of data reading is shown, and a reading operation of the circuit will be described below. Here, the cell 1 selected by the word line WL and the sub bit line SBLU is
Description will be made assuming that 2 / 3Vint information is stored and that information is read.

During the period until time t1, the precharge control signal line BBL of the sub-bit line pair is at the high active level, and the sub-bit line pairs (SBLU, SBLBU), (SB
L, SBLB) and (SBLL, SBLBL)
Precharged to 1 / 2Vint level.

At the subsequent time t1, when the precharge control signal line BBL of the sub-bit line pair changes to the low inactive level, the precharge operation of the sub-bit line pair in FIG. 11 stops. At time t1, the control signal line T
Since both GL0 and TGL1 change to the low-inactive level, the sub-bit lines SBL and SBLL and SBLB and SBLBL are both electrically isolated.

Next, at time t2, the control signal line OC for offset cancellation of the sub sense amplifier circuit SSA
S and OCV change as shown in FIG. 12, and the threshold voltage variations of the sense amplifier transistors Tr1 and Tr2 are compensated. Here, for the sake of simplicity, the description will be made on the assumption that there is no variation in the threshold voltage of the sense amplifier transistors Tr1 and Tr2.

At the subsequent time t3, the word line WL selected by the address input signal goes to the high active level, and 2/3 Vint, which is the information of cell 1, becomes the sub-bit line SBL.
Output on U, SBL. At this time, the sub bit line SB
The potentials of LU and SBL fluctuate by a very small potential ΔV from the precharged potential. For example, if the information of cell 1 is Vi
When nt, 1 / 3Vint, 0, the sub-bit lines SBLU, SB
The potential of L fluctuates from the precharged potential by 3ΔV, −ΔV, −3ΔV.

At the subsequent time t4, when the read switch signal RS changes to the high active level as shown in FIG. 12, the transistors Tr5 and Tr6 of the sub sense amplifier circuit SSA are turned on, and the main bit line precharge circuit (not shown) turns on. The potential of the main bit line pair (GBL, GBLB) precharged to 1/2 Vint is lowered according to the gate potential of the sense amplifier transistors Tr1, Tr2, that is, the level of the sub bit line pair (SBL, SBLB). Thereby, the sub-bit line pair (SBL, SBL
B) is applied to the main bit line pair (GBL, GBL).
BLB).

At the subsequent time t5, when the read switch signal RS falls to the low inactive level, the main sense amplifier circuit MSA causes the main bit line pair (GB
L, GBLB) is amplified to Vint or GND level. When the information of the cell 1 is Vint or 2/3 Vint, the bit line GBL is at the Vint level and the bit line GBLB is at the GND level. This indicates a read operation of the upper bits, and indicates that '1' data is read in any case. On the other hand, when the information of the cell 1 is 1/3 Vint or 0, the read operation of the upper bits causes the data to be “0”.
Data is read.

As described above, since the control signal line CPE is at the high active level while the main bit line pair (GBL, GBLB) is amplified between the times t5 and t6, the main capacitance is controlled by the coupling capacitance Cc. Bit line pair (G
The potential of the sub-bit line pair (SBL, SBLB) also fluctuates under the influence of the fluctuation of the potential of BL, GBLB). When the information of the cell 1 is 2/3 Vint, the potential of the sub-bit line SBLB rises by ΔVc with the rise of the potential of the bit line GBL, and the potential of the sub-bit line SLB rises with the fall of the potential of the bit line GBLB.
The potential of BL drops by ΔVc.

Here, similarly to the above-mentioned first conventional example,
When the ratio between the coupling capacitance Cc and the memory cell capacitor Cs is adjusted so that ΔVc = ΔV, Vint, 2 / 3Vi
nt, 1 / 3Vint, 0, sub-bit line pairs (SB
L, SBLB) are all equal to ΔV and are equal.
This potential difference is also equal to the minimum value ΔV of the potential difference between the pair of sub-bit lines (SBL, SBLB) when reading the upper bits.

Subsequently, at time t6, the control signal line T
When GU0 and CPE fall to the low-in active level, the sub-bit line pair (SBL) in the memory cell array unit
U, SBLBU) and the sub sense amplifier circuit SSA are electrically separated. Thereafter, the sub-bit line pair (SB
L, SBLB) is applied to the main bit line pair (GBL, GBL).
B) is no longer affected by the potential fluctuation.

At the subsequent time t7, when the write switch signal WSU rises to the high active level, the potential of the amplified main bit line pair (GBL, GBLB) becomes
The data is written to the sub-bit line pairs (SBLU, SBLBU).

At the subsequent time t8, when the write switch signal WSU falls to the low inactive level, the main bit line pair (GBL, GBLB) is precharged to the 1/2 Vint level.

At the subsequent time t9, the read switch signal RS rises to the high active level again, and the potential difference between the pair of sub-bit lines (SBL, SBLB) is transmitted to the pair of main bit lines (GBL, GBLB).

At the subsequent time t10, the read switch signal RS falls to the low inactive level,
The main bit line pair (GB
L, GBLB) is amplified to Vint or GND level. When the information of the cell 1 is 2/3 Vint or 0, the bit line GBL is at the GND level and the bit line GBLB is at the Vint level. This indicates a lower bit read operation, and indicates that '0' data is read in any case. On the other hand, if the information of cell 1 is Vint or 1 / 3Vi
In the case of nt, '1'
Data is read.

At the subsequent time t11, the write switch signal WSL and the control signal line TGL0 rise to the high active level, and the amplified main bit line pair (GBL,
GBLB) is applied to the sub-bit line pair (SBLL, SBL).
BL) and (SBL, SBLB).

At the subsequent time t12, when the write switch signal WSL falls to the low inactive level and the control signal line TGU0 rises to the high active level, the sub bit line pair (SBLU, SBLB)
U), (SBL, SBLB) and (SBLL, SBLBL) are all connected. Here, the sub-bit line pair (SBLL,
The control signal line TGL1 for dividing the SBLBL into two is at the low-inactive level, and the sub-bit line pair (SBLU,
SBLBU) and sub-bit line pair (SBLL, SBLBL)
Is 2: 1. The parasitic capacitance of the sub-bit line pair (SBL, SBLB) in the sub-sense amplifier circuit SSA is reduced to the sub-bit line pair (SBLU, SBLBU), (SB
LL, SBLBL) and neglecting it as small as compared with the parasitic capacitance of the sub-bit line S when the information of the cell 1 is 2/3 Vint.
The potential of the BLU is Vrest = (2Cb * Vint + Cb * 0) / (2Cb + Cb) = 2/3 Vint, which is equal to the potential stored in the cell 1 before the reading. This potential is written to the cell 1 again in the period from the time t12 to the time t13.

Thereafter, at time t13, the selected word line WL goes low. Then, at time t14, the precharge control signal line BBL of the sub-bit line pair rises to the high active level, and the sub-bit line pairs (SBLU, SBLBU), (SBL,
SBLB), (SBLL, SBLBL) are all 1 / 2Vint
The level is precharged, and the read operation ends.

While the data read operation has been described above, the description of the data write operation is omitted as in the first conventional example.

Next, two points common to the above-mentioned two conventional operation systems will be described.

In each of the first and second conventional examples, the ratio between the coupling capacitance Cc and the memory cell capacitor Cs is adjusted so that ΔVc = ΔV. By setting in this way, the signal voltages at the time of reading the lower bits corresponding to each of the four pieces of information are all equal to ΔV and equal. In the case of '10' and '01', the signal voltage is also equal to the signal voltage ΔV of the upper bit.

In the case of the first conventional example, ΔVc = ΔV
Holds when Cc = 1 / 9Cs holds between the coupling capacitance Cc and the memory cell capacitor Cs. The coupling capacitance Cc satisfying the above equation can be realized by connecting nine memory cell capacitors Cs in series. FIG. 13 shows an example of the configuration.

In the configuration example shown in FIG. 13, in the coupling capacitance forming section in the sense amplifier circuit, between the upper bit line BL1 on the section A side and the lower bit line BL2B on the section B side, and Upper bit line BL1B and lower bit line BL2
, Nine capacitors (memory cell capacitors Cs) each composed of the plate 10 and the stacked polysilicon 11 are connected in series. Specifically, four plates each having the stacked polysilicon formed at two locations and one plate having the stacked polysilicon formed at one location are connected to the capacitance contact portion so that the capacitance of each plate is connected in series. 12 are connected.

On the other hand, in the case of the second conventional example, Δ
Vc = ΔV holds when Cc = 1 / 3Cs holds between the coupling capacitance Cc and the memory cell capacitor Cs. Coupling capacitance Cc that satisfies the above equation
Can be realized by connecting three memory cell capacitors Cs in series. FIG. 14 shows an example of the configuration.

In the configuration example of FIG. 14, the main bit line pair GB in the coupling capacitance forming portion in the sense amplifier circuit is formed.
Between L and the sub-bit line pair SBLB and between the main bit line pair GBLB and the sub-bit line pair SBL, the capacitance (memory cell capacitor Cs) constituted by the plate 20 and the stacked polysilicon 21 is 3 respectively. Are connected in series. Specifically, one plate having the stacked polysilicon formed at two locations and one plate having the stacked polysilicon formed at one location are connected to the capacitor contact so that the capacitance of each plate is connected in series. Part 2
2 are connected. Here, the main bit line pair GBL is a line in which three capacitors are connected in series via a transistor including a diffusion layer 23a and a contact portion 24a (a main bit line pair GBL and a sub bit line pair SBL).
Of the main bit line pair G.
BLB is a line (main bit line pair GBLB and sub bit line pair SBL) in which three capacitors are connected in series via a transistor including a diffusion layer 23b and a contact portion 24b.
Is connected to the capacitance contact portion 22 which is one end of a line connecting between the capacitor contact portion 22. A control signal line CPE (gate line) is connected to the gate of each transistor.

In each of the above-mentioned conventional examples,
4 of '11', '10', '01', '00' as shown in FIG.
When writing two pieces of information into memory cells,
nt, 2/3 Vint, 1/3 Vint, and 0 potential. Therefore, during the write operation, the ratio between the parasitic capacitance Cb1 of the bit line pair corresponding to the upper bit and the parasitic capacitance Cb2 of the bit line pair corresponding to the lower bit is set to 2: 1 to generate this potential. I have. Since the ratio of the parasitic capacitance is set to 2: 1 in this manner, in any of the conventional examples, the memory cell array is formed by the transfer gate by the transfer gate.
It is divided into two parts. For example, in the first conventional example shown in FIG. 9, a memory cell array is divided into two by a transfer gate controlled by control signal lines CTGU and CTGL, and in the second conventional example shown in FIG. The memory cell array is divided into two by the transfer gate controlled by the lines TGU1 and TGL1.

FIG. 15 shows an example of a layout arrangement in which a memory cell array is divided into two by a transfer gate.
Shown in

In the layout arrangement of the transfer gate separation unit shown in FIG. 15, the memory cell array 30 is divided by the transfer gate separation unit 33 into two, a memory cell array unit 31 and a memory cell array unit 32. In each of the memory cell array units 31 and 32, a plurality of word lines 34 and a plurality of bit lines 35 are arranged so as to intersect, and a plate 36 formed between a pair of word lines is provided for each bit line. Is formed. Stack polysilicon 37 is formed on each plate 36, thereby forming a capacitance (memory cell capacitor). Control signal lines 37a and 37b for controlling the transfer gate are provided in the transfer gate separating unit 33 for separating the memory cell array unit 31 and the memory cell array unit 32.
Are arranged so as to cross the bit lines. Each bit line pair 35 is provided with a transistor composed of diffusion layers 38a and 38b and contact portions 39a and 39b, respectively, and having a gate connected to control signal lines 37a and 37b.

[0045]

However, in the case of the conventional example described above, there are the following two problems.

The first problem is that in the coupling capacitance forming section shown in FIGS. 13 and 14, the memory cell capacitor of the coupling capacitance forming section is separated from the memory cell array region and isolated in the sense amplifier circuit. It is a point that is arranged. In the case where the pattern of the memory cell capacitor is isolated in the sense amplifier circuit as described above, process conditions such as exposure and etching in forming the pattern of the memory cell capacitor that is isolated are determined by the memory cell capacitor. The process conditions in the memory cell array region where the capacitor pattern is densely arranged will be different. Therefore, there is a risk that the capacitance value of the memory cell capacitor in the coupling capacitance forming portion is different from the capacitance value of the memory cell capacitor in the memory cell array region. In this case, there is a concern that the sense margin at the time of the read operation is reduced due to the deviation of the reference level from the optimum value.

The second problem is that, in the transfer gate separation structure shown in FIG. 15, a memory cell to be accessed exists adjacent to a transfer gate separation part for separating memory cells. Since there is no memory cell capacitor pattern in the transfer gate separation unit 33, the memory cell arrays 31, 32 in which the memory cell capacitor patterns are densely arranged are arranged.
Process conditions such as exposure and etching are different. Therefore, the process uniformity is disturbed in a region (a region adjacent to the transfer gate separation unit) on both sides of the transfer gate separation unit in the memory cell array unit. For example, in a region (boundary region) on both sides of the transfer gate isolation portion of the memory cell array portion, the exposure shape, the etching shape, and the like become unstable compared to the central region of the memory cell array portion, and the desired shape and device There is a risk that the electrical characteristics cannot be obtained.

In view of the above-mentioned problems, an object of the present invention is to provide
Reduce the effects of isolated placement of memory cell capacitors,
Further, it is an object of the present invention to provide a semiconductor memory device capable of obtaining a sufficient read margin and realizing a high yield by reducing the influence of disturbance of a memory cell capacitor pattern due to separation of a memory cell array.

[0049]

In order to achieve the above object, a first semiconductor memory device according to the present invention comprises complementary first and second bit line pairs and the first bit line pair. A first sense amplifier circuit group respectively connected to
A second bit line pair group connected to the second bit line pair group;
Are connected between the sense amplifier circuit group and the first bit line pair group and the second bit line pair group, each of which includes a plurality of memory cell capacitors connected in series. A semiconductor memory device having a ring capacitance group, wherein the first and second sense amplifier circuit groups are separately provided on both sides of a region where the coupling capacitance group is formed. A dummy pattern of a memory cell capacitor is formed around a region to be formed.

A second semiconductor memory device according to the present invention includes a hierarchical main bit line pair group and a sub bit line pair group, and a main sense amplifier circuit connected to the main bit line pair group. And a sub-sense amplifier circuit group respectively connected to the main bit line pair group and the sub bit line pair group, and a sub sense amplifier circuit group connected between the main bit line pair group and the sub bit line group, respectively. Has a coupling circuit group formed by connecting a plurality of memory cell capacitors and a transfer gate in series, and a coupling capacitance forming region in which a plurality of memory cell capacitors constituting the coupling circuit group are formed In the semiconductor memory device in which the sub sense amplifier circuit group is provided separately on both sides of the memory cell, a dummy memory cell capacitor is provided around the coupling capacitance region. Turn wherein the formed.

According to a third semiconductor memory device of the present invention, there are provided a complementary bit line pair group, a transfer gate group for separating the bit line pair group into two, and the bit line pair via the transfer gate group. A memory cell array comprising a plurality of memory cells connected to a pair group, wherein the memory cell array is provided separately on both sides of a region where the transfer gate group is formed, and controls conduction of the transfer gate group. In the semiconductor memory device in which writing of potential to each memory cell of the memory cell array is controlled by the method, a dummy pattern of a memory cell capacitor is formed in a region where the transfer gate group is formed.

A fourth semiconductor memory device according to the present invention comprises a complementary bit line pair group, a transfer gate group for separating each of the bit line pair groups into two, and the bit line pair via the transfer gate group. A memory cell array comprising a plurality of memory cells connected to a pair group, wherein the memory cell array is provided separately on both sides of a region where the transfer gate group is formed, and controls conduction of the transfer gate group. In a semiconductor memory device in which writing of a potential to each memory cell of a memory cell array is controlled by a memory cell capacitor, a region adjacent to a region where the transfer gate group is formed in a region where the memory cell array is formed is provided with a memory cell capacitor. A semiconductor memory device, wherein the dummy pattern is formed.

(Operation) In the present invention configured as described above, the dummy pattern of the memory cell capacitor is formed around the area where the transfer gate group is formed. The memory cell capacitor in the portion does not become isolated from the memory cell capacitor in the memory cell array region. Therefore, the amount of change in the process condition due to the difference in the pattern of the memory cell capacitor is reduced, and the capacitance value of the memory cell capacitor in the coupling capacitance forming portion is substantially equal to the capacitance value of the memory cell capacitor in the memory cell array region.

In the invention in which the dummy pattern of the memory cell capacitor is formed in the area where the transfer gate group is formed, the memory divided by the transfer gate group formation area due to the formation of the dummy pattern The pattern of each memory cell capacitor in the cell array does not become isolated due to the division of the area. Therefore, the variation in the forming process conditions for each memory cell capacitor of the divided memory cell array is reduced, and the capacitance values of those memory cell capacitors are substantially the same.

Further, in the invention in which the dummy pattern of the memory cell capacitor is formed in the region where the memory cell array is formed and in the region adjacent to the region where the transfer gate group is formed, the influence of the disturbance of the forming process conditions is provided. Will occur only in the dummy pattern. Therefore, among the memory cell capacitors of the divided memory cell arrays, the possibility of obtaining a desired shape and electrical characteristics of the patterns of all the memory cell capacitors to be accessed is improved.

[0056]

Next, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) The semiconductor memory device of this embodiment has exactly the same circuit configuration as that of the first conventional example shown in FIG. 8 and FIG. The operation waveform of ()) is exactly the same as the operation waveform shown in FIG. Therefore, the description of the operation waveform is omitted here, and the basic circuit configuration and the layout arrangement of the coupling capacitance forming unit will be described.

This semiconductor memory device comprises a complementary first and second bit line pair group, a first sense amplifier circuit group respectively connected to the first bit line pair group, and a second bit line group. A second sense amplifier circuit group respectively connected to the line pair group, a transfer gate group connecting the first bit line pair group and the second bit line pair group, and a first bit line pair group And a second bit line pair group, each having a coupling capacitance group formed by connecting a plurality of memory cell capacitors in series. In this semiconductor memory device, the amplification result of the first sense amplifier circuit group activated first is fed back to the sense level of the second sense amplifier circuit group activated thereafter by the function of the coupling capacitor. ,
The multi-level operation is realized by performing the read operation twice. The layout is such that a region where the first and second sense amplifier circuit groups are formed exists on both sides of the region where the coupling capacitance group is formed. Hereinafter, a specific configuration of the layout arrangement will be described.

FIG. 1 shows a layout of a coupling capacitance forming section in a sense amplifier circuit of the semiconductor memory device according to the first embodiment of the present invention. In FIG.
Although only the configuration of one bit line pair is shown, a similar configuration is actually provided for a plurality of bit line pairs.

A coupling capacitance forming section 110 is formed to divide the sense amplifier sections 102a and 102b. The coupling capacitance forming unit 110 is configured to include the bit line pair BL1 for the upper bit on the section A side and the section B
Nine capacitors (memory cell capacitors Cs) composed of the plate 10 and the stacked polysilicon 11 are connected in series between the lower-order bit line pair BL2B on the side,
Similarly, the bit line pair BL for higher-order bits on the section A side
1B and bit line pair BL2 for lower bits on section B side
, Nine capacitors (memory cell capacitors Cs) are connected in series. With this configuration, Cc = 1 / 9Cs is established between the coupling capacitance Cc and the memory cell capacitor Cs.

Around the coupling capacitance forming section 110, a plurality of dummy patterns 103 of the memory cell capacitor are arranged. These dummy patterns 103 are also composed of the plate 10 and the stacked polysilicon 11, similarly to the capacitance of the coupling capacitance forming section 110 (memory cell capacitor Cs).

With the above configuration, the coupling capacitor forming section 110 and the memory cell array section (10 in FIG. 9) in which the patterns of the memory cell capacitors are densely arranged.
(0, 101), the fluctuation of the process conditions at the time of exposure, etching, etc. is reduced, and the capacitance value of the capacitance (memory cell capacitor Cs) of the coupling capacitance forming unit 110 and the capacitance value of the memory cell capacitor Cs of the memory cell array unit Are of the same order.

In the configuration shown in FIG. 1, two dummy patterns are arranged on both sides (in the direction of the bit line) of the coupling capacitance forming portion, however, the number of the dummy patterns is not particularly limited. Is not
Desirably, the capacitance value of the memory cell capacitor in the coupling capacitance forming unit is set to a minimum value that is substantially equal to the capacitance value of the memory cell capacitor in the memory cell array region.

(Embodiment 2) The semiconductor memory device of the present embodiment has exactly the same circuit configuration as that of the second conventional example shown in FIG. 11, and the operation at the time of reading (including the restore operation) is performed. The waveform is exactly the same as the operation waveform shown in FIG. Therefore, the description of the operation waveform is omitted here, and the basic circuit configuration and the layout arrangement of the coupling capacitance forming unit will be described.

This semiconductor memory device has hierarchical main bit line pairs and sub bit line pairs, a main sense amplifier circuit group connected to the main bit line pairs, and a main bit line group. A sub-sense amplifier circuit group connected to the pair group and the sub-bit line pair group, and a plurality of memory cell capacitors and a transfer gate each connected between the main bit line pair group and the sub-bit line group. Are connected in series. In this semiconductor memory device, the amplification result of the main sense amplifier circuit group that is activated for the first time is fed back to the second sense level of the sub sense amplifier circuit group by the function of the coupling capacitor, and the read operation is performed for two times. The multi-level operation is realized by performing the above operations. The layout arrangement is such that the region where the sub-sense amplifier circuit group is formed is located on both sides of the region where the coupling circuit group is formed. Hereinafter, a specific configuration of the layout arrangement will be described.

FIG. 2 shows a layout arrangement of a coupling capacitance forming section in a sense amplifier circuit of a semiconductor memory device according to a second embodiment of the present invention. In FIG.
Although only the configuration of one bit line pair is shown, a similar configuration is actually provided for a plurality of bit line pairs.

A coupling capacitance forming section 210 is formed so as to divide the sub sense amplifier sections 201 and 202. The coupling capacitance forming section 210 is provided between the main bit line pair GBL and the sub bit line pair SBLB.
0 and the stack polysilicon 21 (memory cell capacitor Cs) are connected in series, and similarly, a capacitor (memory cell capacitor Cs) is connected between the main bit line pair GBLB and the sub bit line pair SBL. Cs) are connected in series. Here, the main bit line pair GB
L is a line (a line connecting between the main bit line pair GBL and the sub bit line pair SBLB) in which three capacitors are connected in series via a transistor including the diffusion layer 23a and the contact portion 24a. Similarly, the main bit line pair GBLB is connected to the capacitive contact portion 22 which is one end.
One end of a line in which three capacitors are connected in series (a line connecting between main bit line pair GBLB and sub bit line pair SBL) via a transistor including diffusion layer 23b and contact portion 24b Capacitance contact part 2
2 are connected. A control signal line CPE (gate line) is connected to the gate of each transistor. With this configuration, Cc = 1 / 3Cs is established between the coupling capacitance Cc and the memory cell capacitor Cs.

Around the coupling capacitance forming section 210, a plurality of dummy patterns 203 of the memory cell capacitor are arranged. These dummy patterns 203 are also formed by forming the stack polysilicon 21 on the plate 20, similarly to the capacitance (memory cell capacitor Cs) of the coupling capacitance forming section 210.

With the above-described configuration, the coupling capacitance forming section 21 can be formed in the same manner as in the first embodiment.
0 and the memory cell array unit (see FIG. 11) in which the patterns of the memory cell capacitors are densely arranged, the variation in the process conditions during the exposure and the etching is reduced, and the capacity of the coupling capacitance forming unit 210 (memory The capacitance value of the cell capacitor Cs) and the capacitance value of the memory cell capacitor Cs in the memory cell array section are substantially the same.

The configuration shown in FIG. 2 has a configuration in which two dummy patterns are arranged on both sides (in the direction of the bit line) of the coupling capacitance forming portion, similarly to the configuration shown in FIG. 1 described above. Although the number of patterns is not particularly limited, it is preferable that the number of patterns be such that the capacitance value of the memory cell capacitor in the coupling capacitance forming portion is substantially equal to the capacitance value of the memory cell capacitor in the memory cell array region. Set to value.

(Embodiment 3) The semiconductor memory device of this embodiment has exactly the same circuit configuration as that shown in FIG. 9 described above, and the operation waveform at the time of reading (including the restore operation) is also the same as that shown in FIG. The operation waveforms are exactly the same as those shown in FIG. Since the basic configuration is the same as that of the first embodiment, here, only the layout arrangement of the transfer gate separation unit in the memory cell array will be described.

FIG. 3 shows a layout of a transfer gate isolation portion in a memory cell array of a semiconductor memory device according to a third embodiment of the present invention.

In this layout, the memory cell array 30 is divided by the transfer gate separating section 33 into two memory cell sections 31 and 32.
Are separated into two. In the memory cell array unit 31 and the memory cell array unit 32, a plurality of word lines 34 and a plurality of bit lines 35 are arranged to intersect, and a plate 36 formed between a pair of word lines is provided between each bit line. It is formed every time. Stack polysilicon 37 is formed on each plate 36, thereby forming a capacitance (memory cell capacitor). Control signal lines 37a and 37b for controlling transfer gates are arranged in the transfer gate separating unit 33 for separating the memory cell array unit 31 and the memory cell array unit 32 so as to cross the bit lines. Each bit line pair 35 has a diffusion layer 38a, 38b and a contact portion 39a, 39b, respectively.
And a transistor having a gate connected to the control signal lines 37a and 37b.

The above configuration is the same as that shown in FIG. In the present embodiment, in addition to the configuration, a plurality of dummy patterns 40 of the memory cell capacitor are arranged in the transfer gate separating section 33. In these dummy patterns 40 as well, the capacitance is constituted by the plate 36 and the stack polysilicon 37. By providing the dummy pattern in the transfer gate separation unit 33 in this manner, the transfer gate separation unit 33 does not have any pattern of the memory cell capacitor unlike the conventional example, and the pattern of the memory cell capacitor does not exist. Disturbance of the forming process is reduced.

(Embodiment 4) In the above-described third embodiment, by arranging the dummy pattern 40 of the memory cell capacitor in the transfer gate separation section 33,
Although the memory cell capacitor pattern in the memory cell array part adjacent to the transfer gate separation part 33 is prevented from being disturbed, the dummy pattern is formed in the area adjacent to the transfer gate separation part in the memory cell array part where the formation process is disturbed. May be formed.

FIG. 4 shows a layout arrangement of a transfer gate isolation portion in a memory cell array in a semiconductor memory device according to a fourth embodiment of the present invention.
This layout arrangement is different from the layout arrangement shown in FIG.
Instead of arranging the dummy pattern 40 of the memory cell capacitor, a dummy pattern of the memory cell capacitor which is not accessed is provided in a region of the memory cell array units 31 and 32 adjacent to the transfer gate separating unit 33. It is characterized by. More specifically, two dummy word line pairs 41a and 41b are formed in regions of the memory cell array units 31 and 32 adjacent to the transfer gate separation unit 33, respectively, and each of the dummy word line pairs 41a and 41b is , A dummy pattern 42 of a memory cell capacitor which is not accessed.

In the above configuration, the dummy pattern 42 which is not accessed is provided in a portion where the exposure shape and the etching shape in the memory cell array portion become unstable, that is, in a region adjacent to the transfer gate separation portion. Therefore, the influence of the disturbance in the formation process occurs only in these dummy patterns 41.
Therefore, in the memory cell array units 31 and 32 of the present embodiment,
A memory cell capacitor having a stable shape and electrical characteristics of the element can be obtained.

In this embodiment, the memory cell array units 31 and 3
2, two rows of dummy patterns are present in portions located on both sides of the transfer gate separating section 33. The number of dummy patterns depends on the design due to the influence of the disturbance of the memory cell capacitor pattern accompanying the memory cell array separation. It is desirable to set in consideration of the area covered by.

(Embodiment 5) The semiconductor memory device of this embodiment has exactly the same circuit configuration as that shown in FIG. 11 described above, and the operation waveform at the time of reading (including the restore operation) is also the same as that shown in FIG. The operation waveforms are exactly the same as those shown in FIG. Since the basic configuration is the same as that of the above-described second embodiment, only the layout arrangement of the transfer gate separation unit in the memory cell array will be described here.

FIG. 5 shows a layout arrangement of transfer gate isolation sections in a memory cell array of a semiconductor memory device according to a fifth embodiment of the present invention. The layout arrangement shown in the figure is the same as the layout arrangement shown in FIG. That is, by arranging the dummy pattern 40 of the memory cell capacitor in the transfer gate separation unit 33, the memory cell capacitor pattern in the memory cell array part adjacent to the transfer gate separation unit 33 is prevented from being disturbed.

With this configuration, as in the case of the third embodiment described above, the transfer gate separating section 33 eliminates the absence of the memory cell capacitor pattern at all unlike the conventional example. The disturbance of the cell capacitor pattern is reduced.

(Embodiment 6) In the above-described fifth embodiment, similarly to the above-described fourth embodiment, instead of disposing the dummy pattern 40 of the memory cell capacitor in the transfer gate separating portion 33, the memory By providing a dummy pattern of a memory cell capacitor which is not accessed in a region of the cell array units 31 and 32 adjacent to the transfer gate separating unit 33, a good memory cell capacitor pattern can be obtained. it can. FIG. 6 shows a specific circuit configuration.

The layout arrangement shown in FIG.
Is similar to the layout arrangement shown in FIG. That is, the dummy pattern 4 of the memory cell capacitor which is not accessed is located in the region of the memory cell array portions 31 and 32 adjacent to the transfer gate separating portion 33.
2 to prevent the influence of the disturbance of the forming process by the dummy patterns 42.

Also in this embodiment, the memory cell array unit 3
Regarding the number of dummy patterns 1 and 32 formed in the portions located on both sides of the transfer gate separation section 33, the area affected by the disturbance of the memory cell capacitor pattern accompanying the separation of the memory cell array is taken into consideration according to the design. It is desirable to set.

[0085]

As described above, in the semiconductor memory device of the present invention, the area around the coupling capacitance forming portion is
The presence of the dummy pattern of the memory cell capacitor improves the possibility that the capacitance value of the memory cell capacitor in the coupling capacitance forming portion becomes substantially equal to the capacitance value of the memory cell capacitor in the memory cell array region. Therefore, by setting the optimum reference level, there is an effect that a sufficient read margin can be obtained and a high yield can be realized.

Further, in the semiconductor memory device of the present invention, since the dummy pattern of the memory cell capacitor is provided in or around the transfer gate separating portion, the memory cell to be accessed is not included in the memory cell array due to the memory cell array separation. The effect of disturbance of the capacitor pattern is reduced. Therefore, there is an effect that desired shapes and electrical characteristics of elements can be obtained for all memory cells to be accessed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a layout arrangement of a coupling capacitance forming section in a sense amplifier circuit in a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a layout arrangement of a coupling capacitance forming section in a sense amplifier circuit in a semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a layout arrangement of transfer gate isolation units in a memory cell array in a semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a layout arrangement of a transfer gate separation unit in a memory cell array in a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a layout arrangement of a transfer gate separation unit in a memory cell array in a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 6 is a diagram showing a layout arrangement of transfer gate isolation units in a memory cell array in a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of a write level to a memory cell;

FIG. 8 is a diagram showing a circuit configuration of a memory cell array section and a sense amplifier section in a first example of a conventional semiconductor memory device.

9 is a diagram showing a separation structure of a memory cell array in the circuit configuration shown in FIG.

FIG. 10 shows a conventional semiconductor memory device shown in FIG.
FIG. 9 is a diagram showing operation waveforms at the time of data reading.

FIG. 11 is a diagram showing a circuit configuration of a memory cell array section and a sense amplifier section in a second example of a conventional semiconductor memory device.

FIG. 12 is a diagram showing operation waveforms at the time of data reading in the conventional semiconductor memory device shown in FIG.

FIG. 13 shows a conventional semiconductor memory device shown in FIG.
FIG. 3 is a diagram illustrating a layout arrangement of a coupling capacitance forming unit in a sense amplifier circuit.

14 is a diagram showing a layout arrangement of a coupling capacitance forming section in a sense amplifier circuit in the conventional semiconductor memory device shown in FIG. 11;

FIG. 15 is a diagram showing a layout layout of a transfer gate separation unit in a memory cell array in the related art.

[Explanation of symbols]

 10, 20, 36 Plate 11, 21, 37 Stacked polysilicon 12, 22 Capacitance contact part 30 Memory cell array 31, 32 Memory cell array part 33 Transfer gate separation part 34 Word line 35 Bit line 37a, 37b Control signal line 38a, 38b Diffusion Layers 39a, 39b Contact portions 40, 42, 103, 203 Dummy patterns 41a, 41b Dummy word lines

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 27/108 G11C 11/56 H01L 21/8242

Claims (8)

(57) [Claims] 1. A first group of complementary bit lines and a second group of bit lines, a first sense amplifier circuit group connected to the first pair of bit lines, and a second pair of bit lines. A second sense amplifier circuit group connected to the respective groups, and a plurality of memory cell capacitors each connected between the first bit line pair group and the second bit line pair group. A semiconductor memory device having a coupling capacitance group configured to be connected in series, wherein the first and second sense amplifier circuit groups are separately provided on both sides of a region where the coupling capacitance group is formed 3. The semiconductor memory device according to claim 1, wherein a dummy pattern of a memory cell capacitor is formed around a region where the coupling capacitance group is formed. 2. The semiconductor memory device according to claim 1, wherein said first and second bit line pairs are respectively separated into two groups, and said second transfer gate group. A first memory cell array including a plurality of memory cells connected to the first bit line pair group via a gate group; and a second memory cell array connected to the second bit line pair group via the third transfer gate group A second memory cell array composed of a plurality of memory cells, wherein the first memory cell array is provided separately on both sides of a region where the second transfer gate group is formed; The second memory cell array is separately provided on both sides of the region where the transfer gate group is formed, and controls conduction of the second and third transfer gate groups. By doing so, writing of potential to each memory cell of the first and second memory cell arrays is controlled, and a memory is provided in each of the regions where the second and third transfer gate groups are formed. A semiconductor memory device, wherein a dummy pattern of a cell capacitor is formed. 3. The semiconductor memory device according to claim 1, wherein said first and second bit line pairs are separated into two, respectively, and said second transfer gate group and said second transfer gate group. A first memory cell array including a plurality of memory cells connected to the first bit line pair group via a gate group; and a second memory cell array connected to the second bit line pair group via the third transfer gate group A second memory cell array composed of a plurality of memory cells, wherein the first memory cell array is provided separately on both sides of a region where the second transfer gate group is formed; The second memory cell array is provided separately on both sides of the region where the transfer gate group is formed, and the transfer of the second and third transfer gate groups is performed. Is controlled to control writing of a potential to each memory cell of the first and second memory cell arrays. In each of the regions where the first and second memory cell arrays are formed, A semiconductor memory device, wherein a dummy pattern of a memory cell capacitor is formed in a region adjacent to a region where the second and third transfer gate groups are formed. 4. A hierarchical main bit line pair group and sub bit line pair group, a main sense amplifier circuit group respectively connected to the main bit line pair group, and the main bit line pair group. And a sub-sense amplifier circuit group respectively connected to the sub-bit line pair group, and a plurality of memory cell capacitors and a transfer gate respectively connected between the main bit line pair group and the sub-bit line group. And a coupling circuit group configured by serially connecting the sub-sense amplifier circuit groups on both sides of a coupling capacitance forming region in which a plurality of memory cell capacitors constituting the coupling circuit group are formed. Wherein a dummy pattern of a memory cell capacitor is formed around the coupling capacitance region. Semiconductor memory device. 5. The semiconductor memory device according to claim 4, wherein said sub-bit line pair group is set at a distance of two from said sub-sense amplifier circuit group.
A first and a second transfer gate group separated at a location, and a plurality of memory cells connected to one of the sub-bit line pairs via a fourth transfer gate group.
And a second memory cell array composed of a plurality of memory cells connected to the other of the sub-bit line pair group via a fifth transfer gate group, wherein the fourth transfer gate The first memory cell array is provided separately on both sides of a region where a group is formed, and the second memory cell array is provided separately on both sides of a region where the fifth transfer gate group is formed, By controlling conduction of the fourth and fifth transfer gate groups, writing of a potential to each memory cell of the first and second memory cell arrays is controlled, and the fourth and fifth transfer gate groups are controlled. A dummy pattern of a memory cell capacitor is formed in each area where a transfer gate group is formed. That the semiconductor memory device. 6. The semiconductor memory device according to claim 4, wherein said sub-bit line pair group is set at a distance of two from said sub-sense amplifier circuit group.
A first and a second transfer gate group separated at a location, and a plurality of memory cells connected to one of the sub-bit line pairs via a fourth transfer gate group.
And a second memory cell array composed of a plurality of memory cells connected to the other of the sub-bit line pair group via a fifth transfer gate group, wherein the fourth transfer gate The first memory cell array is provided separately on both sides of a region where a group is formed, and the second memory cell array is provided separately on both sides of a region where the fifth transfer gate group is formed, By controlling conduction of the fourth and fifth transfer gate groups, writing of a potential to each memory cell of the first and second memory cell arrays is controlled, and the first and second transfer gate groups are controlled. Adjacent to the region where the fourth and fifth transfer gate groups are formed in each region where the memory cell array is formed The band, the semiconductor memory device characterized by the dummy pattern of the memory cell capacitor has been formed. 7. A complementary bit line pair group, a transfer gate group for separating the bit line pair group into two, and a plurality of memories connected to the bit line pair group via the transfer gate group. A memory cell array composed of cells, wherein the memory cell array is separately provided on both sides of a region where the transfer gate group is formed, and by controlling conduction of the transfer gate group, the memory cell array is connected to each memory cell of the memory cell array. A semiconductor memory device in which writing of a potential is controlled, wherein a dummy pattern of a memory cell capacitor is formed in a region where the transfer gate group is formed. 8. A complementary bit line pair group, a transfer gate group for separating the bit line pair group into two, and a plurality of memories connected to the bit line pair group via the transfer gate group. A memory cell array composed of cells, wherein the memory cell array is separately provided on both sides of a region where the transfer gate group is formed, and by controlling conduction of the transfer gate group, the memory cell array is connected to each memory cell of the memory cell array. In the semiconductor memory device in which the writing of the potential is controlled, in a region where the memory cell array is formed, a region adjacent to a region where the transfer gate group is formed,
A semiconductor memory device, wherein a dummy pattern of a memory cell capacitor is formed.