JP3156689B2 - UPC / shaper circuit in ATM transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchro
Nous Transfer Mode), which relates to a UPC / shaper circuit in an ATM transmission apparatus that adjusts a variation in cell intervals in a connection.

[0002]

2. Description of the Related Art Conventionally, in an ATM transmission system, a shaper process and a bandwidth of an input connection which reduce burstiness of connection traffic and increase network use efficiency by adjusting a variation of a cell interval in one connection. There is a UPC (Usage Parameter Control) process for monitoring that the data is within the contracted band. In the shaper processing and the UPC processing, there are parameters (traffic parameters) necessary for performing the processing for each connection, and there is a memory for holding the traffic parameters. As shown in FIG. 11, the memory holds traffic parameters (M [bit]) of N management connections.

[0003]

By the way, the contents of the traffic parameters include an average cell interval and a minimum cell interval in one connection, which are approximately 20 bits or more in terms of the number of bits. Therefore, in the related art, as described above, since the traffic parameters (M [bit]) of the N management connections are simply held, if the number of connections managed by the ATM transmission device increases by one, the traffic parameters are changed. Since the memory area for management increases and the hardware scale increases, there has been a problem how to suppress the increase in the memory scale when the number of connections increases.

[0004] The present invention has been made in view of the above circumstances, and it is possible to suppress an increase in the memory size when the number of connections increases, and to reduce the memory size when a limited number of connections are managed. It is an object to provide a UPC / shaper circuit in a device.

[0005]

In order to solve the above-mentioned problems, the invention according to the first aspect of the present invention is an AT which adjusts a variation in a cell interval of a connection in an ATM transmission system.
In the UPC / shaper circuit in the M transmission device,
Traffic parameters are similar for each traffic characteristic
And upper-level storage means for sharing and storing the upper bits of the traffic parameters necessary for performing the UPC / shaper processing, and lower-order bits of the traffic parameters other than the higher-order bits. Low-order storage means for holding for each connection ,
When a cell is received, connection information is received from the received cell.
And based on the connection information,
Traffic parameters from each of the storage means and the lower-order storage means.
The meter is pulled out and combined, and the combined traffic
UPC / shape for received cells based on parameters
It is characterized by performing par processing and outputting .

Further, according to the invention described in claim 2, according to claim 1,
In the UPC / shaper circuit of the ATM transmission device described above, the upper storage means classifies and stores S upper bits of the traffic parameter.

[0007] According to the third aspect of the present invention, the first aspect of the present invention.
3. The UPC / shaper circuit according to claim 2, wherein said lower storage means stores upper bits corresponding to lower bits of said traffic parameter in said upper storage means.
It is characterized in that attribute information indicating which of the upper bits classified into the individual bits belongs is stored for each of the lower bits.

Further, according to the invention described in claim 4, according to claim 1,
4. The UPC / shaper circuit according to any one of claims 1 to 3, wherein the storage control means reads out traffic parameters from the upper storage means and the lower storage means based on connection information obtained from a received cell; And a combining means for combining the upper bits and the lower bits of the traffic parameter read by (1).

According to the present invention, the upper-level storage means includes a UPC /
Upper bits of traffic parameters necessary for performing the shaper processing are shared and held. Further, the lower-order storage unit holds, for each connection, lower-order bits of the traffic parameter other than the upper-order bit. The UPC / shaper circuit, based on the connection information obtained from the received cell, uses the traffic parameter obtained by combining the upper bits and the lower bits read from the upper storage means and the lower storage means, and Is subjected to UPC processing / shaper processing. Therefore, it is possible to suppress an increase in the memory scale when the number of connections is increased, and to reduce the memory scale when limited connection management is performed.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. In general, the characteristics of information such as voice and images are limited in the amount of information per unit time, and the digital coding method and coding speed can be categorized. Therefore, there are several types of traffic parameters used for shaper processing and UPC processing. Can be classified. For example, when there are two connections, each having a bandwidth of 38.88 MHz, the traffic parameters for these are the same.

In the present invention, CB in which the generation of information is constant
AT that manages R (Constant Bit Rate) traffic
In the M transmission device, using the fact that the traffic parameter has a similar value for each traffic characteristic, the upper bit of the traffic parameter setting data is held in another memory or a register, so that the number of bits of the traffic parameter setting data is And reduce the scale of hardware or increase in hardware scale when the number of connections increases.

A. First embodiment A-1. Configuration of First Embodiment FIG. 1 is a block diagram showing an overall configuration according to a first embodiment of the present invention. Here, a description will be given on the assumption that a configuration in which the same type of traffic parameter is set in all connections. In the figure, the UPC / shaper circuit 1
It comprises a UPC / shaper processing unit 2, a memory control unit 3, an upper management memory 4, and a lower management memory 5.

The UPC / shaper processing unit 2 uses a traffic parameter to be described later to
C processing or shaping processing is performed, and cells are output. The memory control unit 3 includes a UPC / shaper processing unit 2
The interface processing is performed for reading the traffic parameters from the. More specifically, the memory control unit 3 sets the setting data from the management system in the upper management memory 4 and the lower management memory 5 described below,
Based on the connection information from the C / shaper processing unit 2, data is extracted from the upper management memory 4 and the lower management memory 5, and the extracted data is sent to the UPC / shaper processing unit 2.

The upper management memory 4 holds the upper bits (A [bit]) of the traffic parameters of M [bit]. The lower management memory 5 holds the lower bits (MA [bit]) of the traffic parameter. Note that the upper management memory 4 may have a configuration in which data is held in a register (flip-flop) instead of a memory. In the upper management memory 4, the upper bits (A [bit]) of the traffic parameter of M [bit] are shared and held. As a result, as shown in FIG. 2, for example, the shaded area can be reduced by the amount shared.

A-2. Operation of First Embodiment Next, the operation of the present embodiment will be described in detail. FIG.
5 is a flowchart for explaining an operation in setting a traffic parameter. First, the upper bits of the traffic parameters are set in the memory controller 3 by the management system (step A1). Memory control unit 3
Sets the upper bits of the traffic parameter in the upper management memory 4 (step A2). Next, the management system sets the lower bits of the traffic parameter of the connection to the memory controller 3 (step A).
3) The memory control unit 3 sends the lower bi of the traffic parameter of the relevant connection to the lower management memory 5.
t is set (step A4).

FIG. 4 is a flowchart for explaining the operation when the UPC / shaper circuit receives a cell. When the UPC / shaper processing unit 2 receives a cell (step B1), it extracts connection information from the received cell (step B2) and outputs the extracted connection information to the memory control unit 3 (step B3). The memory control unit 3 extracts traffic parameters from each of the upper management memory 4 and the lower management memory 5 based on the connection information supplied from the UPC / shaper processing unit 2 (step B4).

Next, the memory control unit 3 combines the extracted parameters of the upper management memory 4 and the lower management memory 5 and outputs them to the UPC / shaper processing unit 2 (step B5). The UPC / shaper processing unit 2 performs UPC / shaper processing on the received cells based on the traffic parameters supplied from the memory control unit 3 (step B6), and outputs the cells downstream after the processing is completed (step B6). Step B7).

B. Second Embodiment Next, a second embodiment of the present invention will be described. Here, a description will be given of a case where the higher-order configuration data (higher-order bits) of N management connections are classified into S (N ≧
S). The configuration of the circuit is the same as that of the first embodiment shown in FIG. As a precondition, similar traffic parameters are set for the connections of each group classified into S, and the management system (not shown) and the memory control unit 3 determine that the N connections have S connections. It is assumed that information on which group belongs is held (where it is possible to recognize where the connection belongs to S connections from the connection information).

B-1. Configuration of Second Embodiment FIG. 5 is a conceptual diagram showing a memory configuration used in the second embodiment. In the figure, the traffic parameter of M [bit] of N management connections is (N / S)
The individual bits are shared, and the upper bit (A [bit]) is used as a common data bit. That is, the upper management memory 4
Is the upper bits of the traffic parameters classified into S
(A [bit]). The addresses of the upper management memory 4 are managed in N / S connections in ascending order.
Further, the lower management memory 5 stores M connections of N connections.
Lower bits (M-
A [bit]).

B-2. Operation of Second Embodiment FIG. 6 is a flowchart illustrating an operation of setting a traffic parameter according to the second embodiment of the present invention. The management system (not shown) calculates where the connection of the traffic parameter to be set belongs to the S classifications, that is, calculates the address of the upper management memory 4 (step C1), and stores the upper bit of the traffic parameter in the memory. The setting is made for the control unit 3 (step C2). The memory control unit 3 sets the upper bits of the traffic parameter in the upper management memory 4 (Step C3).

Next, the management system (not shown) sets the lower bit of the traffic parameter of the connection to the memory controller 3 (step C4). The lower bits of the traffic parameter of the connection are set (step C5).

Next, FIG. 7 shows the second embodiment of the present invention.
5 is a flowchart for explaining an operation when the PC / shaper circuit 1 receives an input cell. UP
When a cell is received by the C / shaper processing unit 2 (step D1), connection information is extracted from the received cell (step D2), and the extracted connection information is output to the memory control unit 3 (step D3). When the connection information is supplied from the UPC / shaper processing unit 2, the memory control unit 3 calculates the address of the traffic parameter to be extracted from the upper management memory 4 based on the connection information (step D4). The traffic parameters are extracted from each of the lower management memories 5 (step D5).

Next, the memory control unit 3 combines the extracted parameters of the upper management memory 4 and the lower management memory 5 and outputs them to the UPC / shaper processing unit 2 (step D6). The UPC / shaper processing unit 2 performs the following processing based on the traffic parameters supplied from the memory control unit 3.
The UPC / shaper process is performed on the received cell (step D7), and after the process, the cell is output downstream (step D8).

C. Third Embodiment Next, a third embodiment of the present invention will be described. In addition,
Also in the third embodiment, as in the second embodiment, the management system (not shown) classifies the higher-order configuration data (upper-order bits) of N management connections into S, and sets S traffic parameters to be set. Of the memory control unit 3 based on the information. Also, S is the second
Similar to the embodiment, it is assumed that the value is sufficiently smaller than N (N ≧ S).

C-1. Configuration of Third Embodiment FIG. 8 is a conceptual diagram showing a memory configuration used in the third embodiment. The configuration of the UPC / shaper circuit is the same as that of the first embodiment shown in FIG. In the third embodiment, as shown in FIG. 8, the upper management memory 4 classifies the upper A [bit] of the traffic parameters of N connections into S, and ranks the upper A of the traffic parameters classified into the S connections. bit (A [bi
t]). The lower management memory 5 stores M [bit]
Lower bits of the traffic parameters of the
Indicates where each of the S belongs to
t (address bit of the upper management memory 4).

C-2. Operation of Third Embodiment FIG. 9 is a flowchart illustrating an operation of setting a traffic parameter according to the third embodiment of the present invention. The management system (not shown) calculates where the connection of the traffic parameter to be set belongs to among the S classifications, that is, calculates the address of the upper management memory 4 (step E1), and performs memory control on the upper bit of the traffic parameter. The setting is made for the unit 3 (step E2). The memory control unit 3 sets the upper bit of the traffic parameter in the upper management memory 4 (step E3). Next, the management system (not shown) adds the address of the upper management memory 4 to the lower bit of the traffic parameter of the corresponding connection (step E4), and sets it to the memory controller 3 (step E).
5). The memory control unit 3 sets the lower bit of the traffic parameter of the connection and the address of the upper management memory 4 in the lower management memory 5 (step E).
6).

FIG. 10 shows a UPC according to the third embodiment.
6 is a flowchart for describing an operation when an input cell is received in the / shaper circuit 1. UPC /
When a cell is received by the shaper processing unit 2 (step F1), connection information is extracted from the received cell (step F2), and the extracted connection information is output to the memory control unit 3 (step F3). When the connection information is supplied from the UPC / shaper processing unit 2, the memory control unit 3 sends data [(traffic parameter lower b) from the lower management memory 5 based on the connection information.
it) + (address of the upper management memory 4)] (step F4). Further, the memory control unit 3 reads the upper bit data of the traffic parameter from the upper management memory 4 using the address bit of the upper management memory 4 of the extracted data as the address of the upper management memory 4 (step F5).

Next, the memory control unit 3 combines the lower bit of the traffic parameter of the data read from the lower management memory 5 and the upper bit data of the traffic parameter read from the upper management memory 4 (step F).
6) Output the combined data to the UPC / shaper processing unit 2 as traffic parameters required for the UPC / shaper processing unit 2 to perform processing (step F)
7). The UPC / shaper processing unit 2 includes a memory control unit 3
The UPC / shaper process is performed on the received cell based on the traffic parameters supplied from (step F8), and after the process is completed, the cell is output downstream (step F9).

[0029]

As described above, according to the present invention,
By sharing the originally used data area, the data to be held can be reduced, so that the memory scale can be reduced and the hardware scale can be reduced. Further, according to the present invention, by sharing the data area, when the number of connections increases, only the data area that is not shared needs to be increased, so that an increase in the memory capacity due to the increase in the number of connections is suppressed. The advantage is that it can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a UPC / shaper circuit according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram illustrating a memory configuration used in the first embodiment of the present invention.

FIG. 3 is a flowchart illustrating an operation of setting a traffic parameter in the first embodiment.

FIG. 4 is a flowchart for explaining the operation of the first embodiment.

FIG. 5 is a conceptual diagram illustrating a memory configuration used in a second embodiment of the present invention.

FIG. 6 is a flowchart illustrating an operation of setting a traffic parameter according to the second embodiment.

FIG. 7 is a flowchart for explaining the operation of the second embodiment.

FIG. 8 is a conceptual diagram showing a memory configuration used in the third embodiment.

FIG. 9 is a flowchart for explaining an operation of setting a traffic parameter in the third embodiment.

FIG. 10 is a flowchart for explaining the operation of the third embodiment.

FIG. 11 is a conceptual diagram showing a memory configuration of a conventional UPC / shaper circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 UPC / shaper circuit 2 UPC / shaper processing part 3 Memory control part (storage control means, coupling means) 4 Upper management memory (higher storage means) 5 Lower management memory (lower storage means)

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/28 H04L 12/56

Claims (4)

(57) [Claims] 1. A UPC / shaper circuit in an ATM transmission apparatus for adjusting a variation in a cell interval of a connection in an ATM transmission system, wherein a traffic parameter has a similar value for each traffic characteristic.
And upper-level storage means for sharing and storing the upper-order bits of the traffic parameters necessary for performing the UPC / shaper process; and lower-order bits of the traffic parameters excluding the upper-order bits. ; and a lower storage means for holding for each connection, when receiving the cell, the connection information from the received cell
And based on the connection information,
Traffic parameters from each of the storage means and the lower-order storage means.
The meter is pulled out and combined, and the combined traffic
UPC / shape for received cells based on parameters
A UPC / shaper circuit in an ATM transmission device, which performs a par process and outputs the result. 2. The UP in the ATM transmission apparatus according to claim 1, wherein said higher-order storage means classifies and holds S upper-order bits of said traffic parameter.
C / shaper circuit. 3. The low-order storage means stores attribute information indicating which high-order bit corresponding to the low-order bit of the traffic parameter belongs to any of the S high-order bits stored in the high-order storage means. 3. The UPC / shaper circuit according to claim 2, wherein the data is stored for each of said lower bits. 4. A storage control unit for reading traffic parameters from the upper storage unit and the lower storage unit based on connection information obtained from a received cell, and an upper order of the traffic parameters read by the storage control unit. 4. The UPC / shaper circuit according to claim 1, further comprising a coupling means for coupling bits and lower bits.