JP3152860B2 - Transmitter and receiver using orthogonal frequency division multiplex modulation - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to orthogonal frequency division multiplexing (hereinafter referred to as OFDM).
The present invention relates to a transmitting device and a receiving device used in a wireless communication system employing a transmission method (referred to as iplex).

[0002]

2. Description of the Related Art Orthogonal frequency division multiplexing transmission systems are based on ITU.
-R (formerly CCIR) is one of the digital modulation techniques to be adopted for wireless digital audio broadcasting (hereinafter, referred to as DAB) under study, and is generally called OFDM or COFDM (coded OFDM: coding is a transmission path). (Meaning encoding). The details of this technology
U-RS Odd Book (TG11 / 3) or Television Society Research Report Vol. 17, No. 54, pp7-12, B
CS'93-33 (Sep. 1993), etc. Here, only the portions relevant to the present invention will be described below.

In recent years, in the transmission of video signals, audio signals, and the like, digital modulation systems with high quality and high frequency use efficiency have been actively developed. In particular, terrestrial broadcasting and mobile communication are expected to employ an OFDM modulation scheme that is resistant to multipath fading and can increase the frequency use efficiency. The OFDM modulation method is a method of modulating transmission digital data with a large number (several hundreds to thousands) of carrier waves (hereinafter, referred to as carriers) orthogonal to each other.

[0004] A conventional OFDM transmission apparatus is configured as follows. FIG. 10 is a circuit block diagram showing a configuration of the OFDM modulation circuit. That is, data encoded by an image encoding circuit or an audio encoding circuit (not shown) is input to the input terminal 50. This signal is first subjected to error correction encoding processing by an error correction encoding circuit 51.
As the error correction method, for example, a block coding method and a convolutional coding method are used. Since the error-correction-coded signal has coded bits added thereto, the number of bits increases before the signal is coded. The encoded signal contains
The reference symbol insertion circuit 52 inserts null symbols and reference symbols necessary for demodulation in the OFDM receiver. These reference symbols are described in detail in the literature and the like.

FIG. 11 shows the configuration of the reference symbol insertion circuit 52. In the figure, a signal output from the error correction encoding circuit 51 is input to a first-in first-out (hereinafter, FIFO: First-in First-out) circuit 522 via an input terminal 520, where it is time-compressed. The reason for the time compression is that the reference symbol generation circuit 521
This is for inserting the null symbol and the reference symbol generated in the above. The signal output from the FIFO circuit 522, the null symbol and the reference symbol output from the reference symbol generation circuit 521 are multiplexed by the multiplexing circuit 523, and output from the output terminal 524.

The output of the reference symbol insertion circuit 52 is supplied to an inverse fast discrete Fourier transform (hereinafter referred to as IFFT) circuit 53.
, Where the IFFT processing is performed,
A guard period for removing the effect of multipath is added. The signal output from the IFFT circuit 53 is converted into an analog signal by the quadrature modulation circuit 54 and then quadrature-modulated, whereby the signal is output from the output terminal 55 as an OFDM modulation signal. This OFDM modulated signal is frequency-converted by a frequency conversion circuit (not shown), and is thereby wirelessly transmitted as a high-frequency signal corresponding to a carrier frequency.

On the other hand, a conventional OFDM receiver is configured as follows. FIG. 12 is a circuit block diagram showing the configuration of the main part. That is, an OFDM modulated signal selected by a receiver (not shown) is input to the input terminal 60. This OFDM modulated signal is first converted to a digital signal by a quadrature detection circuit 61 and then quadrature detected. Then, the orthogonally detected signal is input to a fast discrete Fourier transform (hereinafter referred to as FFT) circuit 62 and subjected to FFT processing. The signal subjected to the quadrature detection is also input to the timing recovery circuit 66. The timing recovery circuit 66 performs timing recovery and clock recovery required for FFT processing by detecting the transmitted reference symbol, and outputs a clock and a timing signal used in other digital circuits.

The signal after the FFT processing is input to a data demodulation circuit 63, where received data is demodulated. In the demodulated data, the reference symbol, the card period, and the like are removed by the FIFO circuit 64, and only the necessary data is time-expanded.
5 for error correction decoding. The signal after the error correction decoding is output from the output terminal 67.

Incidentally, since the waveform of the OFDM modulated wave is similar to white noise, it is difficult to reproduce the clock using the OFDM modulated wave. Therefore, it is conceivable to perform clock recovery using the reference symbol as described above. However, since the reference symbol is transmitted only every tens of symbol periods, for example, the OFDM receiver may take a long time until clock synchronization. There is. However, each subcarrier of the OFDM modulated wave is
In the case where the modulation is performed, the data can be demodulated if the FFT timing reproduction is completed even when the clock is initially asynchronous. This means that when modulated by differential QPSK, a delay detection method can be used for data demodulation,
This is because data demodulation can be performed when the frequency deviation between the clock and the carrier is small (when the accuracy of each oscillator is high). However, when the clock is asynchronous, the timing of the write control and the read control in the FIFO circuit 64 for time extension gradually shifts. This is because the write control can always be controlled by the timing signal, whereas the read control cannot be controlled. As a result, a collision between the write control and the read control occurs, and a FIFO error occurs in which a normal output signal cannot be obtained.

[0010]

As described above, in the conventional OFDM transmission apparatus, since the FIFO circuit 522 for time compression is arranged at the subsequent stage of the error correction coding circuit 51, the signal corrected by the error correction coding is used. Must be performed, and the memory capacity of the FIFO circuit 522 increases. Also, in the OFDM receiving apparatus, since the FIFO circuit 64 for time expansion is arranged before the error correction decoding circuit 65, the FIFO circuit 64 needs a memory capacity for an error correction coded signal.

Further, when a long time is required for clock recovery of the OFDM receiving apparatus, a FIFO for time expansion is used.
The timing of the write control and the read control is not optimized in the circuit 64, and the read control collides with the write control when the clock is initially asynchronous, and the FIFO control is performed.
There has been a problem that a so-called FIFO error occurs in which a normal read output cannot be obtained from the circuit.

The present invention has been made in view of the above circumstances, and an object of the present invention is to apply an orthogonal frequency division multiplexing modulation method capable of reducing the capacity of a first-in first-out memory for time compression or time expansion. To provide a transmitting device and a receiving device.

Another object of the present invention is to apply an orthogonal frequency division multiplexing modulation method which can optimize the timing of write control and read control of a first-in first-out memory for time expansion, thereby preventing occurrence of a first-in first-out error. The purpose of the present invention is to provide an improved receiving device.

[0014]

In order to achieve the above object, a transmitting apparatus according to the present invention to which an orthogonal frequency division multiplexing modulation method is applied is provided with an error correction coding for error correction coding of transmission digital data for output. Means, reference symbol insertion means for inserting and outputting a reference symbol into the digital data after error correction encoding output from the error correction encoding means, and digital data output from the reference symbol insertion means. A modulation unit for orthogonal frequency division multiplex modulation, wherein a first-in first-out unit is arranged in a preceding stage of the error correction coding unit, and the first-in first-out unit uses the reference for the transmission digital data. A time compression process for inserting a symbol is performed.

Further, the transmitting apparatus according to the present invention, when multiplexing a plurality of digital data sequences and modulating them by an orthogonal frequency division multiplexing modulation method for wireless transmission, performs error correction coding on the plurality of digital data sequences and outputs them. A plurality of error correction coding means, a multiplexing means for multiplexing and outputting each digital data after error correction coding output from these error correction coding means and a reference symbol, and a multiplexing means. And a modulating means for orthogonal frequency division multiplexing of the output multiplexed data, wherein first-in first-out means are respectively arranged in front of the error correction coding means, and these first-in first-out means are provided. , A time compression process for the multiplexing is performed on each of the digital data sequences.

In order to further achieve the above object, a receiving apparatus of the present invention to which an orthogonal frequency division multiplexing modulation method is applied,
Demodulation means for orthogonal frequency division multiplex demodulation of a radio modulation wave signal; timing recovery means for detecting a reference symbol from information obtained in a demodulation process by the demodulation means and generating a predetermined timing signal based on the reference symbol; Separating means for separating necessary information from information demodulated by the demodulating means and outputting the information; and error correction decoding means for performing error correction decoding processing on the information output from the separating means. In the receiving apparatus, a first-in first-out means is arranged at a stage subsequent to the error correction decoding means, and the first-in first-out means converts the information after the error correction decoding processing in synchronization with the timing signal generated by the timing reproduction means. The speed conversion is performed to extend the time.

On the other hand, in order to achieve the other object, the receiving apparatus of the present invention to which the orthogonal frequency division multiplexing modulation method is applied, reads the information after error correction decoding in the first-in first-out means for time expansion in the order of writing the information after error correction decoding. A first-in first-out memory to be output, and control means for designating a write timing and a read timing of the information after the error correction decoding with respect to the first-in first-out memory. In the control means, the read timing is synchronized with a reproduced timing signal. At the time of initialization, the timing is set so that the timing margin between the read timing and the write timing before and after the read timing becomes equal.

According to another aspect of the present invention, there is provided a receiving apparatus comprising: a first-in first-out means for time expansion; a first-in first-out memory for reading information after error correction decoding in the order of writing; Control means for designating the write timing and read timing of the information after the error correction decoding, and monitoring whether or not the correlation between the write timing and the read timing designated by the control means is maintained in a predetermined state A timing monitoring unit that performs the reading timing after the initialization of the reading timing, when the timing monitoring unit determines that the correlation between the writing timing and the reading timing is not maintained in a predetermined state. This is to re-initialize.

[0019]

As a result, according to the present invention, in the transmitting apparatus, time compression processing is performed by first-in first-out means on digital data before the error correction code is added, and in the receiving apparatus, error correction after error correction decoding is performed. Time expansion processing is performed on decoded data that does not include a code by first-in first-out means. For this reason, it is possible to reduce the amount of digital data handled by the first-in first-out means as compared with the conventional case where time compression is performed on data after error correction encoding or time expansion is performed on a signal before error correction decoding. This makes it possible to reduce the memory capacity of the first-in first-out means.

On the other hand, according to the receiving apparatus of the present invention, in the first-in first-out means, the read timing is initialized in synchronization with the timing signal reproduced from the received signal. Since the timing is set so that the timing margin between the timing and the timing becomes equal, a problem in which a collision between the write control and the read control occurs during a period until the clock is pulled in and synchronized is avoided, thereby resulting in a first-in first-out operation error. The possibility of occurrence can be minimized.

According to the receiving apparatus of the present invention, when the time interval between the write timing and the read timing gradually changes in the first-in first-out means and the two timings collide, the occurrence of the collision is detected by the timing monitoring means. The read timing is re-initialized according to the detection result. Therefore, for example, even if it takes time to reproduce the clock and an operation error occurs in the first-in first-out means, the first-in first-out means can be returned to a state in which normal write and read control is performed two frames later.

[0022]

【Example】

(First Embodiment) FIG. 1 is a block diagram showing a configuration of an OFDM modulation circuit which is a main part of an OFDM transmission apparatus according to a first embodiment of the present invention.

The OFDM modulation circuit of the present embodiment includes a FIFO circuit 11, an error correction encoding circuit 12,
A reference symbol insertion circuit 13, an IFFT circuit 14, and a quadrature modulation circuit 15 are sequentially arranged. That is,
In this embodiment, a FIFO circuit 11 for performing time compression is arranged before an error correction coding circuit 12.

That is, when digital data encoded by a video or audio compression encoding circuit (not shown) is input to the input terminal 10, first, a FIFO circuit 11 performs time compression for inserting null symbols and reference symbols described later. Is performed to convert the signal into a burst signal. This burst signal is input to a reference symbol insertion circuit 13 after being subjected to error correction coding processing by an error correction coding circuit 12, where a null symbol and a reference symbol are inserted.

FIG. 2 shows a configuration example of the reference symbol insertion circuit 13.
Shown in That is, the signal output from the error correction encoding circuit 12 is supplied to the multiplexing circuit 13 via the input terminal 131.
3 is input. The multiplexing circuit 133 also receives the null symbol and the reference symbol generated by the reference symbol generation circuit 132. Multiplexing circuit 133
Multiplexes the error-corrected transmission signal with the null symbol and the reference symbol, and outputs the multiplexed signal to the IFFT circuit 14 via the output terminal 134. The reference symbol is a known symbol used for clock recovery and timing recovery in the OFDM receiver.

The IFFT circuit 14 converts the multiplexed signal supplied from the reference symbol insertion circuit 13 into an IFFT
In addition to performing the conversion process, a process of adding a guard period for removing the effect of multipath is performed, and the signal subjected to these processes is supplied to the quadrature modulation circuit 15. The quadrature modulation circuit 15 converts the signal supplied from the IFFT circuit 14 into an analog signal and then quadrature modulates the signal, and outputs the quadrature modulated signal to a transmission circuit (not shown) via an output terminal 16.

With such a configuration, the encoded digital data is first input to the FIFO circuit 11,
Temporal compression is performed by the IFO circuit 11 to form a temporal space for inserting null symbols and reference symbols. That is, time-compression is performed by the FIFO circuit 11 on the encoded digital data before the error correction code is added. Therefore, the amount of data input to the FIFO circuit 11 is reduced as compared with the conventional case where the data after error correction encoding is input to the FIFO circuit and time compression is performed, thereby reducing the memory capacity of the FIFO circuit 11. can do.

FIG. 3 is a block diagram of an O / O switch according to the first embodiment of the present invention.
FIG. 3 is a circuit block diagram illustrating a configuration of an OFDM demodulation circuit that is a main part of the FDM receiving device. The OFDM demodulation circuit of this embodiment includes an analog / digital (A / D) converter 21, a quadrature detection circuit 22, an FFT circuit 24, a data demodulation circuit 25, a demapping circuit 26, and a separation circuit 27 in the flow direction of a received signal. , An error correction decoding circuit 28 and a FIFO circuit 29 are arranged in this order, and an automatic frequency control (AFC) circuit 23 is attached to the quadrature detection circuit 22. That is, a FIFO circuit 29 for time-expanding the received demodulated data is provided at the subsequent stage of the error correction decoding circuit 28.

An OFDM modulated wave signal composed of an intermediate frequency signal output from a receiving circuit (not shown) is input to an A / D converter 21 via an input terminal 20 and is sampled there. Is entered. The quadrature detection circuit 22 performs quadrature detection of the OFDM modulated wave signal, and outputs a quadrature detection signal of an in-phase component and a quadrature component. At this time, the local oscillation frequency of the orthogonal detection circuit 22 is controlled by the AFC circuit 23. That is, the AFC circuit 23 detects an error between the frequency of the quadrature detection signal and the frequency of the local oscillator of the quadrature detection circuit 503, smoothes this error signal, and feeds it back to the local oscillator of the quadrature detection circuit 22, thereby The local oscillation frequency is made to follow the reception modulation wave frequency.

The FFT circuit 24 is composed of the above quadrature detection circuit 22
Performs an FFT process on the quadrature detection signal output from. This F
Data demodulation circuit 2 to which a detection signal subjected to FT processing is input
Reference numeral 5 demodulates and outputs the detected signal. At this time, the demodulation method of the data demodulation circuit 25 varies depending on the modulation method of each carrier of the OFDM modulated wave. For example, when each subcarrier is modulated by the differential QPSK method, delay detection is performed. Used.

The demodulated signal output from the data demodulation circuit 25 is demapped by a demapping circuit 26 and then input to a separation circuit 27. This separation circuit 2
Numeral 7 separates only necessary signals from the multiplexed demodulated signals, and supplies the separated and extracted signals to an error correction decoding circuit 28. At this time, the output signal of the separation circuit 27 has a burst shape, but the error correction decoding circuit 28 performs error correction decoding processing in the burst shape. The demodulated signal subjected to the error correction decoding is finally sent to the FIFO.
Input to the circuit 29. The FIFO circuit 29 time-expands the demodulated signal and converts it from a burst signal to a continuous signal. Then, the continuous signal is output from the output terminal 30 as a demodulated signal.

The timing recovery circuit 31 performs frame synchronization detection and clock recovery by detecting a reference symbol sent from the transmission side, and receives the frame synchronization signal, frame pulse, and recovered clock obtained thereby. Supply to each circuit of the device.

With such a configuration, the demodulated signal is
After being subjected to error correction decoding processing by the error correction decoding circuit 28, it is input to the FIFO circuit 29 and time-expanded. For this reason, the FIFO circuit 29 only needs to perform time expansion processing on a signal of a small number of bits that does not include the coded bits for error correction, thereby reducing the memory capacity of the FIFO circuit 29.

By the way, the FIF of the OFDM demodulation circuit
The O circuit 29 is configured as follows, for example. FIG. 4 is a circuit block diagram showing the configuration, and FIG. 5 is a timing chart showing the operation of the circuit shown in FIG.

The FIFO circuit 29 performs time expansion by using two FIFO memories that cannot simultaneously read and write data. That is, the demodulated data after the error correction decoding output from the error correction decoding circuit 28 is
The data is input to the first and second FIFO memories 293 and 294 via the input terminal 290. This input data is shown in FIG.
(B). The FIFO memories 293 and 294 receive a write control signal W from a write control circuit 295 described later.
E is applied, and when the write control signal WE is "H", the input data is written into the FIFO memories 293 and 294, respectively. FIGS. 5C and 5E show the write control signal WE applied to the FIFO memories 293 and 294.
The input data is alternately written to the FIFO memories 293 and 294 for each frame.

On the other hand, the FIFO memories 293 and 29
4 are read out in the order in which they were written by the read control signal RE generated from the read control circuit 296. FIGS. 5D and 5F show the generation timing of the read control signal RE. These read control signals RE are logically inverted by an inverting circuit 297, whereby the FIFO memories 293 and 294 are output.
Are alternately read. These F
Demodulated data read from the IFO memories 293 and 294 are time-expanded as shown in FIGS. 5 (g) and 5 (h).

The demodulated data read from the FIFO memories 293 and 294 is input to the selector 298. The switching control terminal of the selector 298 receives the read control signal RE as a switching signal, whereby the output data of the FIFO memory 293 and the output data of the FIFO memory 294 are alternately output from the selector 298. FIG. 5 (i) shows the output timing of these output data.
The signal is output as demodulated data via the line 99.

The write control circuit 295 and the read control circuit 296 generate the write control signal WE and the read control signal RE in synchronization with the frame pulse and the frame synchronization signal, respectively, as follows. That is, a frame pulse and a frame synchronization signal are input to the write control circuit 295 and the read control circuit 296 via the input terminals 291 and 292, respectively. As shown in FIG. 5A, the frame pulse is a pulse that goes low once per frame in synchronization with the input data, and the frame synchronization signal is a signal indicating whether the frame is in a frame synchronous state or an asynchronous state. . The frame pulse and the frame synchronization signal are generated by detecting the reference symbol sent from the transmitting side in the timing recovery circuit 31 described above.

The write control circuit 295 outputs a write control signal WE whose timing is constantly controlled by a frame pulse in the frame synchronization state. After the frame synchronization is established, that is, after the frame synchronization signal changes from the asynchronous state to the synchronous state, the read control circuit 296 controls the timing with the frame pulse only once to initialize the read timing, and thereafter holds the timing. The read control signal RE is output as it is.

Therefore, when the clock is initially asynchronous,
The timing of the write control signal WE, which is always timing-controlled by a frame pulse, and the timing of the read control signal RE, which are not timing-controlled, are shifted from each other. That is, this is the timing margin T1 between the write control signal WE and the read control signal RE in FIG.
And T2 change. If the output timings of the write control signal WE and the read control signal RE overlap with each other, the next data is written before the previous data is read from the FIFO memory, and the data cannot be output correctly, and a FIFO error occurs. Would.

In order to avoid this FIFO error, the read control circuit 295 of this embodiment uses the read control signal R
When the timing of E is initialized, the write control signal W
The timing margins T1 and T2 between E and the read control signal RE are set so that T1 = T2.
By setting in this way, the possibility that a FIFO error will occur during the time until the clock is pulled in and synchronized is minimized.

As described above, in the first embodiment, the OFDM
In the transmitting device, a FIFO circuit 11 for performing a time compression process for inserting a null symbol and a reference symbol
Is arranged before the error correction coding circuit 12, while the OFD
In the M receiving apparatus, a FIFO circuit 29 for reproducing the original data by time-expanding the received demodulated data is arranged at the subsequent stage of the error correction decoding circuit 28. Also, in the FIFO circuit 29 of the OFDM receiver, the read control signal R
When the timing of E is initialized, the write control signal W
The timing margins T1 and T2 between E and the read control signal RE are set so that T1 = T2.

Therefore, according to the present embodiment, in the OFDM transmission apparatus, time-compression processing is performed by the FIFO circuit 11 on the encoded digital data before the error correction code is added, and in the OFDM reception apparatus, error correction is performed. Since the decoded data that does not include the error-correction code bits after decoding is subjected to time expansion processing by the FIFO circuit 29, the data after error-correction coding is time-compressed, or the signal before error-correction decoding is subjected to time-expansion. The amount of data handled by the FIFO circuits 11 and 29 is reduced as compared with the conventional case in which decompression is performed.
Memory capacity can be reduced.

In this embodiment, when the timing of the read control signal RE is initialized, the timing margins T1 and T2 between the write control signal WE and the read control signal RE are set so that T1 = T2. Since the setting is set, a problem in which a collision between the write control and the read control occurs during a period from when the clock is pulled in and synchronized is prevented, thereby minimizing a possibility that a FIFO error occurs.

(Second Embodiment) In this embodiment, an error detection circuit is provided in a FIFO circuit of an OFDM receiver, and it is monitored whether or not a write control signal and a read control signal are simultaneously generated. When it is detected that they are simultaneously generated, the read control circuit initializes the output timing of the read control signal using the next input frame pulse.

FIG. 6 is a block diagram of an F-mode according to a second embodiment of the present invention.
FIG. 3 is a circuit block diagram illustrating a configuration of an IFO circuit. In addition,
In this figure, the same parts as those in FIG. 4 are denoted by the same reference numerals, and detailed description is omitted.

An error detection circuit 300 is newly provided in the FIFO circuit of this embodiment. The error detection circuit 300 monitors whether the write control signal WE from the write control circuit 295 and the read control signal RE from the read control circuit 301 are simultaneously generated. Then, when it is detected that these control signals WE and RE are simultaneously generated, an error detection signal is generated and this signal is supplied to the read control circuit 301. Once the read control circuit 301 initializes the output timing of the read control signal RE in synchronization with the frame pulse after the frame synchronization is established, the read control circuit 301 thereafter holds the timing. However, when an error detection signal is generated from the error detection circuit 300 during this holding period, the output timing of the read control signal RE is initialized using the next input frame pulse.

With this configuration, when frame synchronization is established, the write control circuit 295 outputs a write control signal WE synchronized with the frame pulse thereafter. On the other hand, in the read control circuit 301, the output timing of the read control signal RE is initialized by the first input frame pulse after the frame synchronization is established, and thereafter, the read control signal RE is generated in a frame cycle based on the initialization timing. Is done.

Now, suppose that in this state, the time interval between the write control signal WE and the read control signal RE changes and a part thereof overlaps. Then, the collision of the control signals is detected by the error detection circuit 300,
The error detection circuit 300 outputs an error detection signal. When an error detection signal is generated, the read control circuit 3
In 01, the output timing of the read control signal RE is initialized using the next input frame pulse.

Therefore, for example, even if it takes time to recover the clock and this causes a FIFO error,
After two frames, the FIFO circuit can be returned to a state where normal write and read control is performed.

(Third Embodiment) In this embodiment, a FIFO circuit of an OFDM receiving apparatus is capable of executing one write control and one read control at the same time.
When a memory is used, a match between the write control timing and the read address reset timing for the FIFO memory is monitored by an error detection circuit, and when a match is detected, the read address reset timing is initialized. , FIFO errors do not continue for a long time.

FIG. 7 is a circuit block diagram showing a configuration of a FIFO circuit according to a third embodiment of the present invention. 6, the same parts as those in FIG. 6 are denoted by the same reference numerals, and detailed description is omitted.

In FIG. 7, reference numeral 310 denotes a FIFO memory which can be read and written at the same time. In the FIFO memory, in addition to the input terminals of the write control signal WE and the read control signal RE, the write address reset signal WRST and the read address reset signal RRST are input. An input terminal is provided.

The FIFO circuit of this embodiment also has an error detection circuit 311 as in the second embodiment. The error detection circuit 311 obtains a logical product of an inverted signal of a write control signal WE output from a write control circuit 312 described later and a read address reset signal RRST output from the read control circuit 313, and uses the output as a basis. , The occurrence of a FIFO error is detected.

After the frame synchronization is established, the write control circuit 312 outputs a write control signal W synchronized with the frame pulse.
E and the write address reset signal WRST are generated at the timings shown in FIGS. On the other hand, the read control circuit 313 initializes the output timing of the read address reset signal RRST once in synchronization with the frame pulse after the frame synchronization is established, and thereafter, as shown in FIG. A read address reset signal RRST is generated in a frame cycle. However, when an error detection signal is generated from the error detection circuit 311 during this holding period, the output timing of the read address reset signal RRST is initialized using the next input frame pulse.

With such a configuration, the read control circuit 313 initializes the generation timing of the read address reset signal RRST only once after the frame synchronization is established, that is, after the frame synchronization signal is switched asynchronously. A read address reset signal RRST is generated at a frame period based on the initialization timing. That is, at the time of the initial clock asynchronous,
Although the generation timing of the write control signal WE and the write address reset signal WRST is always controlled by the frame pulse, the read address reset signal RR
The generation timing of the ST is not controlled in synchronization with the frame pulse, and enters a free-running oscillation state. Therefore, the relative time difference between the write control signal WE and the read address reset signal RRST, that is, T3 and T4 in FIG. 8 gradually changes. When the generation timing of the write control signal WE and the generation timing of the read address reset signal RRST overlap due to this change, FI
The next data is written before the previous data is read from the FO memory 310, and the data cannot be output correctly. That is, a FIFO error occurs.

Therefore, in this embodiment, in order to avoid the FIFO error, the read control circuit 313 initializes the timing of the read address reset signal RRST when initializing the timing of the read address reset signal RRST. T3 and T4 are set so that T3 = T4. By setting in this way, the possibility that a FIFO error will occur during the time until the clock is pulled in and synchronized can be minimized.

Further, while taking such measures, the time interval between the write control signal WE and the read address reset signal RRST changes during the operation after the initial reset due to, for example, a temperature change or an aging change of the element characteristics. It is assumed that the timings overlap. However, in this case, the error detection circuit 311 outputs an error detection signal. Then, in response to the error detection signal, the read control circuit 313 initializes the output timing of the read address reset signal RRST using the next input frame pulse.

Therefore, even if a FIFO error occurs, the FIFO circuit can be returned to a state where normal writing and reading control is performed after two frames.

(Fourth Embodiment) This embodiment is necessary for multiplexing each of the above-mentioned coded digital data in an OFDM transmitting apparatus for multiplexing and transmitting a plurality of video or audio coded digital data sequences. A FIFO circuit for performing a time compression process is disposed at a stage preceding the error correction coding circuit, so that the time compression process is performed on the coded digital data before the error correction code is added.

FIG. 9 is a block diagram showing a fourth embodiment according to the present invention.
FIG. 3 is a circuit block diagram illustrating a configuration of an OFDM modulation circuit that is a main part of the FDM transmission device. This OFDM modulation circuit
FIFO circuits 411 to 411 corresponding to the number of input data series
41n and error correction coding circuits 421 to 42n, and further includes a multiplexing circuit 430 and an IFFT circuit 450.
And a quadrature modulation circuit 451.

Video or audio coded digital data is input to each of the FIFO circuits 411 to 41n via input terminals 401 to 40n. Each of the FIFO circuits 411 to 41n includes a multiplexing circuit 4 to be described later.
At 30, a time compression process is performed to prevent the data of each series from colliding. The time-compressed encoded digital data is input to error correction encoding circuits 421 to 42n. The error correction coding circuits 421 to 42n perform an error correction coding process on the coded digital data that has been made into a burst by the above-described time compression, and the error correction coded digital data is sent to the multiplexing circuit 430, respectively. Is entered.

The multiplexing circuit 430 multiplexes the error-correction-coded digital data supplied from the error-correction coding circuits 421 to 42n with the null symbol and the reference symbol generated from the reference symbol generation circuit 440. Is done. The multiplexed data output from the multiplexing circuit 430 is input to the IFFT circuit 450. The IFFT circuit 450 performs an IFFT conversion process on the multiplexed data, and adds a guard period for removing the influence of multipath. Quadrature modulation circuit 451
Then, the multiplexed data output from the IFFT circuit 450 is orthogonally modulated, and the output signal is output as an OFDM modulated wave from an output terminal 452 to a transmission circuit (not shown).

With such a configuration, each of the encoded digital data is firstly transmitted to the FIFO circuits 411-41.
n, and these FIFO circuits 411 perform time compression processing for multiplexing and inserting null symbols and reference symbols, respectively. That is, for any of the input data sequences, the FIFO circuit 41 applies the coded digital data before the error correction code is added.
Time compression is performed at 1 to 41n. Therefore, compared with the conventional case where the data after error correction coding is input to the FIFO circuit and time compression is performed,
The amount of data input to 41n decreases, thereby reducing the memory capacity of FIFO circuits 411-41n.

It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made to the installation position and circuit configuration of the FIFO circuit without departing from the gist of the present invention.

[0066]

As described in detail above, in the orthogonal frequency division multiplexing transmission apparatus of the present invention, first-in first-out means is arranged at the front stage of the error correction coding means, and the first-in first-out means means for transmitting the transmission digital data. A time compression process for inserting the reference symbol is performed. On the other hand, in the orthogonal frequency division multiplex receiving apparatus of the present invention, first-in first-out means is arranged at a stage subsequent to the error correction decoding means, and the first-in first-out means includes the timing recovery means. In order to time-expand the information after the error correction decoding processing in synchronization with the timing signal generated by the above, the speed conversion is performed.

Therefore, according to the present invention, it is possible to provide a transmitting apparatus and a receiving apparatus to which an orthogonal frequency division multiplexing modulation method capable of reducing the capacity of a first-in first-out memory for time compression or time expansion is applied.

In the orthogonal frequency division multiplex receiving apparatus of the present invention, when the read-out timing is initialized by the first-in first-out means for time expansion in synchronization with the reproduced timing signal, the read-out timing and the write before and after the read-out timing are initialized. The timing is set so that the timing margin between the timing and the timing becomes equal.

In still another receiver, the first-in first-out means for time extension includes timing monitoring means for monitoring whether or not the correlation between the write timing and the read timing is maintained in a predetermined state. After the timing is initialized, when the timing monitoring means determines that the correlation between the write timing and the read timing is not maintained in a predetermined state, the read timing is reinitialized.

Therefore, according to these inventions, the orthogonal frequency division multiplexing modulation system which can optimize the timing of the write control and the read control of the first-in first-out memory for time expansion and thereby prevent the occurrence of the first-in first-out error is applied. A receiving device can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a configuration of an OFDM modulation circuit that is a main part of an OFDM transmission device according to a first embodiment of the present invention.

FIG. 2 is a circuit block diagram showing a configuration of a reference symbol insertion circuit in the OFDM modulation circuit shown in FIG.

FIG. 3 is a circuit block diagram illustrating a configuration of an OFDM demodulation circuit that is a main part of the OFDM receiver according to the first embodiment of the present invention.

FIG. 4 is a circuit block diagram showing a configuration of a FIFO circuit in the OFDM demodulation circuit shown in FIG. 3;

FIG. 5 is a timing chart used to explain the operation of the FIFO circuit shown in FIG. 4;

FIG. 6 is a circuit block diagram showing a configuration of a FIFO circuit according to a second embodiment of the present invention.

FIG. 7 is a circuit block diagram showing a configuration of a FIFO circuit according to a third embodiment of the present invention.

FIG. 8 is a timing chart used to describe the operation of the FIFO circuit shown in FIG. 7;

FIG. 9 is a circuit block diagram illustrating a configuration of an OFDM modulation circuit that is a main part of an OFDM transmission device according to a fourth embodiment of the present invention.

FIG. 10 is a circuit block diagram showing a configuration of an OFDM modulation circuit in a conventional OFDM transmission device.

11 is a circuit block diagram showing a configuration of a reference symbol insertion circuit in the OFDM modulation circuit shown in FIG.

FIG. 12 is a circuit block diagram showing a configuration of an OFDM demodulation circuit in a conventional OFDM receiver.

[Description of Codes] 10, 401 to 40n: Input terminals for encoded digital data 11, 411 to 41n: FIFO circuits for time compression 12, 421 to 42n: Error correction encoding circuits 13, 440: Reference symbol insertion circuits 14 , 450 ... inverse fast discrete Fourier transform (IFFT) circuit 15, 451 ... orthogonal modulation circuit 16, 452 ... OFDM modulated signal output terminal 20 ... OFDM modulated wave input terminal 21 ... analog / digital (A / D) circuit 22 ... Quadrature detection circuit 23 ... Automatic frequency control (AFC) circuit 24 ... Fast discrete Fourier transform (FFT) circuit 25 ... Data demodulation circuit 26 ... Demapping circuit 27 ... Separation circuit 28 ... Error correction decoding circuit 29 ... Time expansion FIFO circuit 30 demodulation data output circuit 31 timing recovery circuit 132 reference symbol generation circuit 33,430 multiplexing circuit 293 ... first FIFO memory 294 ... second FIFO memory 295,312 ... write control circuit 296,301,313 ... read control circuit 297 ... inverting circuit 298 ... selector 300,310 ... error detection Circuit 310: FIFO capable of simultaneous reading and writing
circuit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigeru Okita 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside Toshiba Multimedia Engineering Laboratory Co., Ltd. (72) Inventor Makoto Sato 3-3-9 Shimbashi, Minato-ku, Tokyo No. TOSHIBA ABU Corporation (56) References JP-A-5-219021 (JP, A) JP-A-5-308641 (JP, A) JP-A-6-350649 (JP, A) Kaihei 6-83790 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04J 11/00

Claims (3)

(57) [Claims] 1. A receiving apparatus for receiving and demodulating a radio modulation signal modulated by an orthogonal frequency division multiplexing modulation method, comprising: demodulation means for orthogonal frequency division multiplex demodulation of the radio modulation signal; A timing reproducing means for detecting a reference symbol from the information data sequence obtained in the demodulation process by the reference symbol and generating a predetermined timing signal based on the reference symbol; Separating means for separating and outputting a proper information data string; error correcting decoding means for performing error correction decoding processing on the information data string output from the separating means; The information data sequence after the error correction decoding processing is arranged in synchronization with the timing signal generated by the timing reproduction means. A first-in first-out means for speed-converting and outputting the data, wherein the first-in first-out means reads out the information data sequence after error correction decoding in the order in which the information data was written, and performs error correction on the first-in first-out memory. Control means for designating the write timing and read timing of the decoded information data sequence, and monitoring whether or not the correlation between the write timing and read timing designated by the control means is maintained in a predetermined state And a timing monitoring means for: the control means, after initializing the read timing,
When it is determined by the timing monitoring means that the correlation between the write timing and the read timing is not maintained in a predetermined state, re-initialization of the read timing is performed. A receiving apparatus to which an orthogonal frequency division multiplexing modulation system is applied, wherein a burst-like information data string output from the error correction decoding means is converted into a continuous information data string. 2. When a plurality of digital data sequences are multiplexed and then a radio modulation wave signal modulated by an orthogonal frequency division multiplexing modulation method is received and demodulated, the demultiplexing means demodulates the signal. 2. The receiver according to claim 1, wherein an information data sequence corresponding to a desired digital data sequence is separated and output from the information data sequence. 3. The control unit of the first-in first-out unit, when initializing the read timing in synchronization with a timing signal generated by the timing reproduction unit,
3. The receiving apparatus to which the orthogonal frequency division multiplex modulation system according to claim 1 or 2, wherein the timing is set so that a timing margin between the read timing and the write timing before and after the read timing becomes equal.