JP3147546B2 - Audio data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio data transfer system in an audio storage / reproducing apparatus for storing and reproducing audio data.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing an example of a conventional audio storage / reproducing apparatus, and FIG. 5 is a diagram showing an example of an audio data reproducing process in FIG.

[0003] In FIG. 4, an exchange (1) is provided with an audio storage / reproduction device (3) for storing and reproducing audio transmitted from an accommodation subscriber (2). The audio storage / playback device (3) has two buffer memories (RAM) (3
1) [Individual buffer memories (RAM) are referred to as (31 ₀ ) and (31 ₁ ), and both are collectively referred to as (31)]
, A disk device (DK) (32), a disk controller (DKC) (33), and a processor (CPU) (3).
4) and a direct memory access control device (DMC)
(35) and a serial-parallel interconversion device (PSR) (36), and are connected to the exchange (1) by an upstream highway ( _4U ) and a downstream highway ( _4D ).

The processor (CPU) (34) includes counting units (341) and (342), a synchronization monitoring unit (343), and a transfer stopping unit (344). When the voice storage / reproduction device (3) stores voice transmitted from the subscriber (2) connected via the exchange (1), the serial-parallel mutual conversion device (PSR) (36) From (2) to exchange (1) and downstream highway (4
_The digitally encoded audio data (d) transferred via _D ) is converted from a serial code to a parallel code.

A direct memory access control device (DM)
C) (35) extracts parallel-encoded audio data (d) from the serial-parallel mutual conversion device (PSR) (36) under the control of the processor (CPU) (34), and The data is alternately stored in a memory (RAM) (31).

Each buffer memory (RAM) (31)
Has a storage capacity capable of storing one second of audio data (d) arriving from the downstream highway (4 _D ).

The direct memory access control device (DMC) (35) is a serial-parallel mutual conversion device (PSR).
In parallel with the transfer of the audio data (d) from (36) to the buffer memory (RAM) (31), the audio data (d) for one second stored in the two buffer memories (RAM) (31) Disk controller (DKC)
The data is stored in the disk device (DK) (32) via (33).

[0008] Further, the audio storage / reproduction device (3) transfers the audio data (d) stored in the disk device (DK) (32) to the subscriber (2) connected via the exchange (1). When reproducing, the direct memory access control device (DMC) (35)
Disk device (DK) (32) under the control of (34)
The audio data (d) stored in the buffer memory (d) is extracted for one second at one-second intervals, and is alternately stored in two buffer memories (RAM) (31).

The direct memory access control device (DMC) (35) includes a disk device (DK) (32)
In parallel with the transfer of the audio data (d) from the buffer memory (RAM) (31) to the two buffer memories (RA)
M) Voice data (d) for one second stored in (31)
Are alternately extracted, and the serial-parallel mutual conversion device (PSR) (3
Transfer to 6).

Serial-parallel mutual conversion device (PSR) (36)
Converts the transmitted voice data (d) from a parallel code to a serial code, and transmits it to the subscriber (2) via the upstream highway ( _4U ) and the exchange (1).

The processor (CPU) (34) performs the process of storing and reproducing the audio data (d) as described above.
Downhill highway ( _4D ) and buffer memory (RAM)
(31) and the buffer memory (RA
M) The state of synchronization with the data transfer between (31) and the disk device (DK) (32) is monitored using the counting unit (341), the counting unit (342), and the synchronization monitoring unit (343), Synchronization between data transfer between the disk device (DK) (32) and the buffer memory (RAM) (31) and data transfer between the buffer memory (RAM) (31) and the upstream highway ( _4U ). The status is also monitored in the same manner as described above.

Next, the process of monitoring the synchronization state of the processor (CPU) (34) will be described with respect to the audio data reproduction process shown in FIG. 4 and 5,
The processor (CPU) (34) includes a disk device (D
K) (32), one second of audio data (d) is extracted, and the order in which the data is alternately stored in the two buffer memories (RAM) (31) is counted by the counting unit (341).

For example, from time (t ₁ ) to (t ₁ ′), the first one second of audio data (d) [hereinafter, the i-th one second of audio data is referred to as (d _i ), and so on] From the disk device (DK) (32) to the buffer memory (RA).
M) (31 ₀ ), the counting unit (341) sets the count value (n ₁ ) to (1) _D [where (n) _D indicates a decimal digit].

The elapsed time from the time point (t ₁ ) to the time point (t ₁ ') is determined by the direct memory access control device (DMC) from the disk device (DK) (32) to the buffer memory (RAM) (31 ₀ ). This corresponds to the transfer time of the audio data (d ₁ ) according to (35), but usually ends in a time sufficiently shorter than one second.

Similarly, at the time point (t₁) More than one second intervals
Time (t_Two) Through (t)_Two'), (T _Three) Through
(T_Three'), (T_Four) Through (t)_Four′)
Data (d_Two), (D_Three), (D_Four) To the disk drive (D
K) (32) to the buffer memory (RAM) (31)₁)
Is transferred to the counting unit (341).₁)
Next (2) _D, (3)_D, (4)_DAnd update.

[0016] Further time one second after _{(t 4) (t 5)} , but starts to transfer the fifth audio data (d _5), transfer any way of the fifth audio data (d ₅₎ For this reason, if the transfer is greatly delayed, for example, when the transfer is completed at a time (t ₅ ′) after 2 seconds or more and less than 3 seconds, the counting unit (34)
1) gradually increases the count value (n ₁ ) at time (t ₅ ′) to (5) _D
Update to

On the other hand, the processor (CPU) (34) updates the count value (n ₂ ) of the counting section (342) at one-second intervals,
For example, when the count value (n ₂ ) is updated to (1) _D at the time (t ₂ ), the synchronization monitoring unit (343) in the processor (CPU) (34) makes the count value (n ₁ ) of the count unit (341). Is compared with the count value (n ₂ ) of the counting unit (342), and the count value (n
In ₂₎ is (1) the time it is set to _D (t _2), when confirming that count value (n ₁₎ is also already (1) already set to _D, audio data at time (t ₂₎ ( d ₁ ) has already been stored in the buffer memory (RAM) (31), it is determined that the reproduction of the audio data (d ₁ ) is in a synchronized state, and the audio data (d ₁ ) is stored in the buffer memory (RAM) (31).
To the highway (4 _U ) from the direct memory access control device (DMC) (35).

Processor (CPU) permitted to transfer
(34) extracts audio data (d ₁ ) sequentially from the buffer memory (RAM) (31 ₀ ) during one second from the time point (t ₂ ) and sends it to the serial-parallel mutual conversion device (PSR) (36). The data is transferred, converted from a parallel code to a serial code, and sent out to the upstream highway ( _4U ).

Similarly, the synchronization monitoring unit (343) performs (t ₃ ), (t ₄ ), and (t ₃ ) at one-second intervals from the time (t ₂ ).
At (t ₅ ), the count value (n ₂ ) is (2) _D , (3) _D ,
(4) By comparing _D with the count value (n ₁ ) at each update, it is determined that the reproduction of the audio data (d ₂ ), (d ₃ ), and (d ₄ ) is in a synchronized state, and direct memory access is performed. The voice data (d ₂ ), (d
₃ ), playback of (d ₄ ) is allowed, and audio data (d ₂ )
(D ₃ ) and (d ₄ ) are stored in a buffer memory (RAM) (3
Serial-to-parallel mutual conversion device (PSR) extracted sequentially from 1)
(36), convert the parallel code into a serial code, and send it to the upstream highway ( _4U ).

[0020] Further, the processor (CPU) (34) is the time (t ₅₎ the time after one second from the (t _51), but updates the count value of the (n ₂₎ (5) to the _D, point (t ₅₁ ), The audio data (d ₅ ) has not yet been stored in the buffer memory (RAM) (31 ₀ ) as described above.
The count value (n ₁ ) of the counting section (341) is held in (4) _D.

At the time (t ₅₁ ), the synchronization monitor (343) determines that the count value (n ₂ ) of the counter (342) is (5) _D
On the other hand, when it is recognized that the count value (n ₁ ) of the counting unit (341) is (4) _D , the voice data (d ₅ )
Is determined to be in an asynchronous state, and the transfer stop unit (34)
4) Start.

The activated transfer stop unit (344) stops the reproduction of the audio data (d ₅ ) in the asynchronous state.

[0023]

As is clear from the above description, the conventional audio storage / reproducing apparatus has a synchronization monitoring unit (3).
43) Transfer of audio data (d) from the disk device (DK) (32) to the buffer memory (RAM) (31) and audio data from the buffer memory (RAM) (31) to the upstream highway ( _4U ) The state of synchronization with the transfer of (d) is monitored by the count values (n ₁ ) and (n ₂ ), and if it is determined that the state is asynchronous, the transfer stop unit (344) is activated to output the audio data (d). Since the reproduction was stopped, there was a problem that the subsequent processing was interrupted.

[0024] It is an object of the present invention to minimize interruption of audio data transfer processing.

[0025]

FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, 101 is an audio data transfer path, 102 is audio data storage means, and 103 is temporary storage means.

Reference numeral 111 denotes a transfer continuation unit provided in the audio storage / reproduction device (100) according to the present invention.

[0027]

The transfer continuation means (111) is provided by the provisional storage means (1).
03) and the transfer of the audio data between the audio data storage means (102) and the transfer of the audio data between the temporary storage means (103) and the audio data transfer path (101) are monitored and compared; Even when both transfers are determined to be in an asynchronous state, both transfers are continued without interruption.

The transfer continuation means (111) is provided from the voice data storage means (102) to the voice data transfer path (101).
When the audio data is transferred to the
02) to the temporary storage means (103) when the transfer of the audio data is delayed, until the normal audio data is transferred from the audio data storage means (102) to the temporary storage means (103). It is considered that the voice data stored in (103) is transferred to the voice data transfer path (101).

The transfer continuation means (111) is connected to the sound data transfer means (101) through the sound data storage means (102).
Temporary storage means (103) when transferring voice data to
If the transfer of the audio data from the audio data to the audio data storage means (102) is delayed, the audio data can be discarded until normal audio data can be transferred to the audio data storage means (102). It is considered that the transfer of the audio data from the data transfer path (101) to the temporary storage means (103) is continued.

Therefore, even if the transfer of the audio data in the audio storage / reproducing apparatus becomes asynchronous, the transfer of the audio data can be continued, and the interruption of the transfer processing of the audio data can be prevented. The reliability of the audio storage / playback device is improved.

[0031]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing an audio storage / playback apparatus according to an embodiment of the present invention, and FIG. 3 is a view showing an example of the audio data playback process in FIG. The same reference numerals indicate the same objects throughout the drawings.

In FIG. 2, an upstream highway (4 _U ) and a downstream highway (4 _D ) are provided between the exchange (1) as an audio data transfer path (101) in FIG. A disk unit (DK) (32) and a disk control unit (DKC) (33) are provided as storage means (102), and the exchange (1)
In this example, two buffer memories (RAM) (31) capable of storing one second of audio data (d) are provided as temporary storage means (103), and counting is performed as transfer continuation means (111) in FIG. A unit (341), a counting unit (342), a synchronization monitoring unit (343), and a synchronization adjustment unit (345) are provided.

Hereinafter, as described above, the processor (CP
The process of monitoring the synchronization state of U) and (34) will be described with respect to the audio data reproduction process shown in FIG. 2 and 3, the direct memory access control device (DMC) (35) includes a processor (CP) as described above.
U) Under the control of (34), at one-second intervals (t ₁ ),
At (t ₂ ), (t ₃ ), (t ₄ ), and (t ₅ ), audio data (d ₁ ),
(D ₂ ), (d ₃ ), (d ₄ ), and (d ₅ ) are extracted, and the time points (t ₁ ′), (t ₂ ′), (t ₃ ′), (t ′ ₄ ),
At the time (t ₅ ′), when the data is alternately stored in the buffer memories (RAM) (31 ₀ ) and (31 ₁ ), the counting section (34)
The count value (n ₁ ) of (1) is expressed as (1) _D , (2) _D ,
(3) _D , (4) _D , and (5) _D are updated.

Here, audio data (d ₁ ), (d ₂ ),
The transfer of (d ₃ ) and (d ₄ ) was performed normally and completed in a sufficiently short time than one second.
₂ ), (t ₃ ), (t ₄ ), (t ₅ ), and the next one second of audio data (d ₂ ), (d ₃ ), (d ₄ ), (d ₅ )
Of the disk device (DK) (32) to the buffer memory (RAM) (31) is started.

However, if the transfer of the audio data (d ₅ ) is greatly delayed as described above, and the transfer ends at the time (t ₅ ′), for example, two seconds or more and less than three seconds, the time (t ₅ )
One second later (t ₅₁ ) and two seconds later (t ₅₂ )
, The transfer of the audio data (d ₆ ) cannot be started, and the fourth audio data (d ₆ ) is stored in the buffer memory (RAM) (31 ₁ ).
₄ ) remains accumulated, and the counting unit (341) also
From the time point (t ₄ ′) to the time point (t ₅ ′), the count value (n
₁ ) is retained in (4) _D.

It should be noted that between the time points (t ₅ ) and (t ₅ ′),
From the disk device (DK) (32) to the buffer memory (R)
Although the transfer of voice data (d ₅₎ of the AM) (31) is delayed, the buffer memory (RAM) (audio data accumulated in 31) (d ₄₎ upward highway, etc. (4 _U) Can be transferred without any problem.

On the other hand, as described above, the processor (CPU) (34) counts the value (n) of the counting unit (342) at one-second intervals.
₂ ), the synchronization monitoring unit (343) updates the counting unit (3).
By comparing the count value (n ₁ ) of (41) with the count value (n ₂ ) of the counting section (342), it is determined whether or not the audio data (d) is in the synchronized state, and the state is changed to the synchronized state. If it is determined that there is to be transferred to the buffer memory (RAM) upward highway from (31) (4 _U), allowing the direct memory access controller (DMC) (35), as a result, direct memory access Control device (D
MC) (35) are the time points (t ₁ ), (t ₂ ), (t ₃ ),
A (t ₄₎ for one second from the speech data (d _1),
(D ₂ ), (d ₃ ) and (d ₄ ) are stored in a buffer memory (RA
M) (31) and sequentially extracted from the serial-parallel mutual conversion device (P
SR) (36), converts the parallel code to a serial code, and transmits the converted code to the upstream highway ( _4U ).

[0038] Further, the processor (CPU) (34) is the time (t ₅₎ the time after one second from the (t _51), but updates the count value of the (n ₂₎ (5) to the _D, point (t ₅₁ ), The audio data (d ₅ ) has not yet been stored in the buffer memory (RAM) (31 ₀ ) as described above.
The count value (n ₁ ) of the counting section (341) is held in (4) _D.

At the time point (t ₅₁ ), the synchronization monitoring unit (343) determines that the count value (n ₂ ) of the counting unit (342) is (5) _D
On the other hand, when it is recognized that the count value (n ₁ ) of the counting unit (341) is (4) _D , the voice data (d ₅ )
Is determined to be in an asynchronous state, and the synchronization adjustment unit (34)
5) Start.

The activated synchronization adjustment unit (345) performs synchronization.
Based on the determination result of the monitoring unit (343), the audio data (d
_Five) Is the time (t₅₁) In the buffer memory (RA
M) (31₀)), The storage is not completed,
The count value (n) of several parts (342) _Two) Of (5)_DUpdate to
Invalid, count value (n_Two) To (4)_DTo return to.

As a result, the count value (n) of the counting section (341)
₁ ) is compared with the count value (n ₂ ) of the counting unit (342), and the synchronization monitoring unit (343) compares the count value (n ₁ ) with (4) _D and sets the processor ( CP
U) (34) during one second from time (t ₅₁ ) to (t ₅₂ )
Buffer memory (RAM) (31 ₁ ) of audio data (d ₄ ) specified by count value (n ₂ ) [= (4) _D ]
Transfer to the upstream highway ( _4U ).

As a result, the direct memory access control device (DMC) (35)
Under the control of 4), the audio data (d) is transmitted for one second from the time (t ₅₁ ) following one second from the time (t ₅ ) to (t ₅₁ ).
₄ ) is sequentially extracted from the buffer memory (RAM) (31 ₁ ), transferred to the serial-parallel mutual conversion device (PSR) (36), converted from a parallel code to a serial code, and transmitted to the upstream highway ( _4U ). .

When one second has elapsed from the time point (t ₅₁ ) (t
₅₂ ), the processor (CPU) (34) updates the count value (n ₂ ) of the counting section (342) again from (4) _D to (5) _D , and outputs the sound from the buffer memory (RAM) (31 ₀ ). Attempting to start extracting the data (d ₅ ), as described above, the audio data (d ₅ ) has not yet been stored in the buffer memory (RAM) (31 ₀ ) even at the time (t ₅₂ ), The count value (n ₁ ) of the counting unit (341) is (4) _D
Is held in.

The synchronization monitoring unit (343) determines that the audio data (d ₅ ) has not yet been stored in the buffer memory (RAM) (31 ₀ ) at the time (t ₅₂ ), as at the time (t ₅₁ ). Yes, it is determined that the reproduction of the audio data (d ₅ ) is in an asynchronous state, and the synchronization adjuster (345) is activated as in the case of the time (t ₅₁ ).

The activated synchronization adjustment unit (345), based on the determination result of the synchronization monitoring unit (343), outputs the audio data (d
Still buffer memory even ₅₎ time (t ₅₂₎ (R
AM) (31 ₀ ) recognizes that the accumulation has not been completed,
The updating of the count value (n ₂ ) of the counting section (342) to (5) _D is invalidated, and the count value (n ₂ ) is returned to (4) _D.

As a result, the synchronization monitoring unit (343) is designated by the count value (n ₂ ) [= (4) _D ] within one second from the time point (t ₅₂ ), as in the time point (t ₅₁ ). Memory (RAM) (31) for audio data (d ₄ )
Transfer from ₁ ) to the upstream highway ( _4U ) is permitted.

As a result, the direct memory access control device (DMC) (35)
Under the control of 4), and one second of time (t ₅₎ to (t _51), followed by one second of time (t ₅₁₎ to (t _52), the further one second from the time (t ₅₂₎ , Audio data (d ₄ ) are sequentially extracted from the buffer memory (RAM) (31 ₁ ), transferred to the serial-parallel mutual conversion device (PSR) (36), converted from parallel codes to serial codes, and _U ).

Eventually, the audio data (d_Five) Transfer at the time
(T_Five) And at least two seconds and less than three seconds (t_Five′)
Is completed, and the counting value (n₁)But
(4) _DFrom (5)_DAt the time (t
₅₂) One second after (t)₆) Contains audio data (d₆)
Is started, and the audio data (d₆) Transfer successfully
At the end, the time (t₆') Contains audio data (d₆)But
Buffer memory (RAM) (31₁)
The counting value (n) of the counting unit (341).₁) Also (6) _DTo
Be renewed.

In this state, at the time (t₅₂) From 1 second
Time (t₆), A processor (CPU) (34)
Is the count value (n) of the counting unit (342) again._Two) To (4)_DOr
(5)_DIs updated, the synchronization monitoring unit (343)
The count value (n) of several parts (341) ₁) And a counting unit (342)
Count value (n_Two) And count value (n₁) Already
(5)_DConfirm that it has been set to
(T₆) Already has audio data (d_Five) Is a buffer
Memory (RAM) (31₀) Is determined to be stored in the
Data (d_Five), Buffer memory (RAM) (31)₀)
From the highway (4 _U).

As a result, the direct memory access control device (DMC) (35)
Under the control of 4), the audio data (d ₅ ) is sequentially extracted from the buffer memory (RAM) (31 ₀ ) for one second from the time (t ₆ ), and the serial-parallel mutual conversion device (PSR) (36)
And converts it from a parallel code to a serial code and sends it out to the upstream highway ( _4U ).

Similarly, the direct memory access system
The control device (DMC) (35) is a processor (CPU) (3
Under the control of 4), the time (t₆) Through (t)₆'),(Time
Point (t₇) Through (t)₇'), (T₈) Through (t)₈')of
In the meantime, audio data (d₆), (D₇),
(D₈) From the disk drive (DK) (32),
Transfer to the buffer memory (RAM) (31)
Accumulate and in parallel with this, processor (CPU) (34)
At the time (t₆) And at a time interval of one second (t₇),
(T₈), (T₉) Includes the count value (n) of the counting unit (342).
_Two) To (6)_D, (7) _D, (8)_DUpdate and sync
The count value (n₁)
Audio data stored in the buffer memory (RAM) (31)
Ta (d₆), (D ₇), (D₈) At time (t₇),
(T₈), (T₉) And serial-parallel phase
Transfer to the PSR (36) and convert from parallel code
After converting to serial code, the upstream highway (4_U)
You.

As is clear from the above description, according to the present embodiment, the processor (CPU) (34) transfers the audio data (d ₅ ) from the buffer memory (RAM) (31 ₀ ) to the upstream highway (4 _U ). When the transfer is attempted, the synchronization monitoring unit (343) compares the count value (n ₁ ) of the counting unit (341) with the count value (n ₂ ) of the counting unit (342), thereby obtaining the audio data (d _5). ) Is monitored, and if it is determined that the reproduction is in an asynchronous state, the update of the count value (n ₂ ) is invalidated by the synchronization adjustment unit (345). While the data (d ₄ ) is repeatedly reproduced, the synchronization state is continued, and the reproduction of the audio data is prevented from being interrupted.

2 and 3 are merely examples of the present invention. For example, the object of the present invention is not limited to the reproduction of audio data. The application of the present invention is also considered when accumulating in ()), but the effect of the present invention does not change even in such a case.

[0054]

As described above, according to the present invention, even if the transfer of the audio data in the audio storage / reproduction device becomes asynchronous, the transfer of the audio data can be continued in the audio storage / reproduction device. Interruption of the audio data transfer process can be prevented, and the reliability of the audio storage / reproduction device improves.

[Brief description of the drawings]

FIG. 1 illustrates the principle of the present invention.

FIG. 2 is a diagram showing an audio storage / playback apparatus according to an embodiment of the present invention;

FIG. 3 is a diagram showing an example of an audio data reproducing process in FIG. 2;

FIG. 4 is a diagram showing an example of a conventional audio storage / playback apparatus.

FIG. 5 is a diagram showing an example of an audio data reproducing process in FIG. 4;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 exchange 2 subscriber 3, 100 voice storage and playback device 4 _D down highway 4 _U up highway 31 buffer memory (RAM) 32 disk device (DK) 33 disk control device (DKC) 34 processor (CPU) 35 direct memory access control device (DMC) 36 serial-parallel mutual conversion device (PSR) 101 audio data transfer path 102 audio data storage means 103 provisional storage means 111 transfer continuation means 341 counting section 342 counting section 343 synchronization monitoring section 344 transfer stopping section 345 synchronization adjustment section

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yutaka Yamauchi 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu ACS Co., Ltd. Nagoya Communication System Co., Ltd. (56) References JP-A-1-209856 (JP, A) JP-A-5-37640 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04M 3/42-3/58 G06F 3/06-3/08 G06F 13/38-13/42

Claims (3)

(57) [Claims] 1. An audio storage / reproducing apparatus for transferring audio data between an audio data transfer path and an audio data storage means by alternately using two temporary storage means, wherein the temporary storage means and the audio data storage are transferred. Monitoring the transfer of the audio data between the means and the transfer of the audio data between the temporary storage means and the audio data transfer path,
If both of the transfers are determined to be in an asynchronous state , the transferred
Keep the synchronization state while playing the audio data repeatedly
The Rukoto, wherein without disrupting both transfer audio data transfer method characterized by providing a transfer continues means for continuing. 2. The transfer continuation unit, when transferring the audio data from the audio data storage unit to the audio data transfer path, alternately reaches the two temporary storage units from the audio data storage unit. When the transfer of the audio data is delayed, the same audio data stored in the temporary storage unit is repeatedly reproduced until normal audio data is transferred from the audio data storage unit to the temporary storage unit.
2. The audio data transfer method according to claim 1, wherein the data is transferred to the audio data transfer path. 3. The two provisional means for outputting the audio data alternately when transferring the audio data from the audio data transfer path to the audio data storage means. When the transfer of the audio data from the storage unit to the audio data storage unit is delayed, the audio data may be discarded until normal audio data can be transferred to the audio data storage unit. As the transfer of the audio data from the audio data transfer path to said interim memory means
2. The audio data transfer method according to claim 1, wherein the audio data transfer method is continued.