JP3145769B2 - Semiconductor surface emitting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor surface light emitting device, and more particularly, to forming a current confinement structure (blocking layer) around a light emitting region by one film growth using one kind of dopant. The present invention relates to a planar light emitting device.

[0002]

2. Description of the Related Art As a conventional surface emitting device, as shown in FIG. 1, reflecting mirrors 2 and 3 are provided above and below an active region 1 for generating light, respectively, and are provided in circular holes formed on a substrate 4 side. (Dielectric multilayer film) A structure in which light is slightly transmitted through the reflecting mirror 2 and emerges is known.

In this conventional surface emitting device, it is necessary to have a structure for confining as much current as possible in order to efficiently stimulate the active region 1 with the current. For this reason,
The conventional surface light emitting device has a problem that the structure is complicated and a complicated process is required for its manufacture.

In manufacturing a surface emitting laser device having a structure as shown in FIG. 1, an n-GaAlAs cladding layer 5 and a GaAs serving as an active region are formed on a substrate 4 by a liquid phase growth method.
s layer 1, p-GaAlAs cladding layer 6, p-GaAl
After forming an As cap layer 7 and leaving the active layer, the cladding layer 6 and the cap layer 7 in a mesa shape by etching,
A vertical pn junction region (pn current confinement layer) 8 is formed around the side of the mesa structure including the active region 1 by regrowth. In the drawing, 9 is an Au / Ge upper electrode, 10 is an Au / Zn lower annular electrode, and 11 is an insulating layer.

However, in this device, since a pn junction region is formed by regrowth by a liquid phase growth method, it is difficult to obtain a high-quality interface, and the number of non-radiative recombination centers increases. However, there is a problem that the leak current increases.

In order to solve this problem, (111)
A step is provided on the surface of the III-V compound semiconductor substrate exposing the A-plane, and Si (IV) is formed on the (111) A-plane substrate having the step by molecular beam epitaxy (MBE).
A surface having a structure in which a doped III-V compound semiconductor layer is grown, whereby a pn junction for confining current is formed around a light emitting region (active region) in one growth using one kind of dopant. Light emitting devices have been proposed.

However, the (111) A plane in which the group III element appears on the surface is inactive, and has lower reactivity than the (111) B plane in which the group V element appears on the surface. In the growth of a Si-doped III-V compound semiconductor layer on a V-group compound semiconductor (111) A substrate by MBE, generally, III-
A special technique is required for preparing a group V compound semiconductor (111) A substrate, and a special technique is required for growing a Si-doped III-V compound semiconductor layer.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor surface light emitting device having a simple structure, a simple manufacturing process, and less restrictions on the fabrication.

[0009]

SUMMARY OF THE INVENTION A step having a central flat surface and an inclined surface surrounding it is formed on a substrate surface, and a compound semiconductor layer constituting an active layer is formed thereon by a molecular beam epitaxy (MBE) growth method. To simplify the structure by forming a lateral pn junction for current confinement and / or a non-laminated insulating region around the active region. In the present invention, the group IV element doped into the group III-V compound semiconductor includes C, Ge in addition to Si.
Can also be used.

Further, according to the present invention, the II
Group IV compound semiconductor (111) B substrate or (10)
0) In the layer laminated on the substrate or the (111) A substrate, between the layer on the flat surface of the step portion and the layer on the adjacent slope, or on the other flat surface adjacent to the layer on the slope. A configuration in which a pn junction formed between the layers is used as a light emitting source is also conceivable.

[0011]

According to the above construction, it is possible to easily provide a semiconductor surface light emitting device having a simple structure, a simple manufacturing process, and less restrictions on fabrication.

[0012]

Embodiments of the present invention will be described below.

(Embodiment 1) FIG. 2 shows an embodiment of the first invention of the present invention, and is a cross-sectional view of a semiconductor surface light emitting device according to the present invention. In the manufacture of this device, first, an equilateral triangle pattern is formed by photolithography on a GaAs substrate 21 whose surface is the (111) B plane, and then a flat surface is formed on the surface of the GaAs substrate 21 by wet etching. Seen from the top, an equilateral triangular step 21
a was formed. The step 21a is surrounded by a slope having an angle θ of about 70 ° with the surface of the substrate 21. Then, n-AlAs / G doped with Si by MBE method.
An aAs multilayer film (reflection mirror) 22 was grown. Then, S
An i-doped n-AlGaAs cladding layer 23 was laminated. An Si-doped GaAs active layer 24 was formed thereon. Be-doped p-A on this active layer 24
lGaAs cladding layer 25 and Be-doped p-G
An aAs cap layer 26 was formed.

In the Si-doped GaAs active layer 24, whether or not p-type and n-type regions were formed was evaluated by cathode luminescence (CL) at the stage when the active layer 24 was formed.

FIG. 3 shows cathodoluminescence (CL) emission spectra of the flat layer 24a located on the upper flat surface of the step portion 21a and the inclined layer 24b located on the slope of the step portion 21a measured at a temperature of 78K. Was. As can be seen from FIG. 3, the peak wavelength of light emission from the inclined layer (820 nm) is equal to the peak wavelength of light emission from the flat layer (80 nm).
3 nm). Since each has a characteristic emission wavelength of p-type and n-type, the active layer 24 has a p-type gradient layer 2
4b and the n-type flat layer 24a were formed, and it was found that pn junctions arranged in the horizontal direction were formed. Note that the flat layer 24a forms an active region.

The Si-doped GaAs active layer 24
In the above, whether p-type and n-type regions are formed can also be checked by forming an electrode on the active layer after forming the active layer 24 and examining light emission from the pn junction. evaluated.

FIG. 4 shows the pn formed between the flat layer 24a and the inclined layer 24b measured at a temperature of 12K.
The emission spectrum from the junction is shown. The emission spectrum in the near-infrared wavelength region shown in FIG. 4 indicates that a good pn junction is formed in the portion to be measured.

In this surface light emitting device, the cap layer 26
After etching the central flat layer, the insulating film 27 and the electrode 2
8 and finally a reflective film 29 was laminated on the exposed surface of the cap layer 26. The GaAs (111) B
The electrode 30 is formed on the opposite surface of the substrate 21. In this surface emitting device, the reflection mirror 22 and the reflection mirror 29 act as a resonator, and output light from the upper surface of the drawing.

In the surface light emitting device, since the (111) B plane is a crystal plane having three-fold symmetry, all three slopes around the equilateral triangle can have the same property. By arranging the triangular patterns, it is easy to manufacture a structure in which the surface light emitting elements are arranged two-dimensionally.

(Embodiment 2) The same method as that of the first invention can be applied to a III-V compound semiconductor (100) substrate surface.

First, as shown in FIGS. 5, 6 and 7, the III-V compound semiconductor (100) substrate 40
And a step portion 41 having a two-fold symmetric region is formed thereon. The step portion 41 is surrounded by a slope (tapered slope) 41a that forms an angle of 90 ° or less with the substrate surface and a slope (reverse tapered slope) 41b that forms an angle of 90 ° or more. A GaAs layer 51 doped thereon with an amphoteric impurity group IV element (C, Si, Ge, etc.) by MBE.
To form an n-type flat layer (active region) 5
A p-type slope layer 51b and an insulating region 51c can be formed around 1a. Thereby, III-
A surface emitting device using a group V compound semiconductor (100) substrate can be manufactured.

In each of the above embodiments, the step formed on the substrate surface is formed in a convex shape, but may be formed in a concave shape dug into the substrate.

[0023]

The device according to the present invention has a special orientation having a step formed by a flat surface and an inclined surface surrounding the flat surface.
Molecular beam epitaxy (MB) is applied to the IV group semiconductor substrate surface.
E) The amphoteric impurity group IV element (C, Si, G
e))-grown III-V compound semiconductor layer to grow a current confinement structure having n-type conductivity on the flat surface and p-type conductivity (or insulation) on the slope And a structure surrounding the active region, and the current confinement structure can be manufactured by one growth using one kind of dopant. Therefore, according to the present invention, it is possible to easily obtain a semiconductor surface light emitting device having a simple structure having a carrier confinement region two-dimensionally around an active region.

The results of the second evaluation experiment shown in Example 1 are as follows:
This shows that the pn junction formed by the present invention itself can be used as a light emitting active layer.
In this case, the active layer is perpendicular to the substrate surface, and a light emitting device using the active layer has advantages such as higher integration.

The light emission from the pn junction was measured in Example 1.
The p-type region and n formed on the (100) substrate shown in Example 2 or on the (111) A substrate used in the related art as well as the (111) B substrate shown in FIG.
It is also observed from the pn junction between the mold region.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of a conventional surface light emitting device.

FIG. 2 is a cross-sectional structural view of an example of a surface emitting device according to the present invention having a lateral pn junction.

FIG. 3 is an emission spectrum diagram of cathodoluminescence in a region of a (111) B plane portion of a step portion and a region of a slope portion on a substrate.

FIG. 4 is a current injection emission spectrum diagram from a pn junction between an n-type region on a (111) B plane portion of a step portion and a p-type region on a slope portion on a substrate.

FIG. 5 is a plan view of a current confinement structure formed on a (100) substrate.

6 is a cross-sectional configuration diagram of a current confinement structure taken along a line VI-VI in FIG.

7 is a cross-sectional configuration diagram of a current confinement structure along the line VII-VII in FIG.

[Description of Signs] 21 GaAs whose surface is a (111) B plane
Substrate 21a Stepped portion 22 Si-doped n-AlAs / GaAs multilayer film (reflection film) 23 Si-doped n-AlGaAs cladding layer 24 Si-doped GaAs active layer 24a n-type upper flat layer 24b p-type inclined layer 24c n-type lower flat Layer 25 Be-doped p-AlGaAs cladding layer 26 Be-doped p-GaAs cap layer 27 Insulating film 28 Electrode 29 Reflective film 30 Electrode 40 III-V compound semiconductor (100) substrate 41 Step portion having twice symmetric region 41a Slope having an angle of 90 ° or less with the substrate surface (tapered inclined surface 41b) Slope having an angle of 90 ° or more with the substrate surface (reverse tapered inclined surface) 51 GaAs layer doped with an amphoteric impurity group IV element 51an Type flat layer (active region) 51b p-type slope layer 51c insulating region

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Isao Fujimoto 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Norio Kobayashi 5 Hiratani ATR Optical Co., Ltd. (72) Inventor Teiji Yamamoto Incorporated, Kyoto Prefecture, Soraku-gun Seika-cho Oaiya small character 5 Hiratani 5th ATR Optical Co., Ltd. Inventor Makoto Inai Kyoto, Soraku-gun, Seika-cho, Oita, Sanai, 5 Sanraya, ATR Optical Co., Ltd. (56) References JP-A-5-226778 (JP, A) JP-A-63- 24692 (JP, A) JP-A-63-84186 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01S 5/00-5/50 JICST File (JOIS)

Claims (3)

(57) [Claims] 1. A III-V compound semiconductor (111) B
A step portion consisting of a flat surface and a side slope surrounding the flat surface is formed on the substrate surface of the substrate, and a III-V compound semiconductor layer containing a group IV amphoteric impurity is formed on the substrate surface having the step portion by a molecular beam. The layers on the flat surface of the stacked semiconductor layer are n-type conductive, the regions on the inclined surface are p-type conductive, and the layer on the flat surface is an active layer. And the n-type active layer and the p-type conductive layer on the inclined surface two-dimensionally continuous with it form a lateral pn junction layer for confining current. Semiconductor surface emitting device. 2. A step portion comprising a flat surface, a tapered side slope surrounding the flat surface, and a reverse tapered slope is formed on the substrate surface of the III-V compound semiconductor (100) substrate. A group III-V compound semiconductor layer containing a group IV amphoteric impurity is laminated on a substrate surface having a portion by molecular beam epitaxy, and a region on the flat surface of the step portion of the laminated semiconductor layer has n-type conductivity. In addition, the region on the inclined surface shows p-type conductivity, the layer on the flat surface becomes an active layer, and the n-type active layer and the p on the inclined surface two-dimensionally continuous with the n-type active layer. The conductive layer forms a lateral pn junction layer for confining current, and the non-stacked region on the reverse tapered inclined surface of the step forms an insulating region for confining current. A semiconductor surface-emitting device characterized by the above-mentioned. 3. A III-V compound semiconductor (111) B
A step portion composed of a flat surface and a side slope surrounding the flat surface is formed on the substrate surface of the substrate or (100) substrate, and II containing a group IV amphoteric impurity is formed on the substrate surface having the step portion.
A group IV compound semiconductor layer is laminated by molecular beam epitaxy, and a region on the inclined surface of the laminated semiconductor layer exhibits p-type conductivity, and a region on the flat surface and a region on another flat surface. And n indicate n-type conductivity, and a pn junction formed between one of the n-type regions and the p-type region constitutes a light-emitting source.