JP3143551B2 - Synchronous tracking device for spread spectrum signal - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous tracking apparatus for a spread spectrum signal used in a receiving apparatus for a DS-SS (Direct Spread Spectrum-Spread Spectrum) signal.

[0002]

2. Description of the Related Art For example, DS- using a digital correlator
Japanese Patent Application Laid-Open No. 4-151924 discloses an SS signal receiving apparatus.
Japanese Unexamined Patent Publication (KOKAI) No. 2000-205,086 is known. This has the configuration shown in FIG. That is, 1 is an antenna, 2 is a high frequency amplifier, 3 is a mixer, 4 is a local oscillator, 5 is a band pass filter, 6 and 7 are mixers, and 8 is π / 2 (rad).
Phase shifters, 9 and 10 are low-pass filters, 11 and 12 are A
/ D converters, 13 and 14 are digital correlators, 15 and 16
Is a squaring circuit, 17 is an adder, 18 is a correlation pulse timing decision circuit, 19 is a correlation pulse extraction system circuit, 20 is a data decision circuit, 21 is a VCO correction amount detection circuit, 22 is a loop filter, and 23 is a carrier wave reproduction. VCO (Volt
age Controlled Oscillator).

In this receiving apparatus, a mixer 6, a low-pass filter 9, an A / D converter 11, a digital correlator 1
The squaring circuit 15 is a circuit system related to the signal of the in-phase axis component (I component) of the received signal, and includes a mixer 7, a low-pass filter 10, an A / D converter 12, a digital correlator 14,
The multiplying circuit 16 is a circuit system related to the signal of the orthogonal axis component (Q component) of the received signal.

[0006] As shown in FIG. 6, a correlation pulse timing judging device 18 is connected to frame memories 181 to 18 connected in series.
6, an adder 187, and a maximum value timing determination circuit 188. Each of the frame memories 181 to 186
It has a memory length of one information symbol duration unit (in many cases, one information symbol duration corresponds to a spreading code length), and is constituted by a shift register or the like.

An input terminal 131 receives an A / D-converted signal I of an in-phase component, and an input terminal 141 receives an A / D-converted signal Q of an orthogonal component. The digital correlators 13 and 14 perform a correlation operation. The digital correlator 13 outputs a correlation signal of an in-phase axis component, and the digital correlator 14 outputs a correlation signal of an orthogonal axis component. Each of the correlation signals is squared by the squaring circuits 15 and 16 and then added by the adder 17. The added output is input to the input terminal 180 of the correlation pulse timing determiner 18.

Each of the frame memories 181 to 186 shifts the contents stored in accordance with the input clocks of the digital correlators 13 and 14, and adds the contents of each of the frame memories 181 to 186 at a specific time by an adder 187. When each of the frame memories 181 to 186 is constituted by a shift register, the contents of the same stage of each shift register are added to an adder 187.
To be output.

[0007] The maximum value timing determination circuit 188 observes the output signal of the adder 187 for one information symbol time, and outputs from the terminal 189 the timing at which the maximum level of the correlation pulse is given.

The correlation pulse extraction circuit 19 has a terminal 189
The digital correlator output signal is sampled in accordance with the correlation pulse extraction timing output from, and is output to the data determination circuit 20. Data determination circuit 20 decodes the received data based on this signal.

In Japanese Unexamined Patent Publication No. 3-207134, as shown in FIG. 7, a peak position detecting circuit 31, a peak position determining circuit 32, a counting circuit 33, and an m / N determining circuit 3 are provided.
4, the detection circuit 31 detects the correlation peak position of the correlation signal between the received signal and the small-quantity code sequence over N consecutive periods for each period of the code sequence, and detects the detected peak position of the divided area within one period. The determination circuit 32 determines to which position it belongs, and counts the number of detected peaks belonging to each area by the counting circuit 3.
When the number of detection peaks detected in any one of the divided areas becomes m or more during N cycles, synchronization is considered to be established. When the synchronization is established, the divided area that has reached the predetermined number m is a code sequence. It discloses that a periodic signal is created to be at the center of the cycle.

[0010]

Problems to be Solved by the Invention
No. 4, the frame memories 181 to
186 are connected in series, and a signal input from the input terminal 180 is serially transferred to each frame memory. Therefore, inconvenience occurs, for example, when changing the spread code length.

That is, in the DS-SS communication system, one cycle of the spreading code is usually assigned to one information symbol. Therefore, in order to change the spread code length, the length of each frame memory must be changed, and the position of a tap for extracting a signal from each frame memory must also be changed. However, this publication does not have a configuration that can easily cope with the change, and there is a problem that the change is extremely troublesome.

Further, in Japanese Unexamined Patent Publication No. 3-207134, even if synchronization can be established, synchronization cannot be maintained. In addition, even if the difference from the values of the other divided areas is large or small in one cycle, the largest one is selected. For example, when the desired wave is smaller than the undesired wave. That is, the D / U ratio is dB
If the unit is minus, there is a risk that the detection of the desired wave is overlooked. For example, there is a problem that the correlation value of the divided area that outputs the signal corresponding to the desired wave is always the second or third highest value in each cycle, and is not determined as the maximum peak position although the total is maximum. .

Accordingly, the present invention provides a spread spectrum signal synchronization tracking apparatus which can flexibly cope with a change in the spread code length and can improve the practicality.

Further, the present invention accurately samples the correlation value of a desired wave even when the correlation value of a chip outputting a signal corresponding to the desired wave is always the second or third highest value in each cycle. Provided is a synchronous tracking device for a spread spectrum signal which can output a sampling pulse correctly only once in one cycle of maximum value detection.

[0015]

The invention corresponding to claim 1 is:
It comprises a digital correlator for correlating the sampled sequence of the received signal with the spreading code and outputting a correlation pulse of a magnitude corresponding to the degree of correlation, an arithmetic circuit for calculating the correlator output, and a plurality of stages. A first shift register capable of parallel output for shifting the time series data of the output of the arithmetic circuit for each chip time of the data, a sampling generation circuit for generating a shift timing signal of the first shift register, and a sampling generation circuit A counter that counts the output of the circuit and generates a parallel shift timing signal for each period of the spreading code according to a preset count value; The parallel output of each stage is a serial input, and the parallel shifts in response to the parallel shift timing signal from the counter. Of consisting force capable plurality of stages second
And a plurality of sums of the parallel output of each stage of the first shift register and the parallel output of each stage of each second shift register corresponding to each stage of the first shift register. An addition circuit, and a maximum value timing detection circuit that detects an addition circuit that gives the maximum value of the added correlation pulse from the output of each of the addition circuits, and detects a timing that gives the maximum value of the added correlation pulse. .

According to a second aspect of the present invention, a received signal is sampled.
The correlation between the sequence and the spreading code is calculated, and
Digital correlator that outputs a correlation pulse of
An arithmetic circuit for calculating the output of the function unit , and generating a chip select address for each one-chip time of the time series data of the arithmetic circuit output in accordance with a preset address value, and synchronizing with the chip select address. generating a data shift timing signal, a timing generating circuit addressable value variable to be set, the data of each sheet
Real input, and this input data is
Path is generated by the data shift timing signal.
A plurality of shift registers capable of parallel output,
Chip select add generated by the timing generator
Circuit switching in response to the
Time-series data that has been cut for each
, A plurality of adders for calculating the sum of the parallel outputs of each stage of each shift register, and an adder that gives the maximum value of the added correlation pulse from the output of each adder. In addition, a maximum value timing detection circuit for detecting a timing at which the maximum value of the added correlation pulse is given is provided.

According to a third aspect of the present invention, in the apparatus for tracking a spread spectrum signal according to the first or second aspect, the correlation output corresponding to the timing at which the maximum value detected by the maximum value timing detection circuit is given is sampled. Means and control means for controlling the timing at which the maximum value detected by the maximum value timing detection circuit is provided to be located near the middle of one code cycle.

[0018]

According to the first aspect of the present invention, the first shift register shifts the output data of the arithmetic circuit every one chip time. When the count of the counter reaches a value equal to the code length, the counter generates a parallel shift timing signal. The first shift register outputs data in parallel according to the parallel shift timing signal. Each second shift register shifts data in accordance with a parallel shift timing signal and takes in a parallel output from the first shift register in a first stage.
The data of each stage is output in parallel. Thus each second
Each stage of the shift register holds the past data of a certain stage of the first shift register, and one stage of the second shift register corresponds to a time interval of one cycle of the spread code. Become.

Each adder circuit outputs the sum of the outputs of the corresponding stages of the first shift register and the corresponding stages of the second shift register. The maximum timing detection circuit detects an addition circuit that outputs the largest value from the outputs of the respective addition circuits, and outputs a pulse at a phase timing corresponding to that position.

Since the counter can change the count value to be set, if the count value is within the number of stages of the first shift register, the count value to be set in the counter is changed so that the spread code having a different length can be obtained. Can deal with it.

In the invention according to claim 2, the data selection circuit sequentially allocates data from the arithmetic circuit to data output to each shift register in accordance with a timing and an address generated by the timing generation circuit. Since the timing generation circuit switches the chip select address for each one-chip time of the time series data output from the arithmetic circuit, the output data of the arithmetic circuit is sequentially input to the input terminal of each shift register for each chip. Further, the timing generation circuit simultaneously outputs a data shift timing signal to the shift register that has issued the chip select address. The shift register sequentially outputs the input data according to the data shift timing signal and also outputs the data to the parallel output terminal.

Therefore, in each stage of each shift register, a portion corresponding to the same phase of the output data of the arithmetic circuit is held for each cycle.

Each adder circuit calculates the sum of the parallel outputs of each stage of each shift register. The maximum timing detection circuit detects an addition circuit that outputs the largest value from the outputs of the respective addition circuits, and outputs a pulse at a phase timing corresponding to that position.

Since the timing generation circuit can change the address value to be set, if the address value is within the number of shift registers, the address value to be set in the timing generation circuit is changed so that spread codes having different lengths can be obtained. Can deal with.

Further, in the invention according to claim 3,
The correlation output corresponding to the timing at which the maximum value detected by the maximum value timing detection circuit is given is sampled, and the timing at which the maximum value is given is controlled so as to be located near the middle of one code cycle.

[0026]

An embodiment of the present invention will be described below with reference to the drawings. The overall configuration of the DS-SS signal receiving device is the same as that in FIG.

This embodiment is an embodiment corresponding to claim 1.
There, in block diagram FIG. 1 showing a main portion, 41 denotes an input terminal for inputting a signal of the A / D-converted in-phase axis component (I component), 42 A / D-converted quadrature-axis component (Q component ) Is an input terminal for inputting a signal.

An in-phase component signal input to an input terminal 41 is supplied to a first digital correlator 43, and a quadrature component signal input to an input terminal 42 is supplied to a second digital correlator 44.
To supply.

Numeral 45 is an arithmetic circuit.
A pair of squaring circuits 46 and 47 and an adder 48 are provided.
The first digital correlator 43 performs a correlation operation on the signal of the in-phase axis component, and supplies the obtained correlation signal to the squaring circuit 46. The second digital correlator 44 performs the correlation operation on the signal of the quadrature axis component. The calculation is performed, and the correlation signal is supplied to the squaring circuit 47. And each squared circuit 4
The outputs of 6, 47 are added by the adder 48, and the time series data obtained by the addition is supplied to the input terminal 50 of the correlation pulse timing determiner 49.

The correlation pulse timing decision unit 49
For example, a first shift register 51 having an eight-stage configuration,
Eight second shift registers 521, 5 having a five-stage configuration provided corresponding to each stage of the shift register 51 of FIG.
.., 527, 528 are provided.

The first shift register 51 sequentially shifts and stores time-series data input to the input terminal 50 and can output data in parallel from each stage. Each of the second shift registers 521 to 528
Are used to sequentially shift and store the parallel output from the first shift register 51 and to store data in each stage 5211, 5212,
5213, 5214, 5215, 5221, 5222, 5223, 5
224, 5225, ... 5271, 5272, 5273, 5274, 5
275, 5281, 5282, 5283, 5284, and 5285 can output data in parallel.

The correlation pulse timing determiner 4
Reference numeral 9 denotes a sampling generation circuit 53 that generates a shift timing signal SHT of the first shift register 51, counts the shift timing signal SHT from the sampling generation circuit 53, and sets a spread code 1 according to a preset count value. A counter 54 that generates a parallel shift timing signal PST for each cycle, a sum of parallel outputs of the respective stages of the first shift register 51 and parallel outputs of the respective stages of the second shift registers 521 to 528,
.. 557, 55 which are respectively calculated for each stage of the first shift register 51.
8 and the output of each of the adder circuits 551 to 558, an adder circuit that gives the maximum value of the added correlation pulse is detected from the output, and the timing at which the maximum value of the added correlation pulse is given is detected from the output terminal 57. A maximum value timing detection circuit 56 that outputs a sampling pulse is provided. The counter 54 inputs a preset count value from a data input terminal 58.

The first shift register 51 receives the parallel shift timing signal P from the counter 54.
ST outputs a parallel output.
Each of the second shift registers 521 to 528 receives the parallel shift timing signal P from the counter 54.
The shift is performed sequentially by ST.

As shown in FIG. 2, the maximum value timing detection circuit 56 includes a selection circuit 61, a comparison circuit 62, an area select signal generation circuit 63, a ring counter 64, first and second holding circuits 65 and 66, The selection circuit 61 includes input control circuits 551 to 551.
Select and output from the added output from 58.

The first holding circuit 65 holds the maximum value so far, and when a new maximum value is output from the selection circuit 61, the comparison circuit 62 stores the new maximum value and the first maximum value.
Is compared with the maximum value previously held in the holding circuit 65, and when the new maximum value is large, the contents of the first holding circuit 65 are rewritten to the new maximum value. Then, the value of the ring counter 64 at that time is held by a second holding circuit 66.

The ring counter 64 counts a numerical value corresponding to the code length, for example, 8 at the timing when a clock is input. When counting up to 8, the numerical value returns to 1. The area select signal generating circuit 63 outputs area select signals ASS1 to ASS8 in accordance with the count value of the ring counter 64. This area select signal ASS1
ASS8 are input to the respective adding circuits 551 to 558 so as to perform the adding operation of the adding circuits, and are input to the selecting circuit 61 to select the added output.

The control section 67 outputs a clear signal CL1 to the first holding circuit 65 so as to start the maximum value detection from the adding circuit 551 at first, and clears the holding circuit 65 and the second holding circuit 66. To output the clear signal CL2 to clear the holding circuit 66. When the maximum value is detected, the clear signal CL is set so that the detection of the maximum value is performed in the middle of one code period for detecting the maximum value.
1, the output timing of CL2 is changed.

In the embodiment having such a configuration, the time series data from the arithmetic circuit 45 is inputted to the first stage of the first shift register 51 via the input terminal 50. The first shift register 51 stores the data from the arithmetic circuit 45 in the first stage while sequentially shifting the data by the shift timing signal SHT from the sampling pulse generating circuit 53.

The counter 54 counts the shift timing signal SHT from the sampling pulse generating circuit 53, and outputs a parallel shift timing signal PST every time, for example, eight shift timing signals SHT are counted. That is, the counter 54 has the count value “8” in advance.
Is set. This count value is equal to the number of chips of the spreading code.

The first shift register 51 includes a counter 5
4 outputs the data of each stage in parallel and clears the data of each stage in accordance with the parallel shift timing signal PST. Each of the second shift registers 521 to 528
Shifts the data of each stage to the next stage according to the parallel shift timing signal PST from the counter 54 and outputs the data in parallel.

Each of the adders 551 to 558 finds the sum of the data corresponding to each phase. That is, the adder circuit 551 obtains the sum of the parallel output of the first stage of the first shift register 51 and the parallel output of each stage of the second shift register 521. Similarly, adders 552-5
Numeral 58 indicates the sum of the parallel outputs of the second to eighth stages of the first shift register 51 and the parallel outputs of the respective stages of the second shift registers 522 to 528.

Thus, each of the adders 551 to 558 outputs a result obtained by adding the data input to the input terminal 50 to the data of six cycles for each chip.

The maximum value timing detection circuit 56 sequentially takes in the outputs of the respective adders 551 to 558 from the selector 61 while counting the ring counter 64, and compares the outputs of the respective adders 551 to 558 with the comparator 62. Then, the first holding circuit 65 holds the maximum value, and the second holding circuit 66 holds the value of the ring counter 64 at that time.

Then, the control section 67 detects the position of the addition circuit which outputs the largest value to the first holding circuit 65 from the maximum value and the value of the second holding circuit 66. If the position of the adder circuit corresponds to the stage at the end of the first shift register 51, the position of the adder circuit that outputs the maximum value by changing the clearing timing of each of the holding circuits 65 and 66 is changed. The shift register 51 is controlled so as to be in the vicinity of the center of the shift register 51, that is, in the vicinity of the middle of one code period for detecting the maximum value.

Then, the timing for giving the maximum level of the correlation pulse is sampled from the position of the adder circuit and the count value of the counter 54, and a sampling pulse is output from the output terminal 57 at that timing.

In this apparatus, when the spread code length is changed to a value smaller than 8, the count value set in the counter 54 is reduced according to the changed spread code length. In this case, the change in the count value may be smaller than the number of stages of the second shift registers 521 to 528.

Due to this change in the count value, the first shift register 51 operates only in the stage preceding the set count value, and
Only the shift register corresponding to the stage in which the shift register operates operates. The stage after the count value set in the first shift register 51 is always in the clear state.

When the spreading code length is changed to be equal to or less than the number of stages of the first shift register 51, the change can be flexibly dealt with and the practicality can be improved.

Also, for example, even if the desired wave is smaller than the non-desired wave in each cycle and is always the second or third, the desired wave can be reliably detected if the sum of the six rounds is maximum.

The maximum value timing detection circuit 56
Since the maximum value is detected and the correlation peak is sampled for each correlation output, synchronization is established for each correlation output. As a result, synchronization is maintained by repeating synchronization supplementation. Therefore, there is no need to separately provide a circuit for maintaining synchronization.

Further, since the maximum value detection can be controlled to be performed near the middle of the code length, the sampling pulse output from the output terminal 57 can be surely performed only once in one cycle of the maximum value detection. Detection can be performed stably.

Next, another embodiment of the present invention will be described with reference to the drawings. The same parts as those in the above embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is an embodiment corresponding to claim 2.
As shown in FIG. 3, the correlation pulse timing determiner 49 includes a data selection circuit 61, eight six-stage shift registers 621, 622,..., 627, 628, a timing generation circuit 63, addition circuits 551 to 558, and a maximum. It comprises a value timing detection circuit 56.

The timing generation circuit 63 generates a chip select address every one chip time of the time-series data output from the arithmetic circuit 45 in accordance with a preset address value, and outputs the chip select address and the chip select address. A synchronous data shift timing signal is generated, and a count value for setting an address value is input from an input terminal 68. Chip select
The address and data shift timing signals are generated such that the address makes one cycle per one cycle of the spreading code.

The data selection circuit 61 performs circuit switching in accordance with the chip select address generated by the timing generation circuit 63, and sequentially supplies the time series data from the arithmetic circuit 45 to each of the shift registers 621 to 628. It is supposed to. Each shift register 62
1 to 628 are used as serial inputs for the time-series data separated for each chip by the data selection circuit 61,
Each time data is input by a data shift timing signal generated by the timing generation circuit 63, the data in each stage is sequentially shifted and the data is simultaneously output in parallel. Therefore, each stage of a certain shift register holds only data at a timing corresponding to the same phase of the input time-series data, and there is a phase difference of one cycle between the stages.

Each of the adders 551 to 558 calculates the sum of the parallel outputs of each stage of the shift registers 621 to 628, respectively.

In the embodiment having such a configuration, the time series data from the arithmetic circuit 45 is input to the data selection circuit 61 via the input terminal 50. Then, the data is input to the data selection circuit 61 every chip time according to a clock corresponding to the input clock of the digital correlators 43 and 44 generated by the timing generation circuit 63.

The data selection circuit 61 performs circuit switching according to the chip select address from the timing generation circuit 63, and sequentially supplies input time-series data to each of the shift registers 621 to 628.

Each of the shift registers 621 to 628 receives the data divided for each chip by the data selection circuit 61, sequentially shifts the data of each stage by the data shift timing signal from the timing generation circuit 63, and simultaneously shifts the data. Output data in parallel.

Each of the adders 551 to 558 calculates the sum of the parallel outputs of each stage of the shift registers 621 to 628, respectively. That is, each of the adders 551 to 55
Numeral 8 outputs the result obtained by adding the input time-series data to the data of six cycles for each chip.

The maximum value timing detection circuit 56 takes in the output of each of the addition circuits 551 to 558 and detects the addition circuit that outputs the maximum value. Since the position where the maximum value is detected corresponds to the timing at which the maximum level of the correlation pulse is given, the detection circuit 56 determines the position of the addition circuit that outputs the maximum value and the chip select address generated by the timing generation circuit 63. The timing at which the maximum level of the correlation pulse is given is sampled.

At this time, if the position of the addition circuit that outputs the maximum value is located at the end of one code time period for detecting the maximum value, the detection circuit 56 sets the position of the addition circuit that outputs the maximum value to the maximum value. Control is performed so as to be in the middle of one cycle time of the code for performing the value detection.

The set value of the address generated by the timing generation circuit 63 is at most the number of shift registers, that is, eight.

If the spreading code length is changed to a value smaller than 8, the address value set in the timing generation circuit 63 is reduced according to the changed spreading code length. Due to this change in the address value, the shift register having an address larger than the upper limit of the address does not receive data to be shifted and does not operate. That is, the same operation as the case where the number of shift registers is reduced is performed.

Also in the present embodiment, for example, even if the desired wave is smaller than the non-desired wave and is always the second or third in each period, the desired wave can be surely determined if the sum of the six rounds is maximum. Can be detected.

As described above, in this embodiment, the same effects as in the above embodiment can be obtained.

In each of the above embodiments, the arithmetic circuit 45 has been described as being composed of the square circuits 46 and 47 and the hardware of the adder 48. However, the present invention is not necessarily limited to this. As shown in FIG. , One conversion ROM 69 is used, and the conversion ROM 69 is provided with a data conversion table. The conversion ROM 69 receives (i ² + q ² ) or (i) for the inputs i and q from the digital correlators 43 and 44. ² +
A configuration in which the data conversion output of the square root of q ² ) may be obtained.

The number of shift registers and the number of stages are not limited to those of the above embodiments.

[0069]

As described above, according to the present invention, a change in the spread code length can be flexibly dealt with, and the practicality can be improved.

Further, even when the correlation value of the chip that outputs the signal corresponding to the desired wave is always the second or third highest value in each cycle, the correlation value of the desired wave can be sampled accurately and the sampling can be performed. The pulse can be correctly output only once in one cycle of the maximum value detection.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a maximum value timing detection circuit of the embodiment.

FIG. 3 is a main part block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing another embodiment of the arithmetic circuit.

FIG. 5 is a block diagram showing a configuration of a DS-SS signal receiving device.

FIG. 6 is a block diagram showing a configuration of a conventional correlation pulse timing determiner.

FIG. 7 is a block diagram showing a conventional maximum value timing detection circuit.

[Explanation of symbols]

 43, 44... Digital correlator 45... Arithmetic circuit 49... Correlation pulse timing determiner 51... First shift register 521 to 528. Maximum value timing detection circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields investigated (Int. Cl. ⁷ , DB name) H04B 1/69-1/713 H04J 13/00-13/06 H04L 7/00

Claims (3)

(57) [Claims] 1. A digital correlator for correlating a sampled sequence of a received signal with a spreading code and outputting a correlation pulse of a magnitude corresponding to the degree of correlation, an arithmetic circuit for calculating an output of the correlator, A first shift register capable of parallel output for shifting the time-series data output from the arithmetic circuit for each chip time of the data, and a sampling generation circuit for generating a shift timing signal of the first shift register A counter for counting the output of the sampling generation circuit and generating a parallel shift timing signal for each period of the spread code in accordance with a preset count value; The parallel output of each stage of the first shift register is a serial input, and is responsive to a parallel shift timing signal from the counter. A plurality of second shift registers having a plurality of stages capable of parallel output,
A plurality of adder circuits for respectively calculating the sum of the parallel output of each stage of the shift register and the parallel output of each stage of the second shift register corresponding to each stage of the first shift register; A maximum value timing detection circuit for detecting an addition circuit that gives the maximum value of the added correlation pulse from the output of each addition circuit, and detecting a timing for giving the maximum value of the added correlation pulse. Synchronous tracking device for signals. 2. A digital correlator for correlating a sampled sequence of a received signal with a spreading code and outputting a correlation pulse having a magnitude corresponding to the degree of correlation, an arithmetic circuit for calculating the correlator output, Generating a chip select address for each chip time of the time series data output from the arithmetic circuit in accordance with the set address value, and generating a data shift timing signal synchronized with the chip select address; A timing generation circuit that can change the address value to be set and data are input serially, and
Is generated by the timing generation circuit.
Parameter to be shifted by data shift timing signal
A plurality of shift registers capable of real output;
Responds to the chip select address generated by the
Circuit switching, and for each chip from the arithmetic circuit
The time series data divided into
, A plurality of adders for respectively calculating the sum of the parallel outputs of the respective stages of the respective shift registers, and an adder for giving the maximum value of the added correlation pulse from the output of each adder. A maximum value timing detection circuit for detecting the timing at which the maximum value of the added correlation pulse is detected, and a synchronization tracking device for the spread spectrum signal. 3. A synchronization tracking apparatus for a spread spectrum signal according to claim 1, wherein said means for sampling a correlation output corresponding to a timing giving a maximum value detected by a maximum value timing detection circuit; Control means for controlling the timing at which the maximum value detected by the detection circuit is given to be in the middle of one cycle of the code, and a synchronous tracking device for a spread spectrum signal.