JP3141870B2 - Identifier conversion method and identifier conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchro
Nous Transfer Mode) The present invention relates to conversion of cell routing information, and more particularly to a method and circuit for converting a virtual path identifier and a virtual channel identifier into an internal identifier used in an ATM communication device.

[0002]

2. Description of the Related Art An ATM is a fixed-length data block of 53 bytes (hereinafter referred to as a cell) composed of a 5-byte header for storing routing information and the like and a 48-byte payload (also referred to as an information field). ) Is used as a unit to transfer information within the network.

A plurality of virtual paths (Virtual Paths (hereinafter, referred to as VPs)) are provided between each node in the ATM network. Each VP has a virtual path identifier (Virtual Path identifier).
A number called an Identifier (hereinafter, referred to as VPI) is assigned, and each virtual path is identified by this VPI. Each VP has a plurality of virtual channels (Virtual
Channel (hereinafter, referred to as VC)). Each VC belonging to each VP is assigned a number called a virtual channel identifier (hereinafter, referred to as VCI), and each virtual channel is identified by this VCI.

[0004] The VPI and VCI are stored in a header section. User Network Int
erface (hereinafter referred to as UNI)), the VCI
Are assigned 16 bits, and the VPI is assigned 8 bits. Network / node interface (Networ
In the k Node Interface (hereinafter referred to as NNI), 16 bits are assigned to the VCI and 12 bits are assigned to the VPI.
Bits are assigned.

[0005] In the ATM transmission network, prior to information transfer,
An information transmission path (this is called a connection) in the network connecting the calling and called terminals is set. That is, a passing node is designated, and for each node, the incoming VP / VC and the corresponding outgoing VP / VC are determined. At the time of information transfer, each node identifies the incoming VP / VC from the VPI / VCI in the header of the received cell, and identifies the outgoing VP / VC according to a predetermined connection. The VPI / VCI is set in the header of the cell, and the cell is transmitted to the destination. Thus, information transfer is performed.

[0006] From the above-mentioned incoming VP / VC to outgoing VP / VC,
In principle, the correspondence for identifying the VC is based on the table storing the outgoing VPI / VCI being stored in the incoming VPI / VCI.
This is realized by indexing with / VCI.
Therefore, if placed any use condition for VPI / VCI, ^{2 24} pieces in UNI, it is necessary to prepare a large table with ^{2 28} entries in the NNI.

[0007] In actual operation, it is sufficient that about tens to tens of thousands of connections can be processed simultaneously. Therefore, in order to reduce the number of bits, the VPI in the header of the received cell is
/ VCI is converted to an internal VC used in the ATM communication device.

Conventionally, the number of bits M and V of the VPI used
The number N of bits of the CI is set as a parameter, and according to this setting, the lower M bits and the lower N bits from the VPI area and the VCI area of the received cell VPI / VCI are taken out and combined to determine the physical address of the conversion table. Generate, access the conversion table, and
Conversion from VCI to internal VC was performed.

In the case of the above method, the following two problems are raised. The first problem is the fixed range of VPI / VC
That is, only I can be received. For example, when M = 8 bits and N = 8 bits, the receivable VPI / V
CI ranges from VPI = 0 to FF (H) / VCI = 0.
000 to 00FF (H) (H in parentheses)
Indicates hexadecimal display. same as below. ). The second problem is that the values of the unselected areas are ignored,
That is, different VPI / VCIs are translated into the same address. For example, when M = 8 bits and N = 8 bits, VPI = 00 (H) / VCI = 0005 (H)
And VPI = 00 (H) / VCI = 0105 (H) are converted to the same internal VC.

As a method for solving such a problem, a VPI / VCI to be converted is converted into a CAM (Contents Addressable M
emory: associative memory), and by searching this CAM, the VPI / V of the received ATM cell is obtained.
The CI is converted to a physical address, and the RAM (Random Acces
s Memory) is disclosed in Japanese Patent Application Laid-Open No. Hei 9-17188.

As another conventional example, VPI / VCI
Japanese Patent Application Laid-Open No. 9-205435 discloses an identifier conversion device which performs conversion by addressing a first-stage table with the upper 18 bits of the address and addressing a next-stage table with the read block number and the lower 6 bits of the VPI / VCI. No. 6,086,045.

[0012]

SUMMARY OF THE INVENTION However, CAM
In a memory circuit that converts VPI / VCI using CAM, the VPI / VCI to be converted is stored in the CAM.
The size of the AM increases. This makes LSI (large-scale integrated circuit) design difficult. In addition, if the size of the CAM is large, a long time is required for searching, and high-speed conversion cannot be performed.

Further, in the identifier conversion system for converting between the first-stage table and the next-stage table, the stage table requires one word (16 bits) × 2 ¹⁸ things capacity, LS
I design is difficult.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an identifier conversion circuit and a method which can easily design an LSI and achieve high-speed conversion of an identifier.

[0015]

According to the present invention, there is provided an identifier conversion method which converts an identifier extracted from a header portion of a received data block into a corresponding identifier using a conversion table storing an internal identifier used in the communication device. A first step of dividing the identifier into an unconverted part and at least two converted parts,
A second step of converting the conversion part into address synthesis data corresponding to the conversion part and having a smaller number of bits than the conversion part; and a third step of generating a conversion table address from the non-conversion part and the address synthesis data. And a fourth step of reading the internal identifier from the conversion table according to the conversion table address.

Further, the identifier conversion circuit according to the present invention is a circuit for converting a first identifier extracted from a header portion of a received cell into a second identifier used inside the communication device,
Dividing means for dividing the first identifier into one non-conversion part and N (N is an integer of 2 or more ) conversion parts; and a bit number corresponding to each of the N conversion parts and being smaller than the corresponding conversion part. N to store searchable data for address synthesis with less
Address associative memories, address synthesizing means for generating a conversion table address from the address synthesizing data retrieved from the associative memory and the unconverted portion, and a conversion table address storing and storing all second identifiers used inside the communication device. And a conversion table for outputting a corresponding second identifier in accordance with

[0017] This is equivalent to decoding and checking all bits of the identifier information (VPI / VCI) in the received cell header, and all VPI / VCI values within the range of the number of associative memories that can be registered. On the other hand, reception becomes possible.

By dividing the reception VPI / VCI into a plurality of areas, the size of one CAM can be reduced, and the circuit design becomes easier. Furthermore, by reducing the size of the CAM required for conversion, the time required for search can be reduced, and high-speed conversion processing can be performed.

Further, by providing a plurality of division patterns so as to be selectable and selecting which part of the reception VPI / VCI is to be converted by the CAM, conversion can be performed for a wider range of reception VPI / VCI. It is possible to do.

Further, since the divided reception VPI / VCI into three or more regions are using multiple CAM, it is easy to register the required value of the VPI / VCI to the CAM in order to be grouped .

[0021]

FIG. 1 is a block diagram of an ATM communication device using one form of an identifier conversion circuit according to the present invention. The ATM network 1 includes a plurality of ATM switches, a plurality of ATM servers, a plurality of ATM terminals, and so on.
It is composed of a TM communication device.
The receiving system according to the present embodiment in the TM communication device 10 is illustrated. As is well known, in the transmission system of each ATM communication device, a transmission packet is decomposed into ATM cells, and the ATM cells are routing bits V embedded in a header.
The data is transferred within the ATM network 1 according to the PI / VCI. The receiving system of the ATM communication device converts the VPI / VCI of the received ATM cell into an internal identification number having a smaller number of bits. The conversion from the received VPI / VCI to the internal identification number will be described in detail below.

(First Embodiment) As shown in FIG.
The cell received by the M cell receiving unit 11 has a VPI /
The VPI / VCI is extracted by the VCI separation unit 12 and output to the division unit 13. Dividing section 13 receives VPI / V
The 28-bit information of the CI is divided into a predetermined upper bit string and a lower bit string (hereinafter referred to as “converted data” and “unconverted data”, respectively). Here, as an example, the upper 20 bits (hereinafter, referred to as VPI / VCI _U ) of the reception VPI / VCI are converted data, and the lower 8 bits.
Bit (hereinafter referred to as VCI _L.) The splitting as an untranslated data. Conversion data VPI / VCI _U in the search data memory 14, non-converted data VCI _L is output to the unconverted data memory 15.

The search data memory 14 stores the reception VPI / V
Conversion data VPI / VCI, which is the upper 20 bits of CI
_U is stored with 21-bit search data in which “1” is added as the most significant bit, and the search data is stored in an associative memory (C
AM) 16. The non-conversion data memory 15 stores the non-conversion data input from the division unit 13 and outputs the non-conversion data to the address synthesis unit 17 as it is.

The CAM 16 searches for registered data that matches the search data input from the search data memory 14. If there is matching registration data, the matching signal _SM is set (logical value “1”), and the address synthesizing unit 1
7 and the storage address of the registered data that matches (hereinafter referred to as “matching address ADDR _M ”) is also output to the address synthesizing unit 17. As will be described later, the coincidence address ADDR _M has a smaller number of bits (here, 8 bits) than the conversion data VPI / VCI _U which is the upper 20 bits of the reception VPI / VCI divided by the division unit 13.
Bit). If the registration data matching within CAM16 does not exist, the match signal S _M is not set, the coincidence signal S _M is the address synthesizing portion 17 of the logic value "0"
Output to

The address synthesizing unit 17, when the coincidence signal _{S M} is "1", matches the address A inputted from CAM16
Combining DDR _M on top of unconverted data VCI _L input from unconverted data memory 15, a synthesis address AD
Lookup table DR _C as the physical address 18
Output to When the coincidence signal _SM is “0”, the address synthesizing unit 17 does not generate the synthesized address ADDR _C. The lookup table 18 is an identifier conversion table, and the synthesized address A input from the address synthesis unit 17
The reception permission bit E and the VC number stored in the DDR _C (physical address) are output.

The CAM 16 is provided with a selector 20 and a cell array 21. The selector 20 selects one of the search data and the registered data according to the write / search mode switching signal, and outputs the selected data to the cell array 21. The cell array 21 is a part of the reception VPI / VCI (here, the upper two
In the registration mode, data in which a valid bit V (= "1" or "0") is added as the most significant bit to 0-bit data VPI / VCI _U is stored. By setting the valid bit V to "1", the input data can be written as registered data. Conversely, by setting the valid bit V to "0", no registration can be performed. Furthermore, CAM1
The 6, an address decoder 22 for addressing the cell array 21, the coincidence signal S _M and the matching address ADDR _M If the registration data matching the search data is present
Is provided. In the search mode, the selector 20 selects search data, and registered data matching the search data is searched. If it finds a matching registration data matching address ADDR _M and the coincidence signal _{S M} is outputted to the address synthesizing portion 17 by the encoder 23. Matching address ADDR _M, since may specify the address of each register of the cell array 21, in the case of 2 ^eight cell arrays may be 8-bit address. In other words, the 20-bit data VPI /
This means that VCI _U has been converted to an 8-bit match address ADDR _M.

In the look-up table 18, a reception permission bit E for determining whether or not to accept the reception cell into the apparatus is registered together with the VC number. As described above, the combined address ADDR _C generated based on the VPI / VCI of the received cell is output to the lookup table 18 as a physical address through the selector 24, and the reception permission bit E accessed by the combined address ADDR _C is output. If "1", the reception of the received cell is permitted. Conversely, if the reception permission bit E encounters "0", the cell is discarded. VC numbers are prepared for the number of connections to be processed in the apparatus (for example, 2 ¹⁶ ) and stored in the lookup table 18 in advance.
For example, read ^{2 16} VC numbers respectively, synthetic address ADDR _C is 16 bits.

FIG. 2 is a flowchart showing a processing flow of the identifier conversion method in the first embodiment shown in FIG. The reception VPI / VCI 201 has 28 bits (the upper 12 bits of the VPI and the lower 16 bits of the VCI) in the NNI and 24 bits (the upper 8 bits of the VPI and the lower 16 bits of the VCI) in the UNI. Receive VPI /
The VCI 201 is divided into a predetermined upper bit string and a lower bit string, and output to the search data memory 14 and the non-conversion data memory 15 as conversion data VPI / VCI _U and non-conversion data VCI _L , respectively.

The search data memory 14 stores search data 202 obtained by adding “1” as the most significant bit to the conversion data VPI / VCI _U , which is a high-order bit string, and outputs the search data 202 to the CAM 16. CAM16 is
A search is made for registered data that matches the search data 202. If there is registered data that matches, the match signal _SM is set, and a match address ADDR _M , which is the storage address of the matched registered data, is set in the address combining unit 17. What
BR> Output. As already mentioned, the match address ADD
R _M, since having a high-order bit string and a converted data VPI / VCI _U fewer number of bits of the received VPI / VCI (8 bits in this case) is coupled to the upper unconverted data VCI _L in the address synthesizing unit 17 generates The synthesized address ADDR _C thus obtained is an address shorter than the bit length of the reception VPI / VCI. This short composite address AD
Look-up table accessed by DR _C 1
8 outputs the internal VC number.

The specific size of the CAM 16 can be determined as follows. For example, if VPI / VCI is 28
Bits (VPI is in the upper 12 bits and VCI is in the lower 16
Bits are placed. ) In the NNI
(Corresponding to 2 ^16.) 00 pieces when processing the connection, as described above, the lookup table 1
The physical address given to 8 (that is, the composite address ADDR _C ) has 16 bits. In this case, the received VP
Dividing the I / VCI to the upper 20 bits and lower 8 bits, in order to generate an address lookup table 18, CA with a capacity of (1 + 20) bits × ^{2 8}
M16 may be prepared. This is a realistic circuit scale.

As described above, the received VPI / VCI is divided into a non-conversion part and a conversion part, and the conversion part is converted into a matching address having a smaller number of bits by using CAM. Are combined to generate the address of the lookup table. As a result, all bits of the VPI / VCI of the received cell header can be decoded and converted to an internal identification number by a look-up table. Therefore, reception is possible for all VPI / VCI values within the range of numbers effectively registered in the cell array 21 of the CAM 16. In addition, since the CAM 16 is searched using only the conversion part, the size of the CAM 16 can be designed to be small, and the time required for the search can be reduced to perform high-speed conversion processing.

(Second Embodiment) FIG. 3 is a block diagram showing a second embodiment related to the present invention, and FIG. 4 is an explanatory diagram showing an example of a division mode changing operation in the second embodiment. In the second embodiment, FIG.
As shown in the figure, the dividing unit 30 for dividing the bit string of the reception VPI / VCI into two parts is different from the first embodiment. The dividing unit 30 includes a first dividing unit 301 corresponding to the division mode 1,
A second division unit 302 corresponding to division mode 2 different from division mode 1 and selectors 303 and 304 for selecting their output data and outputting converted data and non-converted data are provided.

The first division unit 301 divides the bit string of the received VPI / VCI into first converted data and first non-converted data, and outputs them to selectors 303 and 304, respectively. The second dividing unit 302 divides the same received VPI / VCI bit string into second converted data and second non-converted data, and outputs them to the selectors 303 and 304, respectively. Selector 30
Reference numerals 3 and 304 select one of the converted data and the non-converted data according to the division mode switching signal and output the selected data to the search data memory 14 and the non-converted data memory 15.

More specifically, as shown in FIG.
Dividing section 301 divides the bit string of reception VPI / VCI 201 into first converted data VPI / VCI _U of an upper bit string and first non-converted data VCI _L of a lower bit string, and
Conversely, division section 302 divides the bit string of received VPI / VCI 201 into second converted data VCI of a lower bit string and second non-converted data VPI of an upper bit string.

When the division mode switching signal is division mode 1, the selector 303 sets the first conversion data VPI / VCI
Select _U output to the search data memory 14, the selector 304 outputs to the unconverted data memory 15 to select the first non-conversion data VCI _L. This division mode 1 is the first
This is the same as the embodiment. When the division mode switching signal is the division mode 2, the selector 303 outputs the second conversion data VC
I is selected and output to the search data memory 14, and the selector 304 selects the second non-conversion data VPI and outputs it to the non-conversion data memory 15. It is easy to set N division modes (N is an integer of 3 or more). In other words, it is only necessary to provide a division unit corresponding to each of the N division modes, and select the conversion and non-conversion data from each division unit by the selector.

As described above, the division range of the reception VPI / VCI 201 can be switched by switching the division mode, and it is possible to select a range of bit strings to be used as search data depending on the reception mode. At this time, registration data corresponding to the selected search data is registered in the CAM 16 in advance. For example, when simultaneous reception is performed for the entire range of the VCI, all the upper bit strings of the VCI are registered in the CAM 16 and the CAM 16 is registered.
16 matches the address ADDR _M and synthetic address ADD a combination of the lower bit string VCI _L as unconverted data
_RC is generated. Conversely, when performing reception based on VPI, the bit string in the entire range of VPI is
Is registered in advance, and VPI is set to
Simultaneous reception can be performed for the entire range of the PI.

Third Embodiment FIG. 5 is a block diagram schematically showing a configuration of an example ( third embodiment ) of an identifier conversion circuit according to the present invention.
In the third embodiment, the bit string of the reception VPI / VCI is reduced.
It is divided into a plurality of ranges of at least two converted parts and a non-converted part . To exemplify the case of dividing into three, the dividing unit 40 divides the reception VPI / VCI 201 into first converted data which is an upper bit string, second converted data which is an intermediate bit string, and non-converted data which is a lower bit string. 401, 402 and non-conversion data memory 403
Output to

The search data memory 401 stores search data S1 in which “1” is added as the most significant bit to the first conversion data, which is a high-order bit string, and outputs the search data S1 to the CAM 404. Similarly, the search data memory 4
02 stores search data S2 obtained by adding “1” as the most significant bit to the second converted data that is an intermediate bit string;
The search data S2 is output to the CAM 405.

The CAM 404 is the CAM 1 of the first embodiment.
As in the case of No. 6, a search is made for registered data that matches the input search data S1, and if there is a registered data that matches, a match signal _SM1 is set and a match address that is the storage address of the matched registered data is set. ADDR _M1
Is output to the address combining unit 406. Similarly, CAM4
05 searches for registered data that matches the input search data S2, and if there is matching registered data,
The matching signal S _M2 is set, and the matching address ADDR _M2 , which is the storage address of the matching registered data, is output to the address combining unit 406.

The address synthesizing unit 406 outputs the coincidence signal S _M1
And only if both _{S M2} is set to generate a composite address ADDR _C. That is, the match address ADDR _M1 , the match address ADDR _M2 ,
And the unconverted data in this order to generate a combined address ADDR _C which is the physical address of the lookup table 18. If one of the coincidence signals S _M1 and S _M2 is not set, no composite address is generated.

As an example, the UNI (and thus the receive VPI
The data length of / VCI is 24 bits. )
A case of processing 2 ¹⁶ (= 65536) connections will be described. The dividing unit 40 divides, for example, the 24-bit received VPI / VCI from the 0th to 7th bit unconverted data, the 8th to 15th bit second converted data, and
It is assumed that the data is divided into three pieces of 23-bit first conversion data.
In this case, the CAM 404 has one word (= 9 bits) ×
Has a capacity of 2 ^4, each word contains all VPI value received in the lower 8 bits, the registration flag is set to the most significant bit. Similarly, the CAM 405 has one word (= 9
It has a capacity of bits) × 2 ^4, each word stores the higher 8 bits of the VCI to receive the lower 8 bits, the registration flag is set to the most significant bit. CAM 404 and 405
Are the same as those described above, and a description thereof will be omitted.

As described above, the reception VPI / VCI is reduced.
By dividing into at least two areas of the converted part and the non-converted part, converting some of the areas using CAM, using the remaining areas as they are, and combining these values, Generate an address of a conversion table (lookup table). By adopting such a configuration, the size of one CAM is smaller than that of the first embodiment (the size of CAM 404 and CAM 405 is 1 word (= 9 bits) × 24). LS
I design becomes easy. Further, since the size of the CAM required for the conversion is reduced, the time required for the search can be reduced, and high-speed conversion processing can be performed.

Further, since grouping can be performed, registration of the received VPI / VCI becomes easy. For example, "VP
"AA (8 bits) / VCI upper (8 bits)"
(H) / AA (H) "," AA (H) / BB (H) ",
“AA (H) / CC (H)”, “BB (H) / AA
(H) "," BB (H) / BB (H) "," BB (H)
/ CC (H) "is registered in the CAM, and when there is one CAM, all of them need to be registered.
When there are two, "AA (H)", "B
B (H) "and" AA (H) "," B
B (H) "and" CC (H) ".

The identifier conversion methods according to the first to third embodiments can be realized by hardware, but can also be realized by software using a program-controlled processing device such as a microprocessor.

[0045]

As described above, according to the present invention,
Divide the received identifier information into multiple areas, convert some of the areas to data with fewer bits using associative memory, and use the same values for the remaining areas, and combine these values Thus, the address of the conversion table is generated. This allows the VP in the received cell header to be
This is equivalent to decoding and checking all bits of the I / VCI, and reception is possible for all VPI / VCI values within the range of the number of CAMs that can be registered.

By dividing the reception VPI / VCI into a plurality of areas, the size of one CAM can be reduced, and circuit design can be facilitated. Furthermore, by reducing the size of the CAM required for conversion, the time required for search can be reduced, and high-speed conversion processing can be performed.

Further, which part of the reception VPI / VCI is
By making it possible to select whether to convert by AM,
Conversion can be performed for a wider range of reception VPI / VCI.

Further, since the received VPI / VCI is divided into three or more areas and a plurality of CAMs are used , grouping can be performed, so that it becomes easy to register necessary values of VPI / VCI in the CAM. .

[Brief description of the drawings]

1 is a block diagram of an ATM communication apparatus using the first embodiment of the identifier conversion circuit according to the present invention.

FIG. 2 is a flowchart showing a processing flow of an identifier conversion method in the first embodiment shown in FIG.

3 is a block diagram showing a second embodiment according to the present invention.

FIG. 4 is an explanatory diagram illustrating an example of a division mode change operation in a second embodiment.

FIG. 5 is a block diagram schematically showing a configuration of a ( third ) embodiment according to the present invention.

[Explanation of symbols]

 Reference Signs List 1 ATM network 10 ATM communication device 11 ATM cell receiving unit 12 VPI / VCI separation unit 13 Division unit 14 Search data memory 15 Non-conversion data memory 16 CAM 17 Address synthesis unit 18 Lookup table 20 Selector 21 Cell array 22 Address decoder 23 Encoder 24 Selector 201 Received VPI / VCI 202 Search data 203 Non-conversion data 204 Synthetic address 301 First division unit 302 Second division unit 303 Selector 304 Selector 401 Search data memory 402 Search data memory 403 Non-conversion data memory 404 CAM 405 CAM 406 Address synthesis Department

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/28 H04L 12/56

Claims (10)

(57) [Claims] 1. A method for converting an identifier extracted from a header part of a received data block into an internal identifier corresponding to the identifier by using a conversion table storing an internal identifier used inside the communication device, wherein: A first step of dividing the data into an unconverted part and at least two converted parts; and a second step of converting the converted part into address synthesis data corresponding to the converted part and having a smaller number of bits than the converted part. A third step of generating a conversion table address from the unconverted portion and the data for address synthesis, and a fourth step of reading the internal identifier from the conversion table according to the conversion table address. Identifier conversion method. 2. The first step includes: preparing a plurality of division patterns for dividing the identifier into a non-conversion part and at least two conversion parts, and selecting one division pattern from the plurality of division patterns 2. The method according to claim 1, further comprising: dividing the identifier. 3. In the second step, a memory is prepared for retrievably storing all registered data corresponding to the converted part, and the registered data matching the converted part is stored by searching the memory. 3. The method according to claim 1, further comprising: generating the address combining data from an address. 4. The method according to claim 3, wherein said memory is an associative memory. 5. The step of generating the conversion table address by arranging a bit string of the address synthesizing data and a bit string of the non-conversion part such that one is located on the upper side of the other. The identifier conversion method according to any one of claims 1 to 4, wherein: 6. A circuit for converting a first identifier extracted from a header part of a received cell into a second identifier used inside a communication device, wherein the first identifier is converted into one unconverted part and N (N is 2 storing more <br/> dividing means for dividing into a transformation portion integer) of the fewer address synthesis data number of bits than the conversion portion N corresponding to each of the pieces of converted portions and the corresponding searchable N address associative memories, address synthesizing means for generating a conversion table address from the address synthesizing data searched in the associative memory and the non-converted portion, and all second identifiers used inside the communication device. A conversion table for storing and outputting a corresponding second identifier according to the conversion table address. 7. The identifier conversion circuit according to claim 6, wherein said dividing means has a selecting means for selecting one divided pattern from a plurality of predetermined divided patterns. 8. The associative memory inputs a corresponding conversion part as search data and outputs an address at which registered data matching the conversion part is stored as the address synthesizing data. Item 6 or 7
The described identifier conversion circuit. 9. The conversion table address is generated by arranging the bit string of the address synthesizing data and the bit string of the non-conversion part such that one is located on the upper side of the other. 9. The identifier conversion circuit according to claim 6, wherein: 10. A program for converting, by a computer, an identifier extracted from a header part of a received data block into an internal identifier corresponding to the identifier, using a conversion table storing an internal identifier used inside the communication device. A first step of dividing the identifier into an unconverted part and at least two converted parts; an address corresponding to the converted part and having a smaller number of bits than the converted part. A second step of converting to the data for synthesis, a third step of generating a conversion table address from the non-conversion portion and the data for address synthesis, and a fourth step of reading the internal identifier from the conversion table according to the conversion table address Record steps and programs to run on a computer The recording medium.