JP3140865B2 - Clock recovery circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal receiving apparatus for receiving, for example, a digital data signal and reproducing the original digital data. In particular, by incorporating the digital signal into this signal receiving apparatus, it is possible to reproduce a plurality of types of clocks. And a clock recovery circuit.

[0002]

2. Description of the Related Art For example, when transmitting digital data,
This digital data is converted into a binary code sequence,
In many cases, the coded code string is converted into an NRZ signal and transmitted in consideration of the economical rate and the rate of occurrence of transmission errors. The transmission rate of this digital data signal, that is, the bit transmission rate (bit transfer rate) V is determined by the CCITT (International Telegraph and Telephone Consultative Committee) according to IS.
For DN, SDH (Synchronous Digital Hierarchy)
Defined as interface speed.

For example, in STM-0, the bit transmission speed V is 51.84 Mb / s, and in STM-1, V = 155.
52 Mb / s, V = 622.080 Mb / s for STM-4, STM
For -16, V = 2488.32 Mb / s, for STM-64, V =
9.95328 Gb / s.

Therefore, a digital data signal having any one of the bit transmission speeds V described above is transmitted through a transmission path such as an optical fiber cable connecting the stations.

In a signal receiving apparatus for receiving a digital data signal transmitted through a transmission line, a clock signal indicating a break of each bit data is received in order to accurately reproduce digital data included in the digital data signal. It must be reproduced from a digital data signal.

FIG. 10 is a block diagram showing a general clock signal reproducing circuit. For example, an NRZ-encoded digital data signal a input to the input terminal 1 is NRZ / R
In the Z conversion circuit 2, the signal is converted into an RZ signal b. RZ
The signal b is input to the next band pass filter 3. The pass center frequency f ₀ of the band pass filter 3 is set to a frequency f _C corresponding to the bit transmission speed V of the digital data signal a applied to the input terminal 1. Thus, the band-pass filter 3 passes only the frequency f ₀ frequency component near of the RZ signal b. Sine wave signal c of frequency f ₀ (= f _C ) output from band pass filter 3
Are input to the waveform shaping circuit 4. The waveform shaping circuit 4 shapes the input sine wave signal c into a rectangular wave, for example, and outputs it from the output terminal 5 as a reproduced clock signal d.

The NRZ / RZ conversion circuit 2 is a circuit for extracting the frequency f _C corresponding to the bit transmission rate V from the NRZ signal. If the input digital data signal a is an RZ signal from the beginning, the NRZ / RZ conversion circuit 2 outputs this signal. The NRZ / RZ conversion circuit 2 is unnecessary.

[0008]

However, FIG.
The clock recovery circuit shown in (1) has the following problems to be solved.

[0009] As described above, since the central pass frequency f _C of the band-pass filter 3 is a fixed value, the digital data signal a having a bit rate V corresponding naturally frequencies that match the central pass frequency f _C Only this clock recovery circuit can perform clock recovery.

On the other hand, in the above-mentioned transmission path between stations in the ISDN, a digital data signal to be transmitted is transmitted depending on regions such as Japan, North America and Europe, and depending on the density of transmission information between the stations. The bit transmission speed V is different.

Therefore, for example, in order for one signal receiving apparatus to receive a plurality of types of digital data signals a having different bit transmission speeds V, a band-pass filter whose passing center frequency f ₀ corresponds to each bit transmission speed V is required. It is necessary to previously incorporate a plurality of clock recovery circuits into which a signal has been incorporated in the signal receiving device. As a result, not only the configuration of the signal receiving device becomes complicated, but also the manufacturing cost increases.

Furthermore, when a transmission line is newly laid between stations or a new transmitter is installed, it is necessary to test the signal quality of a digital data signal transmitted on the transmission line. . In this case, the bit transmission speed V of the digital data signal to be transmitted may be slightly different from the specified bit transmission speed V described above. Even in such a case, it is necessary to reproduce the clock signal in order to reproduce the digital data from the received digital data signal.

However, as shown in FIG. 10, when the pass center frequency f ₀ of the band-pass filter 3 is fixed, when the bit transmission speed V of the received digital data signal fluctuates, an accurate clock signal is output. A problem that cannot be reproduced occurs.

[0014]

The present invention has been made in view of such circumstances.
And a clock recovery circuit that can recover clock signals of a plurality of types of digital data signals having different bit transmission speeds by using a single band-pass filter having a fixed pass center frequency by adding a simple frequency divider. The purpose is to provide.

[0016]

[0017]

[Means for Solving the Problems] In order to solve the above problems
According to the present invention, a plurality of types of digital data signals having bit transmission speeds that are integral multiples of each other are alternatively input, and a clock recovery circuit that recovers a clock signal from the input digital data signal is input. A digital data signal is applied, a pass center frequency is set to a maximum frequency corresponding to a maximum bit transmission rate of each digital data signal, and an output frequency of an output signal output from the band pass filter. Frequency divider that divides the clock and outputs it as a clock signal, and a frequency division ratio that sets the frequency division ratio of the frequency divider to the ratio of the bit transmission speed of the externally specified input digital data signal to the maximum bit transmission speed And a setting device.

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

The principle of operation of the clock recovery circuit thus constructed will be described.

[0024] Generally, Teshitarudeta signal to another frequency component of the frequency f _C, corresponding to the bit rate V, 2 times the frequency f _C, 3, 4, 5, ..., an integral multiple of the frequency of an equal (N · f _C ) frequency components.

Therefore, even if the pass center frequency f ₀ of the band-pass filter does not coincide with the frequency f _C corresponding to the bit transmission speed V of the input digital data signal, the center frequency f ₀ is equal to a frequency that is an integral multiple of the frequency f _C. If so, a frequency component that is an integral multiple of that is output from the bandpass filter. Therefore, a clock signal having a frequency f _C corresponding to the bit transmission speed V can be obtained by dividing the frequency of the output signal by the integral multiple.

In the present invention, the pass center frequency f ₀ of the band-pass filter is set to the maximum frequency corresponding to the maximum bit transmission rate of the input digital data signal. Then, by setting the frequency division ratio of the frequency divider to the ratio of the bit transmission speed of the digital data signal to be inputted this time to the maximum bit transmission speed, a plurality of digital transmission signals having different bit transmission speeds by one clock recovery circuit. The clock signal of the data signal can be reproduced.

[0027]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a filter device according to an embodiment. The digital data signal a1 applied to the input terminal 11 is input to the signal conversion circuit 12.
The signal conversion circuit 12, for example, as shown in FIG.
It is composed of a delay circuit 12a and an exclusive OR gate 12b. The exclusive OR gate 12b outputs an exclusive OR signal of the input digital data signal a1 and the digital data signal a1 delayed for a short time. Therefore, for example, when the input digital data signal a1 is an NRZ signal as shown in FIG. 2 (b), the output signal is a digital data signal b1 containing a large number of frequency f _C components corresponding to the bit transmission rate V such as an RZ signal. Become.

The frequency f output from the signal conversion circuit 12
_The digital data signal b1 containing a large amount of the _C component is input to the next bandpass filter 13. The bandpass filter 13 is formed of, for example, YIG Tuned filter, as shown in FIG. 3, varies substantially in proportion to the applied voltage E _G that passes through center frequency f ₀ is applied to the control terminal G. Therefore, the output signal c1 outputted from the band pass filter 13 is a sine wave signal having a single frequency of the pass center frequency f _0.

The output signal c 1 output from the band pass filter 13 is input to the next waveform shaping circuit 14. The waveform shaping circuit 14 outputs the output signal c having a sine waveform.
1 is shaped into a rectangular wave and output from the output terminal 15 as a reproduced clock signal d1.

The output signal c 1 output from the band-pass filter 13 is also input to the power detection circuit 16. The power detection circuit 16 includes, as shown in FIG.
6a and a capacitor 16b, which detects the power value of the input output signal c1 and outputs a detection signal e having a signal level corresponding to the power value to a gain adjusting buffer 1.
The signal is sent to the next feedback control circuit 17 via 6c.

The DC bias voltage Eb output from the feedback control circuit 17 is applied to the adder 18. Adder 18
Is composed of an input resistor 18a, a buffer amplifier 18b, and a feedback resistor 18c, as shown in FIG. A DC set voltage Es is applied to the adder 18 from a setter 19 in addition to the DC bias voltage Eb. A plurality of set voltages Es corresponding to the bit transmission speed V determined by the type of the digital data signal a1 input to the input terminal 11 are prepared in the setter 19. When the operator specifies the type of the digital data signal a1, the set voltage Es corresponding to this type is output from the setting unit 19.

Further, the oscillator 20 applies a rectangular wave signal g having a constant frequency f _S and a constant amplitude As to the adder 18. The rectangular wave signal g input to the adder 18 is
After the signal level is adjusted at d, the signal level is applied to the buffer amplifier 18b via the DC blocking capacitor 18e. Accordingly, the adder 18 applies a DC bias voltage Eb applied, to the control terminal G of the bandpass filter 13 as the control voltage E _G by adding the predetermined voltage Es and the rectangular wave signal g.

The feedback control circuit 17, as shown in FIG.
It comprises a phase detection circuit 21, a low-pass filter 22, and a differential amplifier 23.

As shown in the figure, the phase detection circuit 21 includes an analog switch 21a that performs switching operation at the frequency f _S of the rectangular wave signal g output from the oscillator 20, an input resistor 21b,
21c, a ground resistor 21d, a buffer amplifier 21e, and a feedback resistor 21f. The detection signal e input from the power detector 16 is alternately sampled by the analog switch 21a at the frequency f _S of the rectangular wave signal g and input to the (−) side terminal and the (+) side terminal of the buffer amplifier 21e, respectively. .

Accordingly, the portion of the detection signal e corresponding to the H (high) level period of the rectangular wave signal g is input to the (−) side terminal of the buffer amplifier 21e, and the L (low) of the square wave signal g in the detection signal e is detected. ) The part corresponding to the level period is input to the (+) side terminal of the buffer amplifier 21e. As a result, the output signal h of the phase detection circuit 21 becomes
As shown in the time chart of FIG. 6, the signal value of the square wave signal g in the H level period of the detection signal e is determined to be a (-) value Ee-, and the L level period of the square wave signal g in the detection signal e. Becomes the (+) value Ee + as it is.

The output signal h of the phase detection circuit 21 is input to the next low-pass filter 22. Low-pass filter 22
Are a resistor 22a, a capacitor 22b, and a buffer amplifier 2
2c, and smoothes the input output signal h and converts it to a signal i close to DC as shown in FIG.

The output signal i of the low-pass filter 22 is input to the next differential amplifier 23. This differential amplifier 23
It comprises an input resistor 23a, a differential amplifier 23b, and a feedback resistor 23c. The output signal i is applied to the (−) terminal of the differential amplifier 23b, and the reference voltage Vc is applied to the (+) terminal. Therefore, as shown in FIG. 6, the DC bias voltage E having a shape corresponding to the difference voltage between the output signal i and the reference voltage Vc is output from the differential amplifier 23.
b is output. This DC bias voltage Eb is sent to the adder 18 described above.

Next, the operation of the filter device thus configured will be described with reference to FIGS.

First, the operator sets the type of the input digital data signal a1 in the setting unit 19. Then, the setting voltage Es corresponding to the bit transmission speed V of the input digital data signal a1, that is, the frequency f _C of the digital data signal a1, is input from the setting device 19 to the adder 18. Since the adder 18 square wave signal g from the oscillator 20 is applied to the control terminal G of the bandpass filter 13, control voltage E _G rectangular wave signal g is superimposed on the DC set voltage Es is applied Is done.

Accordingly, the pass center frequency f ₀ of the band-pass filter 13 is a frequency near the frequency f _C of the digital data signal a 1 as shown in the left waveform of FIG. The passing center frequency f ₀ oscillates in a frequency range of ± Δf determined by the amplitude value of the rectangular wave signal g.

If the passing center frequency f ₀ at that time is located halfway on the left side of the above-mentioned chevron waveform, the signal level of the output signal c 1 of the band-pass filter 13 becomes equal to the detection signal e of the power detector 16. , The lower end frequency f ₀ −Δ corresponding to the L level period of the rectangular wave signal g
The voltage value Ee + at the time f and the voltage value Ee- at the upper end frequency f ₀ + Δf corresponding to the H level period of the rectangular wave signal g appear alternately. In this case, the voltage value E at the upper end frequency f ₀ + Δf
e− becomes higher than the voltage value Ee + at the lower end frequency f ₀ −Δf.

Accordingly, the output signal i of the low-pass filter 22 has a (-) value, and the differential amplifier 23 outputs a (+)-value DC bias voltage Eb. As a result, the increase in the control voltage E _G applied from the adder 18 to the control terminal G of the bandpass filter 13, a band-pass filter 1
The central pass frequency f ₀ of 3 is moved to the peak direction of the chevron waveforms in FIG.

When the passing center frequency f ₀ moves in the peak direction, the difference between the voltage value Ee + at the lower end frequency f ₀ −Δf and the voltage value Ee− at the upper end frequency f ₀ + Δf becomes smaller. Therefore, the signal level of the output signal i of the low-pass filter 22 approaches 0. Then, the rising rate of the DC bias voltage Eb decreases.

The DC bias voltage Eb further rises,
When the passing center frequency f ₀ coincides with the peak position of the chevron waveform, that is, the frequency f _C of the digital data signal a 1,
Since e + = Ee-, and the output signal i of the low-pass filter 22 is at the 0 level, the DC bias voltage Eb has a constant value.

Therefore, the pass center frequency f ₀ of the band-pass filter 13 is equal to the input digital data signal a 1
Automatic tracking to the frequency f _C of

Next, when the type of the input digital data signal a1 is changed, the changed signal type is set in the setting unit 19. Then, the set voltage Es corresponding to the changed bit transmission speed V is output. As a result, the case where the pass center frequency f ₀ of the band-pass filter 13 is located at a middle position on the right side of the chevron waveform as shown on the right side of FIG. The voltage value Ee− at the upper end frequency f ₀ + Δf becomes lower than the voltage value Ee + at the lower end frequency f ₀ −Δf. As a result, the output signal i of the low-pass filter 22 has a (+) value. Thus, the DC bias voltage Eb output from the differential amplifier 23 (-) value becomes, the central pass frequency f ₀ is moved to the left of the peak position. The passing center frequency f ₀ is the peak position of the chevron waveform, that is, the digital data signal a
When the frequency matches the frequency f _C of 1, the DC bias voltage Eb becomes a constant value.

[0048] Thus, the operator if specified in the setting device 19 the type of the input digital data signal a1, automatically tracks the frequency f _C of the digital data signal a1 central pass frequency f ₀ is input to the band-pass filter 13 .

Therefore, the clock signal d1 of a plurality of types of digital data signals a1 having different bit transmission speeds V
Can be played automatically.

In the filter device having such a configuration, even if the bit transmission speed V of the input digital data signal a1 slightly deviates from the bit transmission speed defined in the above-mentioned CCITT standard, a clock signal having a deviated frequency is used. Can be accurately reproduced. Therefore, the bit transmission speed V
Even if the value fluctuates slightly, the signal receiving device incorporating the filter device can always reproduce correct digital data.

FIG. 7 is a block diagram showing a schematic configuration of a clock recovery circuit according to another embodiment of the present invention.

The digital data signal a 2 having the bit transmission speed V input to the input terminal 31 is
Is converted into a digital data signal b2 containing a large number of frequency components of the frequency f _C corresponding to the bit transmission speed V, and is input to the band-pass filter 33. Band-pass filter 33 passes the frequency components of the central pass frequency f ₀ of the digital data signal b2 inputted.

The output signal c 2 having a sine waveform of frequency f ₀ output from the band-pass filter 33 is input to the waveform shaping circuit 34. The waveform shaping circuit 34 shapes the waveform of the input output signal c2 into, for example, a rectangular wave. The output signal j having the frequency f ₀ of the waveform shaping circuit 34 is output to the next frequency divider 3
5 is divided into 1 / N, is output from the output terminal 36 as a reproduced clock signal d2 having a frequency (f ₀ / N). The frequency division ratio N of the frequency divider 35 is set by a frequency division ratio setting device 37.

It is possible to input a plurality of kinds of digital data signals a2 whose bit transmission speeds V are integral multiples of each other to this clock recovery circuit. That is, as described above, the bit transmission rate V adopted in the ISDN is the bit transmission rate V = STM-0.
Assuming that 51.84 Mb / s is the reference bit transmission speed V0, ST
V = 3 × V0 for M-1, V = 12 × V for STM-4
0, STM-16, V = 43 × V0, and STM-64, V = 192 × V0.

Therefore, in the case where the above-mentioned five types of digital data signals a2 are received by the signal receiving device incorporating this clock recovery circuit, the maximum bit transmission speed V = 192 × V0 = 9.95328 Gb / s. set in the corresponding passes frequencies that match the frequency fC (maximum frequency) of the center frequency _{f 0 (= f C = 9.95328} GHz) band-pass filter 33 as.

When applying the STM-64 digital data signal a2, the operator sets N =
A division ratio of 1 is set. In STM-16, N = 4
, And N = 16 in STM-4, and STM-
In the case of 1, N = 64, and in the STM-0, N = 192.

[0057] As described above, the digital data signal a2 of the frequency f _C, as shown in FIG. 8, the signal level is reduced includes a number of harmonic components of an integral multiple of the frequency f _C.

Therefore, the frequency f _C corresponding to the pass center frequency signal f ₀ set in the band-pass filter 33 is used.
Even if the digital data signal a2 does not have the frequency (N · f _C ), the frequency (N · f _C ) that is an integral multiple of the frequency f _C always matches the pass center frequency signal f ₀ , f _C ) is obtained. This output signal j is frequency-divided by the frequency divider 35 to (1 / N), so that the input digital data signal a
The second clock signal d2 is reproduced.

FIG. 9 is a waveform diagram showing the relationship between the input digital data signal a 2 and the output signal j of the band-pass filter 33. 9 (a) is an input digital data signal a2 waveform of STM-4, FIG. 9 (b) is the output signal j of 16 times the harmonics in the corresponding signal (16 × f _C). Further, FIG. 9 (c) is the input digital data signal a2 waveform of STM-1, FIG. 9 (d) is a 64-fold harmonic (64 × f _C) output signal j at the appropriate signal.

Therefore, the output signal j shown in FIG.
Is higher than the signal level of the output signal j shown in FIG. This signal level difference is adjusted to the same signal level by a level adjustment circuit in a subsequent stage (not shown).

With the clock recovery circuit configured as described above, even if the pass center frequency f ₀ of the bandpass filter 33 is fixed, a plurality of types of bit transmission speeds V having an integer multiple of each other are available. The clock signal d2 of the digital data signal a2 can be reproduced.

[0062]

[0063]

As described above , according to the clock recovery circuit of the present invention, a frequency divider having a simple structure is inserted in the output stage of the band-pass filter. Therefore, a single band-pass filter having a fixed center frequency can reproduce clock signals of a plurality of types of digital data signals having different bit transmission speeds.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a filter device according to an embodiment of the present invention;

FIG. 2 is a signal conversion circuit diagram and a signal waveform diagram of the device of the embodiment;

FIG. 3 is a characteristic diagram showing a relationship between a pass center frequency of a band-pass filter and a control voltage;

FIG. 4 is a waveform chart for explaining the operation of the apparatus of the embodiment;

FIG. 5 is a detailed circuit diagram of the device of the embodiment,

FIG. 6 is a time chart showing the operation of the apparatus of the embodiment;

FIG. 7 is a block diagram showing a schematic configuration of a clock recovery circuit according to another embodiment of the present invention;

FIG. 8 is a frequency characteristic diagram showing a relationship between a frequency of an input signal and a harmonic;

FIG. 9 is a waveform chart showing the operation of the clock recovery circuit according to the embodiment;

FIG. 10 is a block diagram showing a schematic configuration of a conventional clock recovery circuit.

[Explanation of symbols]

12, 32: signal conversion circuit, 13, 33: band-pass filter, 14, 35: waveform shaping circuit, 16: power detector, 17: feedback control circuit, 18: adder, 19: setting device, 20: oscillator, 21: phase detection circuit, 22: low-pass filter, 23: differential amplifier, 35: frequency divider, 37:
Division ratio setting device.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 7/027

Claims (1)

(57) [Claims] 1. A clock recovery circuit for selectively receiving a plurality of types of digital data signals having bit transmission speeds that are integral multiples of each other, and recovering a clock signal from the input digital data signal. Digital data signal is applied, a pass center frequency is set to a maximum frequency corresponding to the maximum bit transmission rate of the digital data signals, a band-pass filter (33), and an output output from the band-pass filter. A frequency divider (35) that divides the output frequency of the signal and outputs it as a clock signal; and a division ratio of the frequency divider, the maximum bit of the bit transmission rate of the input digital data signal specified from outside. A clock recovery circuit comprising a frequency division ratio setting device (37) for setting a ratio to a transmission speed.