JP3139995B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a step on a semiconductor substrate, and more particularly to a method for manufacturing a stacked type DRAM.

[0002]

2. Description of the Related Art As is well known, MOS (Metal O)
The gate insulating film of the x-type semiconductor (LSI) transistor is an LSI (Large Scale).
2. Description of the Related Art With the miniaturization of integrated circuits, thinning of devices has been promoted.

[0005] In a conventional MOS transistor, a gate electrode material (conductive layer) is deposited on a gate insulating film, and the electrode material is patterned to form a gate electrode (conductive body).

FIG. 9 schematically shows the steps of manufacturing (gate electrode processing) a general MOS transistor. That is, the element isolation region 101,
Gate insulating films 102 are respectively formed (FIG. 10A), and a gate electrode material 103 is deposited via these element isolation regions 101 and the gate insulating film 102 (FIG. 10B).

Thereafter, the resist 104 is patterned by lithography (FIG. 1C), and anisotropic etching is performed using the resist 104 as a mask.
The gate electrode 105 is formed (FIG. 4D).

However, in the prior art, the apparent thickness of the gate electrode material 103 is smaller than the actual deposition thickness at the stage before the anisotropic etching due to the underlying step due to the element isolation region 101. There is a thick region (near the arrow a in the drawing).

For this reason, when performing anisotropic etching at the time of processing the gate electrode, the amount of etching is set so that the gate electrode material 103 in the region where the film thickness is the maximum can be sufficiently removed. The etching of the thin film region of the electrode material 103 is longer than the time required for sufficient removal.

As a result, as shown in FIG. 1D, the etching proceeds in such a manner that the gate insulating film 102 is scraped off.
When 6 occurs, the characteristics of the element as the MOS transistor greatly differ from the design values.

Such a phenomenon becomes more apparent as the thickness of the gate insulating film becomes thinner with miniaturization of the device, and urgent measures have been desired. In the conventional MOS transistor described above, the gate electrode 105
Is formed at the same time as the formation of the metal wiring (conductor) 107 on the element isolation region 101.

According to such a forming method, since the upper surfaces of the gate electrode 105 and the metal wiring 107 are not on the same plane (at the same height), for example, when forming a multilayer wiring, the surface of the interlayer film is not formed. It is difficult to planarize, and the patterning of the upper layer wiring becomes complicated.

Further, even if flattening can be easily performed, formation of a contact hole becomes difficult because the depth of a contact with an upper wiring varies depending on a place, that is, opening of a hole and embedding of a contact become complicated. There was a problem of doing.

On the other hand, a DRAM having a stacked structure (Dyn)
In the case of an amic RAM, there is a demand that the thickness of the metal wiring be reduced in order to reduce the capacitance between the wirings in the memory cell part in order to optimize the device characteristics, but a large current is required in the peripheral circuit part. There is a demand to reduce the resistance for flowing and to increase the thickness for improving reliability.

Conventionally, the thickness of metal wiring in a DRAM is generally one type, and it has not been possible to form each wiring with a thickness that can simultaneously satisfy the above two different requirements.

In response to such a problem, in recent years, proposals have been made to make it possible to partially (or locally) change the film thickness of a metal wiring (for example, Japanese Patent Application Laid-Open No. Hei 4-1045).
No. 5).

However, in this proposal, although the thickness of the metal wiring can be partially changed, the upper surface of the metal wiring is not on the same plane. When it is formed, it is difficult to flatten the surface of the interlayer film, and the patterning of the upper layer wiring becomes complicated. Further, even if flattening can be easily performed, there is a problem that it is difficult to form a contact hole because a depth of a contact with an upper layer wiring varies depending on a place.

[0016]

As described above, in the prior art, since the upper surfaces of the gate electrode and the metal wiring are not on the same plane, when forming a multilayer wiring, patterning of the upper wiring and formation of contact holes are performed. There was a problem that it was difficult.

Accordingly, the present invention provides a method of manufacturing a semiconductor device suitable for forming a multi-layer wiring, wherein the height of the upper surface of the conductor can be made uniform while locally changing the thickness of the conductor. It is intended to be.

[0018]

In order to achieve the above object, in a method of manufacturing a semiconductor device according to the present invention, a step of forming a step on a semiconductor substrate and the step of forming the step on the semiconductor substrate are described. Forming an insulating film on the substrate, flattening the upper surface of the insulating film by a surface polishing method, and forming a first groove on the surface of the flattened insulating film on the step; Forming a second groove deeper than the first groove on the surface of the semiconductor substrate; and depositing a conductive layer on the insulating film on which the first and second grooves are formed. And polishing the surface of the conductive layer to remove the conductive layer other than the groove on the insulating film, and burying a conductor in each of the first and second grooves, and the upper surface is made flush. Forming the first and second wirings simultaneously. Is formed, the first wiring is a wiring for lining the word lines of the memory, wherein the second wiring is a wiring for the peripheral circuit of the memory.

[0019]

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a memory cell array region with a step on a semiconductor substrate and a step of forming the memory cell array region on the semiconductor substrate on which the memory cell array region is formed are provided. Forming an insulating film along, and polishing the surface to make the upper surface of the insulating film
Planarizing , forming a first groove on the planarized surface of the insulating film, and forming a second groove on the surface of the insulating film having a depth different from that of the first groove. The process of
Depositing a conductive layer on the insulating film in which the first and second grooves having different depths are formed, and polishing the surface of the conductive layer to form a conductive layer other than the grooves on the insulating film; Removing, forming a conductor in the groove, forming a first groove on the step to line up a word line of a memory, and the semiconductor substrate other than the step. A second groove is formed thereon to form wiring for peripheral circuits of the memory.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a memory cell array region with a step on a semiconductor substrate and a step of forming the memory cell array region on the semiconductor substrate on which the memory cell array region is formed are provided. Forming an insulating film along the surface, polishing the surface to flatten the upper surface of the insulating film, and forming a first groove on the surface of the flattened insulating film on the step. And the first
Depositing a conductive layer on the insulating film having the groove formed therein, and polishing the surface of the conductive layer deposited on the insulating film to line the word line of the memory in the first groove. Forming a second groove having a depth different from that of the first groove on a surface of the insulating film on the surface of the semiconductor substrate other than the step; Depositing a conductive layer on the insulating film having the groove formed therein, and polishing a surface of the conductive layer deposited on the insulating film to form a wiring for a peripheral circuit of a memory in the second groove; Forming step.

According to the method of manufacturing a semiconductor device of the present invention, the upper surface of the conductor can be formed as the same plane. This makes it easy to pattern upper layer wiring and form contact holes when forming multilayer wiring, while locally changing the thickness of the conductor to optimize device characteristics. is there.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a cross-sectional structure of a MOS transistor according to the present invention.

That is, this MOS transistor is, for example, an element isolation oxide film (element isolation region) formed on a P-type semiconductor substrate 10 with a step by selective oxidation.
11, a gate oxide film (gate insulating film) 12 formed by thermal oxidation, and an upper surface of a conductive layer uniformly deposited using n-type polysilicon as a material. A gate electrode 15a and a metal wiring 15b formed by anisotropic etching using a resist (not shown) as a mask, and a diffusion region 16 serving as a source and a drain formed by ion implantation of an impurity such as phosphorus. I have.

In this case, after processing so that the height of the upper surface of the conductive layer made of a gate electrode material or the like is within one plane,
Conductor, that is, gate electrode 15a and metal wiring 15b
Patterning is performed.

Next, a method of manufacturing the above-described MOS transistor will be described. FIG. 2 shows an outline of a manufacturing process of the above-described MOS transistor. For example,
First, an oxide film 11 for element isolation is formed on a P-type semiconductor substrate 10 with a step by a selective oxidation method, and then a gate oxide film 12 is formed by thermal oxidation (FIG. 1A).

Subsequently, a conductive layer 13 made of n-type polysilicon as a material for forming a gate electrode 15a and a metal wiring 15b is uniformly deposited on the substrate 10 (FIG. 2B). ).

The conductive layer 13 deposited on the substrate 10
Is processed so that the surface thereof is gradually removed by, for example, a surface polishing method so that the height of the upper surface is constant (within one plane) (FIG. 3C).

That is, since there is an underlying step due to the element isolation oxide film 11 on the semiconductor substrate 10, a region thicker than the actual deposited film thickness caused by depositing the conductive layer 13 along the underlying step is provided. Is sufficiently removed in advance.

As a result, the thickness of the conductive layer 13 immediately before patterning the gate electrode 15a and the metal wiring 15b is the same as the thickness of the actually deposited conductive layer 13 for all the regions on the substrate 10. It can be:

Therefore, the amount of etching at the time of anisotropic etching at the time of processing the gate electrode is reduced by the gate oxide film 1.
By setting the time so that the thickness of the conductive layer 13 on the substrate 2 is sufficiently removed, there is no over-etching, that is, without removing the gate oxide film 12 and removing the substrate 10 as a base, The electrode 15a can be formed.

Thereafter, the resist 14 is patterned by lithography, and anisotropic etching is performed using the resist 14 as a mask (FIG. 4D). At this time, the oxide film 11 for element isolation is also slightly removed together with the conductive layer 13, but the amount is extremely small due to the difference in etching rate between the oxide film 11 for element isolation and the conductive layer 13. Since it is very thick, it does not affect the characteristics of the device.

After the formation of the gate electrode 15a on the gate region having no underlying step and the formation of the metal wiring 15b on the underlying step, respectively, further, after the resist 14 is removed, phosphorus or the like is formed. The MOS transistor shown in FIG. 1 is formed by forming the diffusion region 16 serving as a source and a drain by ion implantation of the impurity.

In the above-described MOS transistor, when forming a multi-layer wiring having the gate electrode 15a and the metal wiring 15b as lower wirings, an interlayer insulating film is further deposited from above and the surface of the interlayer insulating film is planarized. After the formation of the contact holes, formation of an upper layer wiring (both not shown) and the like are performed.

In this case, since the heights of the upper surfaces of the gate electrode 15a and the metal wiring 15b are fixed, the surface of the interlayer insulating film can be easily flattened and the depth of the contact with the upper wiring can be reduced. Thus, the patterning of the upper layer wiring and the formation of the contact hole can be easily performed.

Next, another example according to the present invention will be described. FIG. 3 schematically shows another manufacturing process of the MOS transistor according to the present invention.

For example, on a P-type semiconductor substrate 20, first, a silicon nitride film 21 serving as an oxide film for element isolation is formed. This silicon nitride film 21 is formed, for example, by processing silicon nitride deposited by a vapor deposition method by anisotropic etching.

Subsequently, a gate oxide film 22 is formed by thermal oxidation on the substrate 20 on which the silicon nitride film 21 has been formed (FIG. 1A). Thereafter, a conductive layer 23 made of a gate electrode material made of, for example, n-type polysilicon for forming a gate electrode is uniformly deposited (FIG. 2B).

Then, in the same manner as in the previous example, the upper surface of the gate electrode material 23 is smoothed by, for example, a surface polishing method so that the height of the upper surface is made constant. Thereafter, the resist 24 is patterned by lithography (FIG. 3C), and anisotropic etching is performed using the resist 24 as a mask, thereby forming a gate electrode (conductor) as shown in FIG. 25 are formed.

In this case as well, the gate electrode 25 can be formed without over-etching, in which the gate oxide film 22 is scraped off and the substrate 20 as a base is cut off.
Then, after the resist 24 is removed, impurities such as phosphorus are ion-implanted to form diffusion regions (not shown) serving as a source and a drain, thereby forming a MOS transistor.

The gate electrode 25 is not limited to one made of one kind of metal (here, n-type polysilicon). For example, a MOS having a gate electrode made of two kinds of metals is used.
It can also be applied to transistors and the like.

FIG. 4 shows a MOS transistor having a gate electrode of a two-layer structure as still another example according to the present invention. Here, a gate electrode 25 composed of a conductive layer 23 made of, for example, n-type polysilicon and a metal silicide layer (for example, Ti) 31 is shown as an example.

In this case, the same operation can be performed by smoothing the upper surface of the conductive layer 23 by polishing or the like and then forming the metal silicide layer 31 thereon. As described above, the height of the upper surface of the conductive layer deposited on the substrate can be set within one plane.

That is, of the conductive layer deposited on the substrate,
A region thicker than the actual deposited film thickness due to the underlying step is removed before patterning the gate electrode. As a result, the amount of etching at the time of anisotropic etching can be set to a time at which the thickness of the actually deposited conductive layer is sufficiently removed or less, and the amount of etching can be applied to all regions on the substrate. Can be etched. Therefore, it is possible to easily prevent the problem that the gate insulating film is etched by over-etching and the underlying substrate is digged during the processing of the gate electrode only by adding one step of smoothing.

In addition, since the upper surface of the conductive layer is smoothed by polishing, the time required for etching can be shortened by that much as compared with the conventional case. In addition, since it is possible to equalize the heights of the upper surfaces while changing the thicknesses of the gate electrode and the wiring, when forming a multilayer wiring, it is necessary to pattern the upper wiring and to make contact with the upper wiring. Holes can be easily formed.

The present invention is not limited to the case where a gate electrode of a MOS transistor is formed, but is also applicable to the case of forming a metal wiring in a DRAM having a stacked structure, for example.

FIG. 5 schematically shows a DRAM having a stacked structure according to the first embodiment of the present invention. 2A is a plan view showing a schematic configuration of the DRAM, FIG. 2B is a sectional view along the line AA ′, and FIG. 2C is a sectional view along the line BB ′. It is.

In other words, this DRAM has, for example, a memory cell section 51 and a peripheral circuit section 52 as one constituent unit, and a plurality of these (only one unit is shown in the drawing for convenience) are shown. Is the semiconductor substrate 53
It is configured to be alternately arranged on the upper side.

The memory cell section 51 is composed of, for example, a plurality of memory cell array areas 51a, and each of the memory cell array areas 51a is formed by integrating several cells of capacitors 51b and switching MOS transistors (not shown). It has been.

The memory cell portion 51 is provided with a plurality of word lines 54 formed of, for example, polysilicon so as to extend longitudinally through each memory cell array region 51a.

Further, the memory cell portion 51 is formed so as to cross each memory cell array region 51a.
For example, a bit line 55 from the peripheral circuit section 52 is connected.

A MOS transistor for switching each cell in the memory cell array region 51a is connected to each intersection of the word line 54 and the bit line 55.

That is, each of the memory cells comprises a switching transistor and a capacitor 51b connected to the transistor, and the gate is connected to the word line 5
4, the drain is individually connected to the bit line 55, and the source is connected to the ground potential via the capacitor 51b.

The peripheral circuit section 52 comprises a row / column decoder for selectively turning on / off a switching MOS transistor of each cell, an input / output amplifying circuit (both not shown), and the like. .

For example, when reading data,
The word line 54 connected to the target cell is set to a high voltage by the row decoder, and the bit line 55 is set to the high voltage by the column decoder.

Then, the switching MOS transistors of all the cells in the row direction connected to the word line 54 are turned on, and the drain and source of the switching MOS transistors corresponding to the cells in the column direction connected to the bit line 55 are turned on. Current flows between them.

Thus, the data stored in the cell, that is, the electric charge of the capacitor 51b is read through the input / output amplifier circuit. In addition, data writing is performed similarly.

In the DRAM (stack type structure) having such a structure, each memory cell array region 51a of the memory cell portion 51 is formed due to the presence of the capacitor 51b and the like.
Is thicker than other portions (for example, the peripheral circuit portion 52) and is formed with a step.

Note that, for example, a silicon dioxide film 56 is provided between the capacitor 51b, the word line 54, and the bit line 55. On the other hand, a shunt as a first wiring for lowering the wiring resistance of each of the word lines 54 is provided above the memory cell unit 51.
Metal wiring (conductor) 57 for the peripheral circuit 52
Metal wirings (conductors) 58 as second wirings connected to the bit lines 55 are provided via silicon dioxide films 59 respectively.

The thickness of silicon dioxide film 59 is, for example, 4000 angstroms or more. The backing metal wiring 57 is connected to each of the word lines 54 via contact holes 60 formed in the silicon dioxide films 56 and 59, for example, between the memory cell array regions 51a of the memory cell portion 51. I have.

The metal wiring 58 is formed, for example, in the peripheral circuit 5
2, it is connected to the bit line 55 via a contact hole 61 formed in the silicon dioxide film 59.

The metal wirings 57 and 58 are formed by polishing the upper surface of a conductive layer uniformly deposited using, for example, aluminum (Al) having a lower wiring resistance than the polysilicon forming the word lines 54 by a surface polishing method. After removing and smoothing, it is formed by anisotropic etching using a resist described later as a mask.

In this case, after processing so that the height of the upper surface of the conductive layer is within one plane, the metal wirings 57 and 58 are patterned, and the word lines 54 of the memory cell portion 51 are lined. The thickness of the metal wiring 57 to be formed is smaller than the thickness of the metal wiring 58 by the difference between the underlying steps.

This is because the word line 54 of the memory cell portion 51
When considering the wiring capacitance of the metal wiring 57 that backs
This is advantageous. Conversely, the metal wiring 58 in the peripheral circuit section 52 is inevitably thicker than the metal wiring 57 by the absence of the base step, so as to reduce the resistance when a large current flows and to improve the reliability. Is very desirable.

On the upper layer of the memory cell section 51 and the peripheral circuit section 52, an upper layer wiring 63 for forming a multilayer wiring along the bit line 55 is provided via an interlayer insulating film 62.

The upper wiring 63 is formed of the interlayer insulating film 62
Is formed by, for example, patterning Al after flattening the surface of the memory cell. In each memory cell array region 51a of the memory cell portion 51, a contact is made with each of metal wirings 57 for backing the word line 54. The peripheral circuit unit 5 is connected through a hole 64.
2 is connected to the metal wiring 58 via a contact hole 65.

That is, a hole for contact with the upper wiring 63 is formed in the flattened interlayer insulating film 62, and thereafter, for example, Al is uniformly deposited and anisotropically formed using a resist described later as a mask. The contact hole 6 is patterned into a predetermined shape by reactive etching.
4, 65 and the upper wiring 63 are formed.

In this case, since the upper surfaces of the metal wirings 57 and 58 are processed in advance so that the heights are within one plane, the surface of the interlayer insulating film 62 can be easily flattened, and the upper wirings can be easily formed. 63 can be easily patterned.

Further, since the depths up to the metal wirings 57 and 58 become uniform, the contact holes 64 and 65 can be easily formed. The passivation film 6 is formed on the top of the memory cell section 51 and the peripheral circuit section 52.
6 is formed, and the surface of the element is protected.

Next, a method of manufacturing the above-described DRAM will be described. FIG. 6 shows the DR according to the first embodiment.
1 shows an outline of an AM manufacturing process. Here, description will be made using a cross section taken along the line AA 'in FIG.

For example, on a semiconductor substrate 53, a cell (consisting of a capacitor 51b and a MOS transistor (not shown)) in each memory cell array region 51a of a memory cell portion 51, a peripheral circuit portion 52, a word line 54, a silicon dioxide film 56 , And bit line 55 are formed with a step, and then a silicon dioxide film 59 is formed (FIG. 7A).

Subsequently, after a hole is opened in the silicon dioxide film 59 of the peripheral circuit portion 52 for contact with the bit line 55 (between the memory cell array regions 51a of the memory cell portion 51, The word line 54
A hole for contact with the same is also opened),
A conductive layer 67 made of Al or the like having a lower wiring resistance than polysilicon is uniformly deposited on the silicon dioxide film 59 (FIG. 2B).

In this case, by depositing a metal material such as Al by sputtering or the like, the contact holes 60 and 61 are buried in the holes and the word lines 54 of the memory cell portion 51 are lined. And a conductive layer 67 for forming the metal wiring 58 of the peripheral circuit section 52 are formed.

The surface of the conductive layer 67 deposited on the silicon dioxide film 59 is gradually etched and removed by, for example, a surface polishing method so that the height of the upper surface becomes constant. Figure (c).

That is, since there is an underlying step due to the memory cell portion 51 on the semiconductor substrate 53, a region thicker than the actual deposited film thickness caused by the deposition of the conductive layer 67 along the underlying step is previously formed. Sufficiently removed.

Thus, the thickness of the conductive layer 67 immediately before patterning the metal wirings 57 and 58 is equal to or less than the thickness of the actually deposited conductive layer 67 for all the regions on the substrate 53. can do.

Therefore, the amount of etching performed later in the anisotropic etching during the processing of the metal wiring is reduced by the peripheral circuit portion 52.
By setting the time at which the thickness of the conductive layer 67 is sufficiently removed, the metal wirings 57 and 58 can be easily formed.

In the case of the first embodiment, the conductive layer 67
Since the silicon dioxide film 59 below the silicon dioxide film 59 is formed sufficiently thick, the silicon dioxide film 59 is not erroneously etched down to the base.

Although the silicon dioxide film 59 of the memory cell portion 51 is slightly removed, the amount of the silicon dioxide film 59 is extremely small because the etching rates of the conductive layer 67 and the silicon dioxide film 59 are different, which may affect the characteristics of the element. Absent.

Further, the thickness of the conductive layer 67 can be locally changed by processing in advance so that the height of the upper surface of the conductive layer 67 is within one plane.
For example, the thickness of the conductive layer 67 on the memory cell section 51 can be reduced, and the thickness of the conductive layer 67 on the peripheral circuit section 52 can be increased.

As a result, it is possible to form metal wirings 57 and 58 having different film thicknesses in the memory cell portion 51 and the peripheral circuit portion 52 at the time of metal wiring processing later.

Thereafter, the resist 68 is patterned by lithography, and anisotropic etching is performed using the resist 68 as a mask (FIG. 4D). Thereby, in the memory cell unit 51, the peripheral circuit unit 52
In the peripheral circuit portion 52, a metal wire 58 thinner than the metal wire 58 is formed, and in the peripheral circuit portion 52, a metal wire 58 thicker than the metal wire 57 in the memory cell portion 51 is formed.

After removing the resist 68,
Deposition and planarization of the interlayer insulating film 62, opening of holes for contact with the upper wiring 63, formation of contact holes 64 and 65 by deposition of a metal material, patterning of the upper wiring 63, and formation of a passivation film 66 The DRA shown in FIG.
M is formed.

In this case, since the upper surfaces of the metal wirings 57 and 58 have a constant height, the surface of the interlayer insulating film 62 can be easily flattened, and the depth of contact with the upper wiring 63 can be reduced. The upper wiring 63
And the formation of the contact holes 64 and 65 can be easily performed.

As described above, according to the first embodiment, the upper surface of the conductive layer is smoothed in advance so that the upper surface of the conductor can be formed on the same plane. In addition, even when the thickness of the metal wiring is locally changed, the patterning of the upper wiring and the formation of the contact hole can be easily performed when the multilayer wiring is formed.

That is, while changing the thickness of the conductive layer in the memory cell portion and the thickness of the conductive layer in the peripheral circuit portion,
By making the height of the upper surface of the conductive layer uniform, it becomes easy to flatten the surface of the interlayer insulating film on the metal wiring,
Since the depth of the contact with the upper layer wiring can be made uniform, patterning of the upper layer wiring and formation of a contact hole can be easily performed.

In addition, a metal wiring which is desired to be thin to lower the wiring resistance, a resistance lowering to allow a large current to flow,
More optimal device characteristics can be obtained, for example, it is possible to form a metal wiring to be thickened to improve reliability.

In particular, the present invention is very useful for a DRAM having a stacked structure in which the height of a capacitor is increasing as the degree of integration increases. The method of making the height of the upper surface of the metal wiring uniform is not limited to the method of polishing the surface of the conductive layer, but may be the method of embedding the metal wiring.

A method for making the upper surface uniform by embedding metal wiring will be described below. 7 and 8 show the outline of the manufacturing process of the DRAM according to the second embodiment. Here, description will be made using a cross section taken along the line AA 'in FIG.

For example, on a semiconductor substrate 53, a cell (consisting of a capacitor 51b and a MOS transistor not shown) in each memory cell array region 51a of a memory cell portion 51, a peripheral circuit portion 52, a word line 54, a silicon dioxide film 56 , And bit line 55 are formed with a step, and then silicon dioxide film 59 is formed.

After a hole is opened in the silicon dioxide film 59 of the peripheral circuit portion 52 for contact with the bit line 55 (the above-mentioned region between the respective memory cell array regions 51a of the memory cell portion 51). A hole for contact with the word line 54 is similarly formed), and an interlayer insulating film 62 is uniformly deposited on the silicon dioxide film 59 (FIG. 7A).

The surface of the interlayer insulating film 62 deposited on the silicon dioxide film 59 is gradually etched and removed by, for example, a surface polishing method, and is processed so that the height of the upper surface becomes constant. FIG. 7 (b).

Thereafter, the resist 71 is patterned by lithography, and anisotropic etching is performed using the resist 71 as a mask. As a result, in the memory cell portion 51, a first groove 72 for embedding a metal wiring for lining the word line 54 is opened so as to penetrate the interlayer insulating film 62 (FIG. 7).
(C)).

After the resist 71 is removed, the resist 73 is patterned again, and anisotropic etching is performed using the resist 73 as a mask.
Thereby, in the peripheral circuit section 52, the bit line 5
5 for embedding the metal wiring connected to
A second groove 74 deeper than the groove 72 is formed so as to penetrate the interlayer insulating film 62 (FIG. 8A).

Thereafter, the resist 73 is removed, and a conductive layer made of Al or the like having a lower wiring resistance than polysilicon is uniformly deposited on the interlayer insulating film 62. In this case, the contact holes 60 and 61 are formed by being buried in the holes by depositing a metal material such as Al by sputtering or the like.

Further, the surface of the conductive layer deposited on the interlayer insulating film 62 is gradually etched and removed by, for example, a surface polishing method so that the height of the upper surface becomes constant.

As a result, the metal wiring 57 for backing the word line 54 of the memory cell section 51 and the metal wiring 58 of the peripheral circuit section 52 are formed in the respective grooves 72,
It is formed so as to be embedded in 74 (FIG. 8B).

In this manner, when metal wires 57 and 58 having the upper surfaces of which the heights are constant are formed, the interlayer insulating film 62 is deposited and flattened, and holes for contact with the upper layer wire 63 are formed. Opening, formation of contact holes 64 and 65 by depositing a metal material, patterning of upper layer wiring 63, and formation of passivation film 66 are performed in the same manner, and thus DR shown in FIG.
AM is shaped.

Also in the case of the second embodiment, since the upper surfaces of the metal wires 57 and 58 have a constant height, the surface of the interlayer insulating film 62 can be easily flattened. The contact depth can be made uniform, and the patterning of the upper wiring 63 and the formation of the contact holes 64 and 65 can be easily performed.

In the memory cell section 51, a backing metal wiring 57 thinner than the metal wiring 58 in the peripheral circuit section 52, and in the peripheral circuit section 52,
Metal wires 58 thicker than the backing metal wires 57 in the memory cell portion 51 are formed, respectively, and device characteristics can be optimized.

As described above, according to the above-described second embodiment, grooves having different depths are formed in an interlayer insulating film having a flattened surface, and a metal wiring is buried in the grooves. In order to optimize the device characteristics, the height of the upper surface of the metal wiring can be made uniform on the same plane while locally changing the thickness of the metal wiring.

Therefore, similar to the first embodiment,
In the case of forming a multilayer wiring, patterning of an upper wiring and formation of a contact hole can be easily performed.

In the case of the second embodiment, the embedding of the metal wiring is not limited to being performed simultaneously in the same step.
It is also possible to separate the steps, that is, to form and fill the second groove after filling the first groove.

The present invention is not limited to the DRAM, but can be easily applied to other semiconductor devices having a stacked structure. Of course, various modifications can be made without departing from the scope of the present invention.

[0105]

As described above, according to the present invention, the height of the upper surface of the conductor can be made uniform while locally changing the thickness of the conductor, which is suitable for forming a multilayer wiring. And a method for manufacturing a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing the structure of a MOS transistor according to the present invention.

FIG. 2 is a cross-sectional view schematically illustrating each step of manufacturing a MOS transistor.

FIG. 3 is a cross-sectional view for illustrating an outline of another manufacturing process of the MOS transistor.

FIG. 4 is a cross-sectional view for explaining an outline of a manufacturing process of a MOS transistor, taking a stacked gate structure as an example.

FIG. 5 is a DRAM according to the first embodiment of the present invention;
FIG. 2 is a configuration diagram schematically showing the structure of FIG.

FIG. 6 is a cross-sectional view for explaining an outline of each process relating to the manufacture of the DRAM.

FIG. 7 is a DRAM according to a second embodiment of the present invention;
Sectional drawing shown for demonstrating the outline of the manufacturing process of FIG.

FIG. 8 is also a cross-sectional view schematically illustrating the manufacturing process of the DRAM according to the second embodiment.

FIG. 9 is a diagram showing M to explain a conventional technique and its problems;
FIG. 4 is a schematic view of each step involved in manufacturing an OS transistor.

[Explanation of symbols]

 10, 20 P-type semiconductor substrate 11 Element isolation oxide film 12, 22 Gate oxide film 13, 23 Conductive layer 14, 24 Resist 15a, 25 Gate electrode 16 Diffusion region 21 Silicon nitride film 31 Metal silicide layer 51 Memory cell part 51a Memory cell array area 51b Capacitor 52 Peripheral circuit part 53 Semiconductor substrate 54 Word line 55 Bit line 57, 58 Metal wiring 62 Interlayer insulating film 63 Upper wiring 67 Conductive layers 68, 71, 73: resist 72: first groove 74: second groove

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/3213 H01L 21/768 H01L 21/8242 H01L 27/108

Claims (3)

(57) [Claims] A step of forming a step on a semiconductor substrate; a step of forming an insulating film on the semiconductor substrate having the step formed therein; and a step of flattening an upper surface of the insulating film by a surface polishing method. A first groove is formed on a surface of the flattened insulating film on the step, and a first groove is formed on a surface on the semiconductor substrate.
Forming a second groove deeper than the first groove, a step of depositing a conductive layer on the insulating film in which the first and second grooves are formed, and polishing the surface of the conductive layer to form the second groove. A conductive layer other than the groove on the insulating film is removed, and a conductor is embedded in each of the first and second grooves.
It comprises a step of forming a second wiring simultaneously, the step is formed by, the first wiring memory
Wiring for backing a word line,
A method for manufacturing a semiconductor device, wherein the wiring is a wiring for a peripheral circuit of a memory . A step of forming a memory cell array region with a step on the semiconductor substrate; a step of forming an insulating film along the step on the semiconductor substrate on which the memory cell array region is formed; A step of polishing to flatten the upper surface of the insulating film; a step of forming a first groove in the flattened surface of the insulating film; and a second step having a different depth from the first groove. Forming a groove on the surface of the insulating film; depositing a conductive layer on the insulating film on which the first and second grooves having different depths are formed; and polishing the surface of the conductive layer. Removing a conductive layer other than the groove on the insulating film to form a conductor in the groove, and forming a first groove on the step to line up a word line of the memory. Wiring on the semiconductor substrate other than the step. Method of manufacturing a semiconductor device wiring, characterized in that in order to form each for the peripheral circuit of the memory to form. A step of forming a memory cell array region with a step on a semiconductor substrate; a step of forming an insulating film along the step on the semiconductor substrate on which the memory cell array region is formed; Polishing, flattening the upper surface of the insulating film; forming a first groove on the surface of the flattened insulating film on the step; forming the first groove; A step of depositing a conductive layer on the insulating film; and a step of polishing a surface of the conductive layer deposited on the insulating film to form wiring for backing a word line of the memory in the first groove. Forming a second groove having a depth different from that of the first groove on a surface of the insulating film other than the step on the semiconductor substrate; and forming the second groove on the surface of the semiconductor substrate. Depositing a conductive layer on the insulating film; and depositing a conductive layer on the insulating film. Method of manufacturing a semiconductor device is characterized in that comprising a step of forming a wiring for the conductive layer peripheral circuit of the memory polished to within said second groove surface.