JP3138800B2 - Signal detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal detection circuit, and more particularly, to a detection circuit for detecting a digital modulation signal.

[0002]

2. Description of the Related Art Generally, as a signal detection circuit of this kind,
For example, the one shown in FIG. 8 is known. The illustrated signal detection circuit is used when detecting an ASK modulation wave that is one of digital modulation waves (digital modulation signals).

This detection circuit includes a detector 11, a low-pass filter (LPF) 12, a comparator 13, and a decision unit 14. The detector 11 is supplied with an ASK modulated wave.
The detector 11 detects the ASK modulated wave, extracts the envelope component of the carrier wave, and supplies the envelope component to the LPF 12 as a detected signal. Then, the detected signal is sent to the comparator 13 after the carrier component is removed by the LPF 12.

[0004] A threshold value equal to half the amplitude of the carrier is set in the comparator 13, and the comparator 13 compares the detection signal with the threshold value and outputs a baseband signal according to the result. Then, the determiner 14 determines whether the baseband signal is output from the comparator 13 and
When the baseband signal is detected, the detection of the ASK modulation wave is output. That is, a detection signal is output.

[0005]

As described above, in the conventional signal detection circuit, since it is necessary to detect an input signal (input modulated wave), a detector corresponding to the modulation method must be provided. . In addition, in the processing system after detection, it is necessary to set a pass band, a threshold, and the like according to signal specifications such as a carrier frequency of a modulated wave and a communication speed.

As described above, in the conventional signal detection circuit, signal detection cannot be performed unless detailed signal specifications of the modulated wave to be detected are known in advance. However, there is also a problem that a processing system must be determined according to the carrier frequency and the communication speed while providing a detector corresponding to the modulation format. That is, a signal detection circuit must be separately prepared every time according to the signal specifications of the modulated wave, and there is a problem that one signal detection circuit cannot cope with various modulated waves.

An object of the present invention is to provide a signal detection circuit capable of coping with various modulated waves.

[0008]

According to the present invention, there is provided a signal detection circuit for receiving a digital modulation signal as an input signal and detecting a baseband signal, wherein the input signal is subjected to binary quantization. Quantizing means for generating a bit data string, and calculating means for receiving the bit data string and generating a calculation result data string representing phase information and frequency information,
A signal detection circuit having detection means for detecting the baseband signal in accordance with the operation result data string.

The arithmetic means sets a time reference point, divides the bit data string from the time reference point by a predetermined frame length, and generates a frame data string composed of a plurality of frame data. Generating means, bit rotating means for performing bit rotation in the frame data by a preset direction and bit number to obtain a bit-rotated frame data sequence, and frames adjacent to each other in the frame data sequence and the bit-rotated frame data sequence Exclusive OR operation means for performing an exclusive OR operation on data in bit units to obtain the operation result data string.

The detecting means counts the number of bits "1" of the operation result data string to generate a counting result, and determines the detection of the baseband signal according to the counting result. Determining means.

Further, there is provided buffer means for temporarily holding the bit data string, and the judging means comprises offset information, frame information,
And the bit rotation information, and the buffer means skips and outputs the bit data string by the number of bits specified by the offset information. The frame generation means moves the time reference point by a time specified by the frame information. The bit rotation means performs the bit rotation in the frame data in the direction and the number of bits defined by the bit rotation information.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

Here, a detection method (processing method) of the signal detection circuit according to the present invention will be described first.

First, referring to FIG. 1, a digitally modulated signal is provided as an input signal to a binary quantizer. In the binary quantizer, the input signal is sampled, and a bit data string (“1”, “1”,
(A data string of “0”). In the illustrated example, “1”
11100001111... ".

Next, the bit data string is divided by a predetermined time length L using a predetermined time point in the bit data string as a time reference point, and the frame data strings FL1, FL
2, FL3,...

An exclusive OR (EX-OR) operation is performed for each bit between adjacent frame data in the frame data string obtained in this manner, and operation result data R1, R2,... Are generated. For example, EX-O for each bit in the frame data FL1 and FL2
Perform R. In the illustrated example, the frame data FL1 is “1”.
1100 ”and the frame data FL2 is“ 0011 ”.
Therefore, when the EX-OR is performed, "110011" is obtained as the result operation data R1. Similarly, when the EX-OR is performed on each bit in the frame data FL1 and FL2, the result operation data R2 is obtained. “001100” is obtained.

The result operation data has the same number of bits as the frame data, and represents the phase information and the frequency information between the frame data as a result of the EX-OR operation.

By the way, the above-mentioned time reference point can be moved by temporarily storing a bit data string in a memory and skipping data of several samples at the time of reading. Such movement of the time reference point is effective for estimating the presence or absence of a signal and the signal section, as described later.

FIG. 2 shows an example of such a movement of the time reference point. Referring to FIG. 2, in FIG. 2, frame division (A) indicates a case where a signal section and frame division are asynchronous (not synchronized), and frame division (B)
Indicates a state in which the data of the frame division (A) is skipped by six samples (offset + 6), and the frame division and the signal section are synchronized.

In the frame division (A), the frame data FL1, FL2, and FL3 are each set to "101".
100111000 "," 1110011100
0 "and" 111000100110 "
When the EX-OR operation is performed as described above, “01010000” is obtained as the result operation data R1 and R2, respectively.
0000 "and" 000000001110 ".

On the other hand, in the frame division (B), the frame data FL1, FL2, and FL3 are "111000111000" and "111000111", respectively.
000 "and" 100110100111 ", the EX-OR operation performed as described above results in" 000000 "as result operation data R1 and R2, respectively.
000000 "and" 011110011111 "are obtained.

Here, when the respective operation result data are compared with each other by the frequency of bit "1", in the case of frame division (B), the frequency of the operation result data R1 is zero and the operation result data R1 and R2 It can be seen that the frequency difference is large.

As described above, by moving the time reference point, a signal section or the like can be estimated from the calculation result data.

For a frame length L and a signal period T, L =
When there is a relationship of nT (n is an integer), the above-mentioned calculation result data has a minimum frequency value (phase in-phase), and L = nT +
In the case of (T / 2), the calculation result data has the maximum frequency value (phase reverse phase). Therefore, although the calculation result data differs depending on the frame length L and the signal period T, when the input signal is a periodic signal, the same calculation result may be obtained by the bit rotation processing shown in FIG. it can.

Referring to FIG. 3, frame division (A) is performed by:
The case where the frame length L = nT (n = 1) is shown. In this case, the frequency of the bit “1” is zero in both the operation result data R1 and R2. On the other hand, the frame division (B) shows the case where the frame length L ≠ nT. In this case, the frequency of both the calculation result data R1 and R2 does not become zero, and the error between the frame length L and the signal period T is reduced. It appears in the operation result data R1 and R2.

[0026] Here, in the frame division (B), the frame data FL2 and FL3, bit rotation frame data FL2 performing a bit rotation 2 bits to the ^right, and ^FL3, and when, these bit rotation frame data FL2 ^and, F
When the calculation result data is obtained for the frame division (B) including L3 ^, the calculation result data R1 and R2 are obtained.
Has almost zero frequency. That is, the same result as in the case of L = nT is obtained.

Therefore, by performing the bit rotation, the existence of the periodic signal can be known from the operation result data regardless of the frame length L and the signal period T.

Next, an example of the signal detection circuit according to the present invention will be described.

Referring to FIG. 4, the illustrated signal detection circuit comprises:
A binary quantizer 21, a buffer memory 22, an arithmetic unit 23,
The binary quantizer 21 is provided with a digital modulation signal as an input signal, as described above.

The binary quantizer 21 binarizes the input signal at the sampling frequency Fs and converts the input signal to a binary data sequence (1, 0).
The data is stored in the buffer memory 22 as a data string).

The arithmetic unit 23 includes a frame division unit 23a, a bit rotation unit 23b, and an EX-OR unit 23c.
And 2 read from the buffer memory 22.
The coded data sequence is provided to the frame dividing unit 23a. The frame division unit 23a performs frame division based on frame information described later to generate a frame data sequence. This frame data sequence is stored in the bit rotation unit 2
3b, the bit rotation unit 23b executes bit rotation based on bit rotation information described later, and supplies the bit rotation frame data together with the frame data sequence to the EX-OR unit 23c. The EX-OR unit 23c performs an EX-OR between adjacent frame data (including bit rotation frame data) to generate operation result data.

The counter 24 counts the frequency of the bit “1” with respect to the operation result data, and determines the count result as a decision unit 25.
Give to. The determiner 25 generates offset information, frame information, and bit rotation information based on the counting result.

The offset information, frame information, and bit rotation information are fed back to the buffer memory 22, the frame division unit 23a, and the bit rotation unit 23b.

In the buffer memory 22, when the binary data string is read according to the offset information, the data is skipped according to the offset information. As a result, the movement of the time reference point is performed. The frame division unit 23a determines the frame length according to the frame information, and the bit rotation unit 23b determines the left and right bit rotation and the number of bits according to the bit rotation information.

As described above, until a signal is detected from the counting result, the decision unit 25 repeatedly generates offset information, frame information, and bit rotation information according to the counting result. Then, when a signal is detected from the counting result, the determiner 25 sends out a detection signal (detection output).

Here, a specific example of digital modulation signal detection will be described. Here, the description will be given on the assumption that the communication speed of the digital modulation signal is known (if the communication speed of the digital modulation signal is known, signal detection becomes extremely easy).

Now, as an input signal, the communication speed is 100
It is assumed that an ASK modulation signal of bps is given.

If the communication speed is known, the frame length is fixed. Further, in the case of an ASK modulation signal,
The frame length is の of the communication speed.

If the sampling frequency Fs in the binary quantizer 21 is Fs = 20 kHz, the frame length becomes 100 bits (Fs / communication speed / 2). Here, in consideration of skipping of data due to offset, the amount of data stored in the buffer memory 22 is 52 frames (5200 bytes).
Bit). It is assumed that 50 frames of operation result data are obtained from these frame data.

The ASK-modulated signal is binarized at a sampling frequency Fs = 20 kHz in a binary quantizer 21 and stored in a buffer memory 22 as a binary data string. First, the binarized data sequence is read from the buffer memory 22 with an offset of zero, and is divided into frames by the frame dividing unit 23a to form a frame data sequence. The bit rotation unit 23b does not perform bit rotation, and the EX-OR unit 23c performs EX-OR processing.

Similarly, a binary data string is read from the buffer memory 22 with an offset of zero, and the bit rotation unit 23b and the EX-OR unit 23c repeatedly perform the bit rotation process and the EX-OR process, respectively (in this case, Changes the amount and direction of bit rotation each time).

In the operation result data obtained as a result of such repetitive processing, the frequency of bit "1" is obtained for every bit for each processing, and then the lowest value among these frequencies is obtained.

FIG. 5A shows an example of the result. FIG.
In (A), the codes R and L on the horizontal axis (bit rotation) are the rotation directions (right and left), respectively.
And the number following each of the symbols R and L indicates the amount of rotation (the number of bits). Reference numeral N indicates a case where bit rotation is not performed.

From FIG. 5A, it can be seen that the frequency of the bit "1" becomes the lowest when the rotation (R3) of 3 bits is performed to the right. This indicates that the carrier component of the modulated signal has been detected. Then, as long as the frequency of the carrier signal does not change, the frequency becomes the lowest value at R3.

Next, fixing the rotation to R3,
The signal interval, that is, the symbol timing is estimated by changing the offset. Referring to FIG. 5B, when estimating the symbol timing, the symmetry of the distribution of bit “1” is digitized for each operation result data frame to make the distribution state symmetric. From FIG. 5B, when the offset is +40, the frequency becomes the lowest, and at this time, the operation result data frame matches the symbol timing.

FIG. 6 shows the frequency distribution of bit "1" for each operation result data frame obtained by the above-described processing. From FIG. 6, it can be seen that the frequency is very small in the section where the carrier wave component exists, and about 50 in other sections.

Incidentally, the state of the above-described processing can be visualized by a monitor device (not shown). FIGS. 7A to 7C show examples in which a part of the processing state shown in FIGS. 5A and 5B is visualized.

FIG. 7 shows that bit “1” is set for 50 frames of the operation result data string obtained after the EX-OR processing.
And "0" are represented by black and white dots, respectively. FIG. 7A shows the result of bit rotation N, and FIG. 7B shows the result of bit rotation R3. FIG. 7C shows the result of the timing detection.

As described above, when the input signal is an ASK modulated signal, signal detection can be performed based on the existence and the existence period of the carrier. In the above example, the input signal is AS
Although the description has been given of the case where the signal is a K-modulated signal, signal detection can be easily performed by performing similar processing in other modulation methods.

[0050]

As described above, according to the present invention, signal detection can be performed without performing detection, and as a result, digital modulation signals of various modulation schemes can be handled. That is, there is an effect that digital modulation signals of different modulation methods can be processed by the same signal detection circuit.

Further, according to the present invention, since the processing for signal detection is a very simple bit logical operation, high-speed processing can be performed.

In addition, since it has a feedback loop, it can adaptively cope with various signal specifications, and can estimate the signal specifications.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining basic processing in a signal detection circuit according to the present invention.

FIG. 2 is a diagram for explaining a method of estimating a signal existence section in a signal detection circuit according to the present invention.

FIG. 3 is a diagram for explaining detection of a periodic signal in the signal detection circuit according to the present invention.

FIG. 4 is a block diagram illustrating an example of a signal detection circuit according to the present invention.

FIG. 5 is a diagram illustrating an example of a signal detection process in the signal detection circuit according to the present invention.

FIG. 6 is a diagram for explaining an example of a signal detection result in the signal detection circuit according to the present invention.

FIG. 7 is a diagram visualizing and showing the signal detection process shown in FIG. 5;

FIG. 8 is a block diagram showing a conventional signal detection circuit.

[Explanation of symbols]

 Reference Signs List 21 Binary quantizer 22 Buffer memory 23 Operation unit 23a Frame division unit 23b Bit rotation unit 23c EX-OR unit (exclusive OR operation unit) 24 Counter 25 Judgment unit

Claims (6)

(57) [Claims] 1. A signal detection circuit for receiving a digitally modulated signal as an input signal and detecting a baseband signal, wherein the quantization means binarizes the input signal to generate a bit data sequence. An operation unit that receives the bit data sequence and generates an operation result data sequence representing phase information and frequency information, and a detection unit that detects the baseband signal according to the operation result data sequence,
The calculating means sets a time reference point, divides the bit data string for each predetermined frame length from the time reference point, and generates a frame data string including a plurality of frame data, Bit rotation means for performing a bit rotation within the frame data by a preset direction and a predetermined number of bits to obtain a bit rotation frame data sequence, and a bit rotation between adjacent frame data in the frame data sequence and the bit rotation frame data sequence. An exclusive OR operation means for performing an exclusive OR operation on a unit to obtain the operation result data string. 2. The signal detecting circuit according to claim 1, wherein said detecting means counts the number of bits “1” of said operation result data string to generate a counting result, and said counting result. And a determination means for determining the detection of the baseband signal in accordance with the following. 3. The signal detection circuit according to claim 2, further comprising buffer means for temporarily holding said bit data string. 4. The signal detection circuit according to claim 3, wherein said judging means generates offset information based on said counting result, and said buffer means generates only the number of bits defined by said offset information. A signal detection circuit, wherein the bit data string is skipped and output. 5. The signal detection circuit according to claim 2, wherein the determination unit generates frame information based on the counting result, and the frame generation unit generates the frame information based on the frame information. A signal detection circuit wherein the time reference point is moved by a specified time. 6. The signal detection circuit according to claim 2, wherein the determination unit generates bit rotation information based on the counting result.
A signal detection circuit, wherein the bit rotation means performs the bit rotation in the frame data by the direction and the number of bits defined by the bit rotation information.