JP3138623B2 - Structure and semiconductor device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superlattice structure and a semiconductor device using the same, and more particularly, to an ohmic contact technology for a metal electrode of the semiconductor device and a technology for integrating and improving the functions of the semiconductor device.

[0002]

2. Description of the Related Art Semiconductor laser diodes (LDs) for pumping solid-state lasers, measuring, communicating, and compact disks.
In order to increase the output and function of a semiconductor light emitting device such as a laser diode device, the semiconductor device is electrically connected in series in a direction perpendicular to the semiconductor substrate (series connection).
Attempts have been made to stack them.

One of the simplest methods of stacking semiconductor devices by connecting them in series is a method of soldering and bonding a plurality of semiconductor laser devices to increase the output. This method is described in “Large output characteristics of 1.5 μm band eye-safe pulse LD” (Takemasa Tamanuki et al., 1994).
Proceedings of the 55th Federation of Applied Physics-related Lectures
p. 964) (lecture number 21p-S-16), metalorganic vapor phase epitaxy (MOVPE: Metalorg).
anic Vapor Phase Epitaxy)
A current-light output characteristic of a high-output LD element manufactured by using a growth method has been reported.

[0004] In the LD device reported there, a half of the wafer for the LD device is thinned by polishing the back surface, and then a normal LD device forming process is performed. This is a two-stage stacked LD element manufactured by bonding by soldering onto an LD element manufactured by cutting out from an element wafer.

[0005] As shown in FIG.
i / Au 300, n-InP substrate 301, and n-In
P cladding layer 302 and InGaAsP-SCH-5Q
W303, p-InP cladding layer 304, p-In
GaAs contact layer 305, SiO2 306, T
i / Pt / Au 307, a semiconductor element formed by laminating i / Pt / Au 307, Ti / Au 308, n-InP substrate 309,
InP cladding layer 310 and InGaAsP-SCH-
5QW 311, p-InP cladding layer 312, p-
InGaAs contact layer 313 and SiO2 314
And a semiconductor element formed by laminating Ti / Pt / Au 315 are bonded with solder 319.

[0006] InGaAsP-SCH-5QW303,
311 is a Q1.55 μm (5 × 3.7 nm) well layer 3
16 and Q1.2 μm (8 nm) barrier layers 317 are alternately stacked.

By making the light emitting regions closer by the above-described two-stage stack structure, the total light output of these LD elements can be increased to approximately twice the light output of a single LD element.

Although it is possible to integrate the LD elements by arranging them in an array on the surface of the semiconductor substrate, a beam interval of 10
Since it becomes as large as about 0 μm, a device for condensing light is required. Therefore, a technique of stacking semiconductor elements in a direction perpendicular to the semiconductor substrate is important.

In general, if a semiconductor device and a metal layer can be continuously grown epitaxially, it is easier and more feasible to electrically connect the semiconductor devices in series and integrate them in a direction perpendicular to the semiconductor substrate. It seems to be. However, since the lattice constant of a semiconductor differs greatly from that of a metal, it is generally very difficult to realize the same.

However, in recent years, for the purpose of application to a single electronic device such as a metal quantum well device and a metal-based transistor in the future, a molecular beam epitaxy (MBE) has been proposed.
xy) method, NiAl and CoA are formed on a GaAs substrate.
Research for epitaxially growing an intermetallic compound of a thin film such as l has been advanced. These intermetallic compounds are Ni,
It is a compound composed of a transition metal such as Co and a Group III metal such as Al.

The crystal structure of these intermetallic compounds is CsC
It is an l-type and is different from a zinc blende type crystal structure of a III-V compound semiconductor such as GaAs or InP. However, since the lattice constant of these intermetallic compounds is almost equal to 1/2 of the lattice constant of GaAs or InP,
Epitaxial growth on s or InP is possible. FIG. 23 shows the atomic arrangement of NiAl epitaxially grown on AlAs.

FIG. 22 (a) shows the distribution of lattice constants of these typical intermetallic compounds and semiconductor substrates on a number line. As shown in this figure, GaAs, Al
As, CoAl, NiAl, InP, NiIn _0.24 Al
_0.76 , CoIn _0.365 Al _0.635 , InAs, NiIn
_0.71 Al _0.29 , CoIn _0.835 Al _0.165 , CoIn,
It increases in the order of NiIn.

FIG. 1 also shows the composition of a ternary intermetallic compound which is considered to be lattice-matched to an InP substrate, a GaAs substrate or an InAs substrate.

As described above, the crystal growth of an intermetallic compound thin film on a semiconductor substrate is a heteroepitaxial growth of a heteroatom structure, and therefore requires different growth conditions and crystal growth techniques from the prior art.

A conventional example in which a plurality of semiconductor elements are stacked using an intermetallic compound is described in "Electrica".
l and optical characters
ation of back-to-back Sch
ottky (Al, Ga) As / NiAl / (Al,
Ga) As molecular beam epit
axially double double-hete
Structured Diodes "(TLC
Heeks et al., Applied Physics Letter, 56
Volume (11), P.E. 1043, March, 1990), GaAs / AlAs grown by the MBE method.
There is a back-shared Schottky diode having a double heterostructure of / NiAl / AlAs / GaAs.

As shown in FIG. 19, this Schottky diode has an n ⁺ GaAs substrate and an n ⁺ GaAs substrate.
⁺ GaAs, n-type GaAs, and AlAs
And a portion where NiAl and TiAu are laminated, and NiAl
It is composed of a portion on which n-type GaAs and n ⁺ GaAs are stacked.

However, this structure is an experimental structure for evaluating the difference in quality between the two interfaces of the NiAl layer and the semiconductor by using a Schottky diode, and is not a new element aiming at a practical effect.

As described above, although epitaxial growth of an intermetallic compound thin film on a semiconductor substrate is possible, ohmic contact between the semiconductor layer and the intermetallic compound layer has not been achieved. If ohmic contact cannot be made, a Schottky barrier at the metal / semiconductor interface causes no current to flow through the contacted element, or causes element deterioration due to an increase in the drive voltage of the element.

With respect to ordinary group III-V compound semiconductors, techniques for realizing ohmic contact such as metal alloy electrode materials, alloying by high heat treatment, and high concentration doping of semiconductor contact layers have been almost established. However, II-VI group compound semiconductors are susceptible to high heat of 300 ° C. or more, are difficult to dope at a high concentration, and have properties such as a large band gap. Ohmic contact of the electrodes is a major issue.

"Ohmic contact to p-type ZnSe using ZnTe / ZnSe multiple quantum well structure"
(Ita Okee et al., Proceedings of the 54th Joint Lecture on Applied Physics, Spring 1993, p. 257) (lecture number 29p)
-ZL-17) requires that a p-type ZnTe / ZnSe multiple quantum well structure be used to achieve good ohmic contact with p-type ZnSe by utilizing a resonant tunneling current via a quantum level. Have been reported.
FIG. 18 shows the band structure near the interface between the p-type ZnSe semiconductor and the electrode reported in this report.

The above example is an example of achieving good ohmic contact using a semiconductor and a semiconductor superlattice structure.
Because of the large lattice mismatch between ZnTe and ZnSe,
Including the reliability of the element, it cannot be said that the above-mentioned problem has been completely solved.

"Infra-red AlGaAs a
nd visible AlGaInP laserd
iode stack "(DP Bour et al., Electronics Letters, October, 1993, Vo
l. 29 No. 21, p. 1855) discloses an example in which LD elements are stacked by epitaxial growth in a direction perpendicular to a semiconductor substrate.

As shown in FIG. 21, this two-wavelength laser has a substrate N contact 400 and a Ga
As: Si substrate 401, Al _0.8 Ga _0.2 AsN cladding layer 402, 60 ° GaAs or InGaAs
s QW, Al _0.4 Ga _0.6 As SCH 403 and A
l _0.8 Ga _0.2 AsP cladding layer 404 and GaAsP
⁺ Cap layer 405, a portion where a P contact 416 is stacked, and a GaAsP ⁺ cap layer 405 with Al
_0.5 In _0.5 PN-etch stop 406 and Al
_0.5 In _0.5 PP-etch stop 407 and Ga
A portion where AsN 408 and an N contact 415 are stacked, an Al _0.5 In _0.5 PN cladding layer 409 on GaAs N 408, and 80 ° Ga _0.4 In _0.6 PQW,
(Al _0.6 Ga _0.4 ) _0.5 In _0.5 P SCH410
, Al _0.5 In _0.5 PP clad layer 411, Al
_0.5 In _0.5 PP barrier reduction layer 412 and GaAsP ⁺
It is composed of a portion where a cap layer 413 and a P contact 414 are laminated.

This LD element is composed of an AlGaAs LD and an Al
It has a structure in which a GaInP-based LD is stacked and grown with an AlInP high-resistance layer in between, and two electrodes are newly provided in the middle. As a result, laser beams of two different wavelengths that can be independently controlled and that are separated by only about 2 μm are obtained.

[0025]

In the above-mentioned conventional semiconductor device, in the case of a method in which a plurality of semiconductor laser device wafers are thinned by polishing the back surface to form LD devices and then bonded by soldering, a method of forming the semiconductor wafer on the back surface of the semiconductor substrate is required. It is not suitable for mass production because polishing and soldering are troublesome, and it is difficult to adjust the cleavage and bonding positions with the same resonator length.

In addition, when the back surface of the semiconductor substrate is polished, the thickness cannot be made as thin as about 2 μm. When three or more semiconductor elements are bonded together, the distance between laser beams becomes too large. Is not suitable. Since it is difficult to integrate and quantize three or more semiconductor elements by bonding, it is difficult to further increase the output.

Therefore, if the semiconductor element and the intermetallic compound layer can be continuously grown and the semiconductor element can be electrically connected in series, the integration of the semiconductor element becomes easy.
However, the value of the lattice constant of these binary intermetallic compounds is slightly different from １ ／ of the lattice constant of the semiconductor substrate.

FIG. 22B shows the degree of lattice mismatch between the intermetallic compound and the semiconductor substrate. In the figure, + 1.2% for CoAl on a GaAs substrate at room temperature, N
+ 2.1% for iAl, + 8.3% for CoIn, NiIn
There is a + 9.2% lattice mismatch.

Further, CoAl on the InP substrate is -2.5%.
%, -1.6% for NiAl, + 4.4% for CoIn, N
There is a lattice mismatch of + 5.2% for iIn, -5.6% for CoAl, -4.7% for NiAl, C
There is a lattice mismatch of + 1.1% for oIn and + 1.9% for NiIn.

For this reason, when the intermetallic compound is grown beyond the critical film thickness during multi-layer growth or the like, the crystal undergoes a transition and proliferates, the crystal lattice is relaxed, and the crystal quality is significantly reduced. I will.

Even when a lattice-matched intermetallic compound is used, the Schottky barrier at the metal / semiconductor interface can cause
There is a problem that a current does not flow through the connected semiconductor element, or a driving voltage of the semiconductor element increases, a high electric field is applied to the interface, and the element is likely to deteriorate.

In a structure in which LDs and high-resistance layers are alternately epitaxially grown in a direction perpendicular to the semiconductor substrate and the LDs are stacked, the LD elements are stacked in a direction perpendicular to the semiconductor substrate. Since they are not connected in series, they are not suitable for high output.

In this method, in addition to the labor of etching and electrode processing, difficulty in current confinement, control of the beam shape, non-perpendicularity of the laser beam, and the labor required for laminating two or more elements. Is increased.

Accordingly, an object of the present invention is to solve the above-mentioned problems, to greatly improve the reliability of the light emitting element, and to realize highly functional optical devices, electronic devices, and photoelectric fusion devices. It is to provide a superlattice structure that can be used.

Another object of the present invention is to provide a superlattice structure capable of increasing the output, increasing the wavelength, and increasing the wavelength band of a semiconductor laser.

Another object of the present invention is to provide a semiconductor device which can increase the output of a laser, and can be mass-produced and reduced in cost.

[0037]

The structure of the present invention comprises a metal.
The intermetallic compound crystal and the semiconductor crystal are alternately combined, and the metal
An intermetallic compound layer comprising intermetallic compound crystals and the semiconductor
The thickness of the semiconductor layer composed of the crystal and the trueness of the
The empty level and the energy of the conduction band and the valence band of the semiconductor layer
The transmitted level of one of the incident electrons or holes intensifies the phase
A superlattice structure configured to mate
The structure includes a semiconductor layer and a thick film of the intermetallic compound crystal.
The thick film of the intermetallic compound crystal is inserted between the semiconductor
It is characterized by lattice matching with the substrate .

[0038]

Further, the semiconductor layer made of the semiconductor crystal is of an n-type or p-type conductivity.

In addition, the above-mentioned ultra-conductive type including an n-type semiconductor layer
A superlattice comprising a lattice structure and a p-type semiconductor layer;
And a child structure with the thick film of the intermetallic compound crystal interposed therebetween.
It is characterized by being placed.

[0041]

The semiconductor substrate is an InP substrate,
The intermetallic compound that lattice-matches with the InP substrate is NiIn _0.24
Der any of the Al _0.76 or CoIn _0.365 Al _0.635
It is characterized by that .

The semiconductor substrate is an InAs substrate,
The intermetallic compound that lattice-matches with the InAs substrate is NiIn.
_0.71 any of the Al _0.29 or CoIn _0.835 Al _0.165
It is characterized by being .

[0044]

Further, the number of intermetallic compound layers and semiconductor layers is small.
Both have a structure in which the thickness of one layer is gradually varied.
Features.

In addition, at least one adjacent to the intermetallic compound
One semiconductor layer into multiple semiconductor layers with different band gaps
Characterized by having a structure constituted by:

Also, at least one intermetallic compound layer is provided.
A plurality of golds different in at least one of the composition and constituent elements of
Characterized by having a structure composed of intergeneric compound layers
You.

A first semiconductor device according to the present invention has at least one superlattice structure among the above superlattice structures between a semiconductor portion of a semiconductor device and an electrode.

The second semiconductor element according to the present invention is formed by alternately combining at least one of the above superlattice structures and a semiconductor element having the same structure and stacking them in a direction perpendicular to the semiconductor substrate.・ Accumulated.

A third semiconductor device according to the present invention is formed by alternately combining at least one of the above-described superlattice structures and a semiconductor device, and laminating and integrating them in a direction perpendicular to the semiconductor substrate. In the semiconductor element, a layer structure of at least one semiconductor element among the stacked semiconductor elements is different from at least one other semiconductor element.

A fourth semiconductor device according to the present invention comprises a semiconductor substrate formed by alternately combining at least one of the above superlattice structures with one of a high-resistance semiconductor layer and a semiconductor device. In a semiconductor element stacked and integrated in a vertical direction, the structure of at least one semiconductor element among constituent semiconductor elements is different from at least one other semiconductor element, and at least one semiconductor element among stacked semiconductor elements. Are electrically driven independently.

[0052]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the operation of the present invention will be described below.

The structure according to the present invention is, for example, shown in FIG.
As shown in (a), n-type semiconductor / n-type superlattice structure /
The structure is in the order of intermetallic compound layer / p-type superlattice structure / p-type semiconductor.

That is, the structure according to the present invention is n-In
_0.53 Ga _0.47 As semiconductor layer 1 and n ⁺ -In _0.53 Ga
_An n-type superlattice structure in which _0.47 As contact layer 2, NiIn _0.24 Al _0.76 well layer 3 and n-In _0.53 Ga _0.47 As barrier layer 4 are alternately combined, and NiIn _0.24 Al
_0.76 bulk layer (intermetallic compound layer) 5 and p-In _0.53 G
and p-type superlattice structure formed by combining alternately a _0.47 As barrier layer 6 and NiIn _0.24 Al _0.76 well layer 7, p ⁺ -
In _0.53 Ga _0.47 As contact layer 8 and p-In _0.53
And a Ga _0.47 As semiconductor layer 9.

In the structure according to the present invention, the n-type superlattice structure and the p-type superlattice structure are defined by the thickness of the intermetallic compound layer and the semiconductor layer, the vacuum level of the intermetallic compound layer, and the conduction of the semiconductor layer. The energy levels of the band and the valence band are configured so that the transmitted waves of the incident electrons or holes reinforce the phases.

The effect of the resonance tunnel as described above substantially eliminates the Schottky barrier at the interface between the metal and the semiconductor, so that an ohmic contact between the metal and the semiconductor can be realized. Further, in the above-described superlattice structure, by using a superlattice structure having a structure in which the thickness of the intermetallic compound layer or the semiconductor layer is continuously changed, the energy band width of transmitted carriers can be further increased. Thus, the resistance of the layer near the contact interface can be reduced.

Furthermore, since the composition change from semiconductor to metal becomes smoother on average, there is an effect of reducing the Schottky barrier at the interface. Furthermore, since the intermetallic compound layer 5 is lattice-matched with the InP substrate, the critical film thickness can be increased without limitation, which is advantageous for reducing the resistance of the metal layer.

When a voltage is applied to the above structure, FIG.
As shown in (b), electrons 16 and holes 17 are generated in the intermetallic compound layer 5, and the electrons 16 are NiIn lattice-matched to the InP substrate by the resonant tunneling effect 19 of carriers.
Through the n-type superlattice structure composed of the Al well layer 3 and the n-type InGaAs barrier layer 4, the transmitted electron wave 14 reaches the n-type InGaAs semiconductor layer 1.

Similarly, the holes 17 are p-type I lattice-matched to the InP substrate by the resonant tunneling effect 20 of carriers.
After passing through the p-type superlattice structure composed of the nGaAs barrier layer 6 and the NiInAl well layer 7, the transmission hole 15
To the InGaAs type semiconductor layer 9. As a result, n-type In
A current 18 flows from the GaAs semiconductor layer 1 to the p-type InGaAs semiconductor layer 9.

On the other hand, the conventional structure shown in FIG.
As shown in (a), the semiconductor device is configured in the order of n-type semiconductor / metal layer / p-type semiconductor. That is, the conventional structure includes the n-type semiconductor layer 21, the intermetallic compound layer 22, and the p-type semiconductor layer 23.

When a voltage is applied to this structure, the electrons 16 and holes 17 generated in the intermetallic compound layer 22 become reflected waves 25 due to the Schottky barrier 24 at the interface between the metal and the semiconductor, and the intermetallic compound Since current is trapped in the layer 22, almost no current flows. FIG. 3 (b)
17B, reference numeral 11 denotes a conduction band, 12 denotes a Fermi level, and 13 denotes a valence band.

As described above, by using the superlattice structure of the present invention, an ohmic contact between the metal layer and the n-type semiconductor layer or an ohmic contact between the metal layer and the p-type semiconductor layer can be realized.

Further, by using the structure of the n-type superlattice structure / intermetallic compound layer / p-type superlattice structure according to the present invention, the n-type semiconductor layer and the p-type semiconductor layer are interposed via the intermetallic compound layer. Can be connected in series.

Therefore, by alternately stacking the superlattice structure of the present invention and a plurality of optical devices such as light-emitting devices and light-receiving devices and semiconductor devices such as electronic devices that can be epitaxially grown on the same semiconductor substrate, A semiconductor integrated element which is connected in series ohmically can be realized.

A superlattice structure having a semiconductor layer for compensating for crystal lattice mismatch between the intermetallic compound layer and the semiconductor substrate and having a lattice constant different from that of the semiconductor substrate is provided. Since the total amount of body strain can be suppressed to a negligible level, the crystal quality of the semiconductor element layers alternately stacked with the superlattice structure is not reduced.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a sectional view showing the configuration of the first embodiment of the present invention. In the figure, a structure according to a first embodiment of the present invention comprises an n-In _0.53 Ga _0.47 As semiconductor layer 1, an n ⁺ -In _0.53 Ga _0.47 As contact layer 2,
NiIn _0.24 Al _0.76 well layer (hereinafter referred to as well layer) 3 and n-In _0.53 Ga _0.47 As barrier layer (hereinafter referred to as “well layer”).
A superlattice structure on an InP substrate having a structure in which an n-type superlattice structure formed by alternately combining 4) and a NiIn _0.24 Al _0.76 bulk layer (intermetallic compound layer) 5 are sequentially laminated. is there. Note that a structure in which the above-described growth layers are stacked in the reverse order is also possible.

That is, the structure according to the first embodiment of the present invention is a superlattice structure in which an n-type semiconductor / n-type superlattice structure / intermetallic compound layer is lattice-matched on an InP substrate .

FIG. 1B is a band structure diagram of FIG. 1A. In the figure, the vacuum level of the well layer 3 and the energy level of the conduction band 11 and the valence band 13 of the barrier layer 4 or the effective mass of the electrons 16 in the well layer 3 and the barrier layer 4 are compared with the well layer. The thickness of the barrier layer 4 and the thickness of the barrier layer 4 are designed so that the transmitted electron wave 14 strengthens the phase. Thereby, an ohmic contact between the metal layer and the n-type semiconductor layer can be realized.

The above-mentioned superlattice structure and semiconductor element are formed by molecular beam epitaxy (MBE), gas source MBE,
Metalorganic MBE or metalorganic vapor phase epitaxy (MOVP
E) method, or migration enhanced epitaxy (MEE: Migration E) in which different constituent atoms of the growth layer are alternately supplied and grown.
nhancet Epitaxy method, ALE (Atomic Layer Epitaxy)
It can be manufactured using a thin film growth method such as the y) method.
The superlattice structure and the semiconductor element described below are manufactured in the same manner as described above.

The MEE method (or AL
E)), In and A constituting the intermetallic compound layer
Group III atoms such as 1 and transition metals such as Ni are alternately supplied to the semiconductor substrate for growth. In the MEE method (or the ALE method) of the III-V compound semiconductor layer, III
Group atoms and group V atoms are alternately supplied to the semiconductor substrate for growth. These supply cycles are on the order of one to two minutes.

Hereinafter, specific growth for forming a heterostructure of an intermetallic compound layer and a III-V (or II-VI) compound semiconductor layer for realizing the above-described superlattice structure or semiconductor element will be described. The method will be described.

When the intermetallic compound layer is grown next to the group III-V (or group II-VI) compound semiconductor, one or more types of group III (or group II) are formed on the surface of the semiconductor layer. Group), the background pressure of the group V (or group VI) in the growth chamber is sufficiently reduced to 3 × 10 ⁻⁹ torr or less, and the transition metals (Ni, Co, etc.) of the intermetallic compound layer are covered.
Is grown in one atomic layer, and then the intermetallic compound layer is grown.

The growth temperature of the intermetallic compound layer is usually
About 350 ° C for E growth, 450 ° C for MBE growth
Do about. However, there is an example in which the MEE is grown at a growth temperature of about 250 ° C. in the lattice-matched intermetallic compound layer.

Conversely, when a group III-V compound semiconductor layer is grown next to the intermetallic compound layer, after growing the intermetallic compound layer, one atomic layer of transition metal (Ni, Co, etc.) is grown (transition metal). Termination). If the intermetallic compound layer is lattice-mismatched, then 100 ° C. to suppress three-dimensional growth
After growing a III-V (or II-VI) compound semiconductor layer to a thickness of several nm by MEE at a low temperature,
At a growth temperature of around 50 ° C (or around 300 ° C),
III-V (or II-VI) compound semiconductor layer
EE growth. If the intermetallic compound layer is a lattice matching system, the subsequent growth may be performed by MBE growth at a growth temperature of about 450 ° C.

FIG. 2A is a sectional view showing the structure of the second embodiment of the present invention. In the figure, a structure according to a second embodiment of the invention comprises a NiIn _0.24 Al _0.76 bulk layer 5,
p-In _0.53 Ga _0.47 As barrier layers (hereinafter referred to as barrier layer) 6 and NiIn _0.24 Al _0.76 well layers (hereinafter referred to as the well layer) 7 formed by combining alternately p-type superlattice structure, p ⁺ -In _0.53 Ga _0.47 As contact layer 8,
This is a superlattice structure on an InP substrate having a structure in which p-In _0.53 Ga _0.47 As semiconductor layers 9 are sequentially laminated. still,
A structure in which the above growth layers are stacked in the reverse order is also possible.

That is, the structure according to the second embodiment of the present invention is a superlattice structure lattice-matched on an InP substrate of an intermetallic compound layer / p-type superlattice structure / p-type semiconductor .

FIG. 2 (b) is a band structure diagram of FIG. 2 (a). In the figure, the well level is determined with respect to the vacuum level of the well layer 7 and the energy level of the conduction band 11 and the valence band 13 of the barrier layer 6 or the effective mass of the hole 17 in the well layer 7 and the barrier layer 6. The thickness of the barrier layer 6 and the thickness of the barrier layer 6 are designed so that the transmission hole wave 15 reinforces the phase. Thereby, ohmic contact between the metal layer and the p-type semiconductor layer can be realized.

FIG. 3A is a sectional view showing the structure of the third embodiment of the present invention. In the figure, a structure according to a third embodiment of the present invention is an n-In _0.53 Ga _0.47 As semiconductor layer 1.
, An n ⁺ -In _0.53 Ga _0.47 As contact layer 2, an n-type superlattice structure in which a well layer 3 and a barrier layer 4 are alternately combined, a NiIn _0.24 Al _0.76 bulk layer 5, a barrier layer 6 and a well A p-type superlattice structure in which layers 7 are alternately combined, and ap ⁺ -In _0.53 Ga _0.47 As contact layer 8
And a p-In _0.53 Ga _0.47 As semiconductor layer 9 in this order.
Note that a structure in which the above-described growth layers are stacked in the reverse order is also possible.

That is, the structure according to the third embodiment of the present invention is lattice-matched to the n-type semiconductor / n-type superlattice structure / intermetallic compound layer / p-type superlattice structure / p-type semiconductor InP substrate. It is a super lattice structure .

FIG. 3 (b) is a band structure diagram of FIG. 3 (a). In the figure, the vacuum level of the well layer 3 and the energy level of the conduction band 11 and the valence band 13 of the barrier layer 4 or the effective mass of the electrons 16 in the well layer 3 and the barrier layer 4 are compared with the well layer. The thickness of the barrier layer 4 and the thickness of the barrier layer 4 are designed so that the transmitted electron wave 14 strengthens the phase.

Similarly, with respect to the vacuum level of well layer 7 and the energy level of conduction band 11 and valence band 13 of barrier layer 6 or the effective mass of hole 17 in well layer 7 and barrier layer 6. The thickness of the well layer 7 and the barrier layer 6
The transmission hole wave 15 is designed to reinforce the phase. As a result, serial connection of the n-type semiconductor layer and the p-type semiconductor layer via the intermetallic compound layer can be realized.

The fourth embodiment of the present invention is directed to a superlattice structure according to the third embodiment of the present invention described above.
_0.24 Al _0.76 intermetallic compound layer and n-type In _0.53 Ga _0.47
A superlattice structure having a structure in which an n-type In _0.52 Al _0.48 As semiconductor layer having a thickness of 10 atomic layers or less is inserted between As semiconductor layers, or a NiIn _0.24 Al _0.76 intermetallic compound layer and a p-type A p-type In _0.52 Al _0.48 A having a thickness of 10 atomic layers or less between the In _0.53 Ga _0.47 As semiconductor layer.
A superlattice structure having a structure in which an s-semiconductor layer is inserted and having a structure in which at least one semiconductor layer adjacent to an intermetallic compound layer is composed of a plurality of semiconductor layers having different band gaps.

That is, in the structure according to the fourth embodiment of the present invention, the type of the group III atom contained in the intermetallic compound layer is the same, and the type of the group III-V compound semiconductor layer lattice-matched to the semiconductor substrate is the same. A superlattice structure having an intermetallic compound layer interposed therebetween .

The fifth embodiment of the present invention relates to the superlattice structure according to the fourth embodiment of the present invention, wherein the NiIn
_0.24 Al _0.76 intermetallic compound layer and n-type In _0.52 Al _0.48
A superlattice structure having a structure in which an n-type In _0.24 Al _0.76 As semiconductor layer having a thickness of 10 atomic layers or less is inserted between As semiconductor layers, or a NiIn _0.24 Al _0.76 intermetallic compound layer and a p-type A p-type In _0.24 Al _0.76 A having a thickness of 10 atomic layers or less between the In _0.52 Al _0.48 As semiconductor layer.
A superlattice structure having a structure in which an s-semiconductor layer is inserted and having a structure in which at least one semiconductor layer adjacent to an intermetallic compound layer is composed of a plurality of semiconductor layers having different band gaps.

That is, in the structure according to the fifth embodiment of the present invention, the III-V compound semiconductor layer in which the type of group III atoms contained in the intermetallic compound layer and the composition ratio of the group III atoms are the same. And a superlattice structure having the intermetallic compound layer interposed therebetween .

FIG. 4A is a sectional view showing the structure of the sixth embodiment of the present invention. In the figure, the structure according to the sixth embodiment of the present invention is an n-In _0.53 Ga _0.47 As semiconductor layer 5.
1, an n ⁺ -In _x Ga ₁ -x As strain compensating contact layer (X ≧ 0.6) 52, a Ni _0.5 Al _0.5 well layer 53
And n-In _Y Ga _1-Y As barrier layer (Y ≧ 0.6) 5
4 is alternately combined with an n-type superlattice structure, and Ni _0.5
It has a structure in which an Al _0.5 intermetallic compound layer 55 is sequentially laminated. Note that a structure in which the above-described growth layers are stacked in the reverse order is also possible.

However, the Ni _0.5 Al _0.5 intermetallic compound layer 5
5 is a layer thickness within the critical film thickness .

FIG. 4B is a band structure diagram of FIG. 4A. In the figure, a Ni _0.5 Al _0.5 well layer (−1.
6% tensile strain) (hereinafter referred to as a well layer) 53 and n-I
The superlattice structure with the n _Y Ga _1-Y As barrier layer (compressive strain) (hereinafter referred to as a barrier layer) 54 is a layer of the well layer 53 and the barrier layer 54 such that the transmitted electron waves 14 strengthen the phase. The thickness is designed.

FIG. 4C is a strain distribution diagram of FIG. 4A. In the figure, in the superlattice structure according to the sixth embodiment of the present invention, the product of the thickness of the well layer 53 and the absolute value of the tensile strain is equal to the product of the thickness of the barrier layer 54 and the compressive strain. As described above (strain compensation condition), the amount of compressive strain or the In composition Y of the barrier layer 54 is determined.

However, the band gap of the barrier layer 54 is I
Since the thickness of the well layer 53 and the barrier layer 54 and the In composition Y of the barrier layer 54 depend on the n composition Y, the condition that the transmitted electron wave 14 strengthens the phase and the condition of the strain compensation are simultaneously satisfied. It has been decided to meet.

Similarly, the n ⁺ -In _x Ga ₁ -x As strain compensating contact layer 52 is composed of the Ni _0.5 Al _0.5 intermetallic compound layer 5.
5 has a composition X and a film thickness determined so as not to exceed the critical film thickness.

As described above, even when the intermetallic compound layer has a crystal lattice mismatch with the semiconductor substrate, by applying the opposite strain to the combined semiconductor layer and compensating the strain, the entire superlattice structure can be compensated. The amount of strain can be made negligibly small in epitaxial growth.

When compressive strain is applied to the n ⁺ -In _x Ga ₁ -x As strain compensating contact layer 52 and the barrier layer 54, the band gap becomes smaller than when no strain is applied, and the Schottky barrier is reduced. Ohmic contact between the semiconductor layer and the intermetallic compound layer is easily realized.

FIG. 5A is a sectional view showing the structure of the seventh embodiment of the present invention. In the figure, the structure according to the seventh embodiment of the present invention is a p-In _0.53 Ga _0.47 As semiconductor layer 6.
1, ap ⁺ -In _x Ga ₁ -x As strain compensation contact layer (X ≧ 0.6) 62, a Ni _0.5 Al _0.5 well layer (hereinafter referred to as a well layer) 63 and p-In _Y Ga _1-Y As
Barrier layer (Y ≧ 0.6) (hereinafter referred to as barrier layer) 64
And p-type superlattice structure formed by combining alternately, Ni _0.5 A
l has sequentially laminated structure and _0.5 intermetallic compound layer 65. Note that a structure in which the above-described growth layers are stacked in the reverse order is also possible.

However, the Ni _0.5 Al _0.5 intermetallic compound layer 6
5 is a layer thickness within the critical film thickness .

FIG. 5B is a band structure diagram of FIG. 5A. In the figure, the well layer (-1.6% tensile strain) 6
The layer thickness of the well layer 63 and the barrier layer 64 is designed so that the transmission hole wave 15 reinforces the phase of the superlattice structure including the barrier layer 3 and the barrier layer (compression strain) 64.

FIG. 5C is a strain distribution diagram of FIG. 5A. In the figure, in the superlattice structure according to the seventh embodiment of the present invention, the product of the thickness of the well layer 63 and the absolute value of the tensile strain is equal to the product of the thickness of the barrier layer 64 and the compressive strain. The amount of compressive strain or the In composition Y of the barrier layer 64 is determined as described above (strain compensation condition).

However, the band gap of the barrier layer 64 is I
Since the thickness of the well layer 63 and the barrier layer 64 and the In composition Y of the barrier layer 64 depend on the n composition Y, the condition that the transmission hole wave 15 reinforces the phase and the condition of the strain compensation are simultaneously satisfied. It has been decided to meet.

Similarly, the p ⁺ -In _x Ga ₁ -x As strain compensating contact layer 62 is composed of the Ni _0.5 Al _0.5 intermetallic compound layer 6.
5 has a composition X and a film thickness determined so as not to exceed the critical film thickness.

The eighth embodiment of the present invention is directed to a superlattice structure according to the seventh embodiment of the present invention, wherein the Ni _0.5 A
The l _0.5 intermetallic compound layer 65 NiIn _0.24 Al _0.76 intermetallic compound layer which is lattice matched to the InP substrate, p ⁺ -In _X
The Ga _1-x As strain compensation contact layer 62 is formed by p ⁺ -In _0.53
It has a structure replaced with a Ga _0.47 As semiconductor layer, and
NiIn _0.24 Al _0.76 and Co lattice-matched with nP substrate
A superlattice structure including a semiconductor layer having a lattice constant different from that of a semiconductor substrate for compensating for crystal lattice mismatch between an intermetallic compound layer made of any one of In _0.365 Al _0.635 and a semiconductor layer .

That is, the superlattice structure according to the eighth embodiment of the present invention is characterized in that a strained layer is used as the intermetallic compound well layer and a non-strained layer is used as the bulk intermetallic compound layer of the superlattice structure. And As a result, the amount of distortion of the superlattice structure can be reduced, so that the crystal quality is improved and the barrier layer 64 is improved.
When compressive strain is applied, the band gap is reduced as compared with the case where no strain is applied, and the Schottky barrier is reduced, so that ohmic contact between the semiconductor layer and the intermetallic compound layer is easily realized.

FIG. 6A is a sectional view showing the structure of the ninth embodiment of the present invention. In the figure, the structure according to the ninth embodiment of the present invention is an n-In _0.53 Ga _0.47 As semiconductor layer 7.
1 and n ⁺ -In _0.53 Ga _0.47 As contact layer 72
And NiIn _0.24 in which each layer thickness changes continuously with each other
Al _0.76 well layer (hereinafter referred to as well layer) 73 and n
A superlattice structure in which -In _0.53 Ga _0.47 As barrier layers (hereinafter referred to as barrier layers) 74 are alternately combined;
It has a structure in which n _0.24 Al _0.76 bulk layers 75 are sequentially laminated.

Incidentally, a structure in which the above-described growth layers are stacked in the reverse order is also possible .

FIG. 6B is a diagram showing changes in the thicknesses of the well layer 73 and the barrier layer 74 of the superlattice structure of FIG. 6A. In the superlattice structure according to the ninth embodiment of the present invention, the sum of the thicknesses of the adjacent well layer 73 and the barrier layer 74 is constant, and the thickness of the well layer 73 is changed to the thickness change line of the NiIn _0.24 Al _0.76 well layer. By continuously increasing along the line 76 and decreasing the thickness of the barrier layer 74 continuously along the layer thickness change line 77 of the n-In _0.53 Ga _0.47 As barrier layer,
It has a structure in which the thicknesses of the well layer 73 and the barrier layer 74 are continuously changed.

By using a superlattice structure having a structure in which the thickness of the intermetallic compound layer or the semiconductor layer is continuously changed, the energy band width of the transmitted carriers can be further increased, and the vicinity of the contact interface can be increased. The resistance of the layer can be reduced. Further, since the composition change from semiconductor to metal becomes smoother on average, there is also an effect of reducing the Schottky barrier at the interface.

FIG. 7A is a sectional view showing the structure of the tenth embodiment of the present invention, and FIG. 7B is a band structure diagram of FIG. 7A. In these figures, the tenth aspect of the present invention is shown.
The structure according to the embodiment of the present invention has n ⁺ GaAs 81 and n-Ga
As _Y P _{1 -Y} strain compensation contact layer (Y ≧ 0.6) (tensile strain) 82, n-AlAs spacer layer 83 and Co _0.5 A
l _0.5 well layers (compression strain) 84 and n-AlAs spacer layer 83 and the _{n-GaAs X} P _1-X barrier layer (X ≧ 0.6)
(Tensile strain) 85 are alternately combined, a superlattice structure, an AlAs spacer layer 83, and a Co _0.5 Al _0.5 layer (compressive strain) 86 are sequentially laminated.

It is to be noted that a structure in which the above-described growth layers are stacked in the reverse order is also possible.

That is, in the superlattice structure according to the tenth embodiment of the present invention, the semiconductor layer adjacent to the intermetallic compound (Co _0.5 Al _0.5 well layer 84) is formed of a plurality of semiconductor layers (n-AlAs) having different band gaps. Spacer layer 83, n-
It has a structure composed of a GaAs _X P _1-X barrier layer 85).

Moreover, the superlattice structure according to the tenth embodiment of the present invention is characterized by the condition that the phase of the transmitted wave of electrons is strengthened, the tensile strain layer (n-GaAs _X P _{1 -X} barrier layer 85) and the compressive strain. so as to satisfy the layer condition of the distortion compensation of the (Co _0.5 Al _0.5 well layer 84) at the same time, Co _0.5 Al _0.5 well layers 84
And n-GaAs _X P ₁ -x barrier layer 85 and n-AlA
The thickness of the s spacer layer 83 and the As composition ratio X of the n-GaAs _X P ₁ -x barrier layer 85 are determined, and have a structure in which strain is compensated so as not to exceed the critical film thickness. I have.

In the superlattice structure according to the tenth embodiment of the present invention, the Co _0.5 Al _0.5 well layer 84 and the n-GaAs
N-AlAs of several atomic layers between the _X P _1-X barrier layer 85
Since the spacer layer 83 is interposed therebetween, the growth of the C
o _0.5 Al _0.5 / AlAs hetero interface with GaAs _X P
_{A 1-X} / AlAs heterointerface is obtained. Also, nA
Since the lAs spacer layer 83 is substantially lattice-matched to the GaAs substrate, the interface between the tensile strain layer (n-GaAs _X P ₁ -x barrier layer 85) and the compressive strain layer (Co _0.5 Al _0.5 well layer 84). It has a function to mitigate sudden distortion change.

FIG. 8 is a sectional view showing the structure of the eleventh embodiment of the present invention. In the figure, the structure according to an eleventh embodiment of the present invention is a _{p-InP90, p-In 0.53} Ga
_0.47 As spacer layer 91, p ⁺ -In _x Ga ₁ -x As barrier layer (X ≧ 0.6) (compression strain) 92 and p-In _0.53 G
a _0.47 As semiconductor layer composed of As spacer layer 91 and N
iIn _0.24 Al _0.76 spacer layer 93 and Ni _0.5 Al _0.5
A superlattice structure in which intermetallic compound layers composed of well layers (tensile strain) 94 and NiIn _0.24 Al _0.76 spacer layers 93 are alternately combined; and a NiIn _0.24 Al _0.76 bulk layer 95
Are sequentially laminated.

It is to be noted that a structure in which the above-described growth layers are stacked in the reverse order is also possible .

That is, in the superlattice structure according to the eleventh embodiment of the present invention, the intermetallic compound layer is composed of a plurality of intermetallic compound layers (NiIn _0.24 Al
_0.76 spacer layer 93, Ni _0.5 Al _0.5 well layer 94)
It has the structure constituted by.

Moreover, in the superlattice structure according to the eleventh embodiment of the present invention, the condition that the phase of the transmitted wave of the hole is strengthened, the compression strain layer (p ⁺ -In _x Ga ₁ -x As barrier layer 92) and P ⁺ -In _x Ga ₁ -x A is set so as to simultaneously satisfy the conditions for strain compensation with the tensile strain layer (Ni _0.5 Al _0.5 well layer 94).
s barrier layer 92, Ni _0.5 Al _0.5 well layer 94, p−
In _0.53 Ga _0.47 As spacer layer 91, NiIn _0.24 A
l _0.76 spacer layer 93 thickness and p ⁺ -In _x Ga ₁ -x
The In barrier layer 92 has a structure in which the In composition ratio X is determined and the strain is compensated so as not to exceed the critical film thickness.

In the superlattice structure according to the eleventh embodiment of the present invention, the p ⁺ -In _x Ga ₁ -x As barrier layer 92 and the Ni
Between _0.5 Al _0.5 well layers 94, and the p-In _0.53 Ga _0.47 As spacer layer 91 is lattice-matched layer NiIn
Since the structure sandwiches the _0.24 Al _0.76 spacer layer 93, the interface between the semiconductor layer and the intermetallic compound layer is the interface between the semiconductor layer and the intermetallic compound layer that are both lattice-matched.

Further, in the superlattice structure according to the eleventh embodiment of the present invention, since the interface between the different crystal structures of the semiconductor layer and the intermetallic compound layer is lattice-matched, the quality of both crystals is improved. Furthermore, in addition to the resonance tunnel effect, p ⁺ −
Since a compression ratio is applied to the In _x Ga ₁ -x As barrier layer 92, the band gap is reduced from that when there is no distortion, and the Schottky barrier is reduced, so that the ohmic contact between the semiconductor layer and the intermetallic compound layer is reduced. It is easier to realize.

Further, the structure of the superlattice structure according to the eleventh embodiment of the present invention is a structure in which the strain is compensated so as not to exceed the critical film thickness, and the p-type lattice matching layer is formed.
In _0.53 Ga _0.47 As spacer layer 91 and NiIn _0.24
The Al _0.76 spacer layer 93 is formed of a compression strain layer (p ⁺ -In _x Ga).
_1-X As barrier layer 92) and tensile strained layer (Ni _0.5 Al _0.5
Since it has a function of alleviating a sudden change in strain at the interface with the well layer 94), deterioration of the crystal due to strain can be avoided.

FIG. 9 is a sectional view showing a structure of a semiconductor device according to a twelfth embodiment of the present invention. In the figure, a semiconductor device according to a twelfth embodiment of the present invention has an In electrode 100
, N-InP substrate 101, and n-InAlAs / n-
InP buffer layer 102 and n-Cd _0.52 Zn _0.48 Se
The lattice matching layer 103 and n-MgZnCdSe (0.4 μm
m composition) cladding layer 104 and n-MgZnCdSe
(0.5 μm composition) Guide layer 105 and un-Cd _0.52
Zn _0.48 Se active layer 106 and p-MgZnCdSe
(0.5 μm composition) Guide layer 107 and p-MgZnC
dSe (0.4 μm composition) cladding layer 108 and p ⁺ −
Cd _0.52 Zn _0.48 Se contact layer 109 and p-Cd
_0.52 Zn _0.48 Se / NiIn _0.24 Al _0.76 superlattice structure 110 and NiIn _0.24 Al _0.76 intermetallic compound layer 111
II-VI compound semiconductor laser device lattice-matched to an InP substrate formed by laminating an Au electrode 112 with an InP substrate. That is, the semiconductor device according to the twelfth embodiment of the present invention has the superlattice structure defined by the present invention between the semiconductor portion of the semiconductor device and the electrode.

However, p-Cd _0.52 Zn _0.48 Se / NiI
The n _0.24 Al _0.76 superlattice structure 110 is a superlattice structure of a p-type semiconductor and an intermetallic compound layer .

Hereinafter, an example of a method for fabricating a semiconductor device (LD) according to the twelfth embodiment of the present invention will be described. II
An n-InAlAs / n-InP buffer layer 1 is formed on an n-InP substrate 101 in a growth chamber for growing an IV group compound semiconductor.
Then, the wafer on which No. 02 has been grown is put into an MBE growth chamber for growing a II-VI compound semiconductor.

In the MBE growth chamber, n-Cd
_0.52 Zn _0.48 Se lattice matching layer 103 and n-MgZnC
dSe cladding layer 104, n-MgZnCdSe guide layer 105, un-Cd _0.52 Zn _0.48 Se active layer 10
6, p-MgZnCdSe guide layer 107, p-M
gZnCdSe cladding layer 108 and p-Cd _0.52 Zn
The structure of the II-VI compound semiconductor LD lattice-matched to the InP substrate composed of the _0.48 Se contact layer 109 is sequentially laminated.

Thereafter, the II-VI compound semiconductor LD
P-Cd _0.52 Zn _0.48 Se / NiIn _0.24
Al _0.76 superlattice structure 110 and NiIn _0.24 Al _0.76
The intermetallic compound layer 111 is grown.

This wafer is taken out of the MBE growth chamber,
An Au electrode 112 is mounted on the p side of the wafer by vapor deposition such as sputtering, and an In electrode 100 is mounted on the n side. The semiconductor device (LD) according to the twelfth embodiment of the present invention is manufactured by cleaving the wafer obtained in this manner to an appropriate size to expose a laser cavity surface and fusing it to a heat sink.

The structure of the main body of the II-VI compound semiconductor LD according to the twelfth embodiment of the present invention is different from that of the II-VI compound semiconductor LD other than the above-described II-VI compound semiconductor LD if the cladding layer is lattice-matched to the InP substrate. -Group VI compound semiconductor LD structure, or II
It may have an IV group semiconductor LD structure.

Although the semiconductor element according to the twelfth embodiment of the present invention uses an InP substrate, the semiconductor substrate is not limited to InP, but may be a GaAs substrate or an InAs substrate.
The present invention can be applied to a semiconductor on a semiconductor substrate such as an II-VI compound semiconductor substrate such as an IV group compound semiconductor substrate, a ZnSe substrate, or a Si substrate.

The thirteenth embodiment of the present invention relates to the superlattice structure 11 of the semiconductor device according to the twelfth embodiment of the present invention.
Instead of 0, p ⁺ -In _0.53 Ga _0.47 As contact layer and p-In _0.53 Ga _0.47 As / NiIn _0.24 Al
_This is a semiconductor laser device using a _0.76 superlattice structure.

P ⁺ -In _0.53 Ga _0.47 As contact layer and p-In _0.53 Ga _0.47 As / NiIn _0.24 Al _0.76
If the superlattice structure is grown by MEE at a low temperature of 300 ° C. or less in a growth chamber for growing a III-V compound semiconductor, II
-It can be laminated without damaging the growth layer of the group VI compound semiconductor LD.

Although the semiconductor barrier layer of the superlattice structure of the semiconductor device according to the thirteenth embodiment of the present invention uses a II-VI compound semiconductor, the III-V compound semiconductor uses a II-VI compound semiconductor. Since the Schottky barrier is lower than that of the group III compound semiconductor, ohmic contact is easily obtained.

FIG. 10 is a sectional view showing a structure of a semiconductor device according to a fourteenth embodiment of the present invention. In the figure, a semiconductor device according to a fourteenth embodiment of the present invention is a semiconductor device in which a superlattice structure according to the present invention and semiconductor devices having the same structure are alternately combined and stacked and integrated in a direction perpendicular to a semiconductor substrate. Here, the semiconductor device according to the fourteenth embodiment of the present invention is the semiconductor device defined in claim 13 of the claims.

That is, the semiconductor device according to the fourteenth embodiment of the present invention comprises an n-side electrode 120 and an n-InP substrate 121.
, N-InP buffer layer 122 and first LD 138
, Superlattice structure 139, second LD 140, p-I
n _0.53 Ga _0.47 As contact layer 128 and p ⁺ -In
_0.53 Ga _0.47 As contact layer 129 and p-side electrode 13
7 is a semiconductor LD.

The first LD 138 and the second LD 140 have the same structure, and include an n-InP cladding layer 123 and an n-I
an nGaAsP guide layer 124, an un-InGaAs active layer 125, a p-InGaAsP guide layer 126,
and a p-InP cladding layer 127.

FIG. 11 is a sectional view showing the structure of the superlattice structure 139 of FIG. In the figure, the superlattice structure 13
9 is a p-In _0.53 Ga _0.47 As contact layer 128;
p ⁺ -In _0.53 Ga _0.47 As contact layer 129 and N
iIn _0.24 Al _0.76 well layer 130 and p-In _0.53 G
a _0.47 As barrier layer 131, a superlattice structure alternately combined, a NiIn _0.24 Al _0.76 bulk layer 132,
-In _0.53 Ga _0.47 As barrier layer 133 and NiIn
_0.24 and Al _0.76 well layer 134 formed by combining alternately superlattice structure, n ⁺ -In _0.53 Ga _0.47 As contact layer 135. consisting superlattice structure [FIGS. 1 (a) to indicate a third of the present invention the same superlattice structure] superlattice structure according to the embodiment consists of _{n-in 0.53 Ga 0.47 as /} n-InP superlattice buffer layer 136..

In the semiconductor device according to the fifteenth embodiment of the present invention, the semiconductor device according to the fourteenth embodiment of the present invention includes a single LD and an arbitrary number of superlattice structures 139 (for example, k
), That is, an n-side electrode / n−
InP substrate / first LD / superlattice structure 139 / second LD
/ Superlattice structure 139 / third LD / superlattice structure 139
/ 4th LD /.../ superlattice structure 139 / kth LD /
This is a semiconductor LD element having a structure to be a p-side electrode.

In the semiconductor device according to the fourteenth embodiment of the present invention, two identical LDs are stacked in a direction perpendicular to the semiconductor substrate.
It is an integrated semiconductor LD device. However, since the superlattice structure 139 is lattice-matched to the n-InP substrate 121, it is possible to manufacture a semiconductor LD device in which an arbitrary number of LDs are stacked like the semiconductor device according to the fifteenth embodiment of the present invention. It is.

FIG. 12 is a sectional view showing a structure of a semiconductor device according to a sixteenth embodiment of the present invention. In the figure, a semiconductor device according to a sixteenth embodiment of the present invention is the same as the semiconductor device according to the fourteenth embodiment of the present invention shown in FIG. 10, except that the superlattice structure 139 is replaced by a strain-compensated superlattice structure 147. It is a semiconductor element, and the same components are denoted by the same reference numerals .

FIG. 13 is a sectional view showing the structure of the superlattice structure 147 of FIG. In the figure, the superlattice structure 14
7 is a p-In _0.53 Ga _0.47 As contact layer 128;
p ⁺ -In _0.53 Ga _0.47 As contact layer 129 and N
iAl well layer (tensile strain) 142 and p-In _x Ga
A superlattice structure in which _1-X As barrier layers (X ≧ 0.6) (compression strain) 143 are alternately combined, and NiIn _0.24 Al
_0.76 bulk layer (lattice matching layer) 144 and n-In _x Ga
A superlattice structure in which _1-X As barrier layers (X ≧ 0.6) (compression strain) 145 and NiAl well layers (tensile strain) 146 are alternately combined, and an n ⁺ -In _0.53 Ga _0.47 As contact layer 135 And a superlattice structure consisting of n-In _0.53
Ga _0.47 As / n-InP superlattice buffer layer 136.

The superlattice structure of the semiconductor device according to the sixteenth embodiment of the present invention comprises a superlattice structure according to the sixth embodiment of the present invention shown in FIG. 4A and a superlattice structure shown in FIG. FIG. 13 shows a superlattice structure obtained by combining the superlattice structure according to the seventh embodiment of the present invention as shown in FIG.

In the semiconductor device according to the seventeenth embodiment of the present invention, the LD and the superlattice structure 147 of the semiconductor device according to the sixteenth embodiment of the present invention are provided in an arbitrary number (for example, k
), That is, an n-side electrode / n−
InP substrate / first LD / superlattice structure 147 / second LD
/ Superlattice structure 147 / third LD / superlattice structure 147
/ 4th LD /.../ superlattice structure 147 / kth LD /
This is a semiconductor LD element having a structure to be a p-side electrode.

The semiconductor device according to the sixteenth embodiment of the present invention is a semiconductor LD device in which two identical LDs are stacked and integrated in a direction perpendicular to a semiconductor substrate. However, since the superlattice structure 147 has an average amount of strain of almost zero with respect to the n-InP substrate 121 due to the strain compensation structure, the first structure of the present invention
Like the semiconductor device according to the seventh embodiment, a semiconductor LD device in which an arbitrary number of LDs are stacked can be manufactured.

FIG. 14 is a sectional view showing the structure of a semiconductor device according to the eighteenth embodiment of the present invention. In the figure, a semiconductor device according to an eighteenth embodiment of the present invention is a semiconductor device in which at least one superlattice structure of a superlattice structure and a semiconductor device are alternately combined and stacked and integrated in a direction perpendicular to a semiconductor substrate. In the element, at least one of the stacked semiconductor elements has a different layer structure from at least one of the other semiconductor elements.

That is, the semiconductor device according to the eighteenth embodiment of the present invention comprises an n-side electrode 150 and an n-GaAs substrate 15.
1, the n-GaAs buffer layer 152, and the first LD 17
0, superlattice structure 171, second LD 172, p-
A semiconductor LD including a GaAs contact layer 158, a p ⁺ -GaAs contact layer 159, and a p-side electrode 169
It is.

The first LD 170 and the second LD 171 have the same structure, and have an n-Al _0.7 Ga _0.3 As cladding layer 1.
53, an n-Al _0.3 Ga _0.7 As guide layer 154,
InGaAs / GaAs DQW active layer (wavelength 0.98
μm) 155 and p-Al _0.3 Ga _0.7 As guide layer 1
56 and a p-Al _0.7 Ga _0.3 As clad layer 157.

InGaAs / GaAs DQW Active Layer 1
55 is n-GaAs (20 nm), i-GaAs (30
nm), In _0.2 Ga _0.8 As (8 nm) well layer, n
-GaAs barrier layer (14 nm), In _0.2 Ga _0.8 A
s (8 nm) well layer, i-GaAs (20 nm), p
-Double quantum well structure (DQW: Double Quantum Well) made of GaAs (30 nm)
And the oscillation wavelength is 0.98 μm.

FIG. 15 is a sectional view showing the structure of the superlattice structure 171 of FIG. In the figure, the superlattice structure 17
1 is a p-GaAs contact layer 158 and p ⁺ -GaAs
s contact layer 159, p ⁺ -GaAs _X P ₁ -x strain compensation contact layer (X ≧ 0.6) (tensile strain) 160, C
o _0.5 Al _0.5 well layer (compression strain) 161 and p-Ga
As _Y P _{1 -Y} barrier layer (Y ≧ 0.6) (tensile strain) 162
Super lattice structure formed by combining alternately body and Co _0.5 Al _0.5
A superlattice structure composed of alternating combinations of a bulk layer (compressive strain) 163, an n-GaAs _Y P _{1 -Y} barrier layer (tensile strain) 164 and a Co _0.5 Al _0.5 well layer (compressive strain) 165, and n ⁺ -GaAs _X P _1-X distortion compensation contact layer (tensile strain)
166, and an n-GaAs buffer layer 167. Here, the superlattice structure 1
Reference numeral 71 denotes a superlattice structure on a GaAs substrate .

[0145] 18 superlattice structure 171 of a semiconductor device according to an embodiment of the present invention, as a superlattice structure according to a tenth embodiment of the present invention shown in FIG. 7 (a), Co _0.5 A
between the _0.5 well layer 161 and the p-GaAs _Y P _{1 -Y} barrier layer 162 or between the n-GaAs _Y P _{1 -Y} barrier layer 164 and the Co _0.5 Al _0.5 well layer 165 It is also possible to use a superlattice structure having a structure in which a type or p-type AlAs spacer layer is inserted.

The semiconductor device according to the nineteenth embodiment of the present invention comprises an arbitrary number (for example, k) of a single LD of the semiconductor device and the superlattice structure 171 according to the eighteenth embodiment of the present invention.
), That is, an n-side electrode / n−
InP substrate / first LD / superlattice structure 171 / second LD
/ Superlattice structure 171 / third LD / superlattice structure 171
/ 4th LD /.../ superlattice structure 171 / kth LD /
This is a semiconductor LD element having a structure to be a p-side electrode.

In the semiconductor device according to the eighteenth embodiment of the present invention, two identical LDs are stacked in a direction perpendicular to the semiconductor substrate.
It is an integrated semiconductor LD device. However, the superlattice structure 171 has an n-GaAs substrate 15
Since the average amount of strain with respect to 1 is almost zero, it is possible to manufacture a semiconductor LD device in which an arbitrary number of LDs are stacked like the semiconductor device according to the nineteenth embodiment of the present invention.

The semiconductor device according to the twentieth embodiment of the present invention is the same as the above-described semiconductor LD device on a GaAs substrate according to the nineteenth embodiment of the present invention, except that the first LD is formed of AlGaAs.
System LD, the second LD is an AlGaInP system LD, the third LD is a ZnSe system LD, and each material system L
The LD having the structure of the active layer D is alternately laminated with the superlattice structure according to the present invention, and the oscillation wavelength is from 1 μm to 0.4 μm.
This is a multi-function or continuous-wave high-performance LD element that continuously covers a wide wavelength range up to. Here, the second aspect of the present invention
The semiconductor device according to the zeroth embodiment is the semiconductor device defined in claim 14 of the appended claims.

The semiconductor device according to the twenty-first embodiment of the present invention is a semiconductor LD device on an InP substrate such as an InGaAlAs LD or an InGaAsP LD, wherein the material of the active layer is made of InGaAs, InAsP of various compositions,
By changing to InGaAsP or InAs, and further changing the quantum well width, the LD in which the band structure of the quantum well active layer of the LD is changed is alternately laminated with the superlattice structure according to the present invention, and the oscillation wavelength is from 2 μm to 1 μm. Multi-wavelength or continuous wavelength high-performance LD element that continuously covers a wide wavelength range .

FIG. 16 is a sectional view showing a structure of a semiconductor device according to the twenty-second embodiment of the present invention. In the figure, a semiconductor device according to a twenty-second embodiment of the present invention is formed by alternately combining a superlattice structure according to the present invention and a high-resistance semiconductor layer or a semiconductor device and laminating and integrating them in a direction perpendicular to a semiconductor substrate. In the semiconductor device, the layer structure of at least one of the constituent semiconductor devices is different from that of at least one of the other semiconductor devices, and at least one of the stacked semiconductor devices is electrically connected. Is a semiconductor element having a structure for independent driving.

That is, the semiconductor device according to the twenty-second embodiment of the present invention comprises an n-side electrode (first LD) 180 and an n-In
A P substrate 181, a first LD 205, a first superlattice structure 206, an InAlAs insulating layer 190, a second superlattice structure 207, an n-InGaAs / n-InP superlattice buffer layer 195, and a second LD 208. , P-In _0.53 G
a _0.47 As contact layer 201 and p ⁺ -In _0.53 Ga
_0.47 As contact layer 202 and p-side electrode (second LD)
203, a first LD 205
And a second LD 208. The semiconductor LD element includes a p-side electrode (first LD) 204 and an n-side electrode (second LD) 192 for independently driving the second LD 208 and the second LD 208.

The first LD 205 is the n-InP cladding layer 1
82, n-InGaAsP guide layer 183, and InG
aAsP / InGaAsP-MQW (multiple quantum well) active layer (wavelength: 1.3 μm) 184 and p-InGaAsP
This is a semiconductor LD including a guide layer 185 and a p-InP clad layer 186.

The second LD 208 is the n-InP cladding layer 1
96, n-InGaAsP guide layer 197, and InG
aAsP / InGaAsP-MQW (multiple quantum well) active layer (wavelength 1.55 μm) 198 and p-InGaAs
The semiconductor LD includes a P guide layer 199 and a p-InP clad layer 200.

The first superlattice structure 206 has p ⁺ -In _0.53
Ga _0.47 As contact layer 187 and NiIn _0.24 Al
_0.76 / p-In _0.53 Ga _0.47 As superlattice layer 188 and N
This is a p-type superlattice structure [a p-type superlattice structure according to the second embodiment of the present invention shown in FIG. 2A] composed of an iIn _0.24 Al _0.76 bulk layer 189.

The second superlattice structure 207 is made of NiIn _0.24 A
l _0.76 / n-In _0.53 Ga _0.47 As superlattice layer 193;
An n-type superlattice structure comprising an n ⁺ -In _0.53 Ga _0.47 As contact layer 194 [the first embodiment of the present invention shown in FIG.
N-type superlattice structure according to Example 1).

[0156]

As described above, by using the superlattice structure of the present invention, an ohmic contact between a metal layer and an n-type semiconductor layer or between a metal layer and a p-type semiconductor layer can be realized. .

The metal electrode layer of the present invention is a high-quality epitaxial layer, and uses a superlattice structure composed of a lattice-matched intermetallic compound layer and a semiconductor layer. Therefore, the problem of ohmic contact between III-V and II-VI semiconductor light emitting devices is improved, and III-V and II-VI semiconductor LEDs (Light Emitting Diodes) are improved.
Alternatively, the reliability of a light emitting element such as an LD can be greatly improved.

Further, by using the structure of the n-type superlattice structure / intermetallic compound layer / p-type superlattice structure of the present invention, the n-type semiconductor layer and the p-type semiconductor layer via the intermetallic compound layer are provided. Can be connected in series. Therefore, it is possible to realize a semiconductor light-emitting integrated device in which the superlattice structure of the present invention and a plurality of light-emitting devices that can be epitaxially grown on the same substrate are alternately stacked and electrically electrically connected in series. As a result, it is possible to achieve a higher output, a larger wavelength, and a wider wavelength band of the semiconductor laser than ever before.

The semiconductor laser device according to the present invention does not require the trouble and difficulty of the conventional method of attaching an LD by soldering, and a plurality of lasers can be integrated more than before, so that a higher laser output can be achieved. Can be achieved. In addition, since the beam interval is narrow, the light can be directly incident on the fiber using a rod lens or the like, so that a multiplexer is not required and the loss between the light source and the fiber can be reduced.

Further, since the number of lasers is reduced, their mounting is simplified and the number of external control circuits is reduced. In addition, since the laser has a simple structure, a complicated etching process accompanying the device is not required, and the number of steps is small because of batch growth, so that it is suitable for mass production and cost reduction is possible.

Multi-wavelength LD that can be driven independently according to the present invention
Has an advantage that the light emitting regions of the upper LD and the lower LD are aligned because the current flows uniformly inside each LD element as compared with the conventional example. Therefore, multi-wavelength laser light can be easily introduced into one optical fiber, and wavelength multiplexing optical communication can be easily realized.

The superlattice structure according to the present invention enables a serial connection of a plurality of semiconductor light emitting elements, light receiving elements, optical devices such as modulators, and electronic devices such as transistors, which can be grown on the same substrate. As a result, the functions of the optical device, the electronic device, and the optoelectronic device can be enhanced.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view showing a configuration of a first embodiment of the present invention, and FIG. 1B is a band structure diagram of FIG.

FIG. 2A is a sectional view showing a configuration of a second embodiment of the present invention, and FIG. 2B is a band structure diagram of FIG.

FIG. 3A is a cross-sectional view illustrating a configuration of a third embodiment of the present invention, and FIG. 3B is a band structure diagram of FIG.

FIG. 4A is a sectional view showing a configuration of a sixth embodiment of the present invention, FIG. 4B is a band structure diagram of FIG. 4A, and FIG.
FIG. 4 is a strain distribution diagram of FIG.

5A is a sectional view showing a configuration of a seventh embodiment of the present invention, FIG. 5B is a band structure diagram of FIG. 5A, and FIG. 5C is a diagram of FIG.
FIG. 4 is a strain distribution diagram of FIG.

FIG. 6A is a cross-sectional view illustrating a configuration of a ninth embodiment of the present invention, and FIG. 6B is a view illustrating changes in the thicknesses of a well layer and a barrier layer of the superlattice structure of FIG. is there.

FIG. 7A is a cross-sectional view showing a configuration of a tenth embodiment of the present invention, and FIG. 7B is a band structure diagram of FIG.

FIG. 8 is a sectional view showing a configuration of an eleventh embodiment of the present invention.

FIG. 9 is a sectional view showing a configuration of a semiconductor device according to a twelfth embodiment of the present invention.

FIG. 10 is a sectional view showing a configuration of a semiconductor device according to a fourteenth embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a configuration of the superlattice structure of FIG.

FIG. 12 is a sectional view showing a configuration of a semiconductor device according to a sixteenth embodiment of the present invention.

FIG. 13 is a cross-sectional view showing the configuration of the superlattice structure of FIG.

FIG. 14 is a sectional view showing a configuration of a semiconductor device according to an eighteenth embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a configuration of the superlattice structure of FIG.

FIG. 16 is a sectional view showing a configuration of a semiconductor device according to a twenty-second embodiment of the present invention.

17A is a cross-sectional view showing a configuration of a conventional example, and FIG.
FIG. 3A is a band structure diagram of FIG.

FIG. 18 is a diagram showing a band structure near a semiconductor / electrode interface of a semiconductor light emitting device using a conventional semiconductor superlattice structure.

FIG. 19 is a diagram showing a sectional layer structure diagram and a current-voltage characteristic of a conventional semiconductor device having an intermetallic compound layer.

FIG. 20 is a diagram showing the structure of a conventional two-stage stacked semiconductor laser.

FIG. 21 is a sectional view showing the structure of a conventional two-wavelength semiconductor laser.

22A is a diagram showing the lattice constant of an intermetallic compound and a semiconductor substrate, and FIG. 22B is a diagram showing the degree of lattice mismatch between the intermetallic compound and the semiconductor substrate.

FIG. 23 is a diagram showing an atomic arrangement of a NiAl / AlAs hetero interface.

[Explanation of symbols]

Reference Signs List 1 n-In _0.53 Ga _0.47 As semiconductor layer 2 n ⁺ -In _0.53 Ga _0.47 As contact layer 3 NiIn _0.24 Al _0.76 well layer 4 n-In _0.53 Ga _0.47 As barrier layer 5 NiIn _0.24 Al _0.76 bulk layer 6 p-In _0.53 Ga _0.47 As barrier layer 7 NiIn _0.24 Al _0.76 well layer 8 p ⁺ -In _0.53 Ga _0.47 As contact layer 9 p-In _0.53 Ga _0.47 As semiconductor layer 11 conduction band 12 Fermi level 13 valence band 14 transmitted electron wave 15 transmission hole Wave 16 Electron 17 Hole 19 Carrier Resonant Tunneling Effect 51 n-In _0.53 Ga _0.47 As Semiconductor Layer 52 n ⁺ -In _X Ga ₁ -x As Strain Compensation Contact Layer 53 Ni _0.5 Al _0.5 Well Layer 54 n- In _Y Ga _1-Y As barrier layer 55 Ni _0.5 Al _0.5 intermetallic compound layer 61 p-In _0.53 Ga _0.47 As semiconductor layer 6 ^{_{p + -In X Ga 1-X}} As distortion compensation contact layer 63 Ni _0. 5 Al _0. 5 well layer _{64 p-In Y Ga 1-} Y As barrier layer 65 Ni _0.5 Al _0.5 intermetallic compound layer 71 n-an In _0.53 Ga _0.47 As semiconductor layer 72 n ⁺ -In _0.53 Ga _0.47 As contact layer 73 NiIn _0.24 Al _0.76 well layer 74 n-In _0.53 Ga _0.47 As barrier layer 75 NiIn _0.24 Al _0.76 bulk layer 76 NiIn _0.24 Al _0.76 well layer the thickness change line 77 n-in _0.53 Ga _0.47 As barrier layers in the layer thickness change line ^{81 n + GaAs 82 n-GaAs} Y P 1-Y distortion compensation contact layer (tensile strain) 83 n-AlAs spacer layer 84 Co _0.5 Al _0.5 well layer (compressive _{strain) 85 n-GaAs X P 1} -X barrier layer (tensile strain) 86 Co _0.5 Al _0.5-layer (compressive strain) 90 p-InP 91 p- In 0.53 Ga 0.47 s spacer layer ^{_{92 p + -In X Ga 1-}} X As barrier layer (compressive strain) 93 NiIn _0.24 Al _0.76 spacer layer 94 Ni _0.5 Al _0.5 well layers (tensile strain) 95 NiIn _0.24 Al _0.76 bulk layer 100 an In electrode 101 n -InP substrate 102 n-InAlAs / n-InP buffer layer 103 n-Cd _0.52 Zn _0.48 Se lattice matching layer 104 n-MgZnCdSe (0.4 μm composition) cladding layer 105 n-MgZnCdSe (0.5 μm composition) guide layer 106 un -Cd _0.52 Zn _0.48 Se active layer 107 p-MgZnCdSe (0.5 μm composition) guide layer 108 p-MgZnCdSe (0.4 μm composition) cladding layer 109 p-Cd _0.52 Zn _0.48 Se contact layer 110 p-Cd _0.52 Zn _0.48 Se / NiIn _0.24 Al
_0.76 superlattice structure 111 NiIn _0.24 Al _0.76 intermetallic compound layer 112 Au electrode 120 n-side electrode 121 n-InP substrate 122 n-InP buffer layer 123 n-InP cladding layer 124 n-InGaAsP guide layer 125 InGaAs active layer 126 p -InGaAsP guide layer 127 p-InP cladding layer 128 p-In _0.53 Ga _0.47 s contact layer 129 p ⁺ -In _0.53 Ga _0.47 As contact layer 130 NiIn _0.24 Al _0.76 well layer 131 p-In _0.53 Ga _0.47 As barrier layer 132 NiIn _0.24 Al _0.76 bulk layer 133 n-In _0.53 Ga _0.47 As barrier layer 134 NiIn _0.24 Al _0.76 well layer 135 n ⁺ -In _0.53 Ga _0.47 As contact layer 136 n-In _0.53 Ga _0.47 As / n-InP superlattice buffer 137 p Side power Pole 138 First LD 139 Superlattice structure 140 Second LD 142 NiAl well layer (tensile strain) 143 p-In _x Ga ₁ -x As barrier layer (compressive strain) 144 NiIn _0.24 Al _0.76 bulk layer (lattice matching layer) 145 n -In _x Ga ₁ -x As barrier layer (compressive strain) 146 NiAl well layer (tensile strain) 147 Superlattice structure 150 n-side electrode 151 n-GaAs substrate 152 n-GaAs buffer layer 153 n-Al _0.7 Ga _0.3 As Cladding layer 154 n-Al _0.3 Ga _0.7 As guide layer 155 InGaAs / GaAs DQW active layer (wavelength 0.98 μm) 156 p-Al _0.3 Ga _0.7 As guide layer 157 p-Al _0.7 Ga _0.3 As clad layer 158 p-GaAs contact layer 159 p ⁺ -GaAs contact layer ^{_{160 p + -GaAs X P 1-}} X distortion compensation co Contact layer (tensile strain) 161 Co _0.5 Al _0.5 well layers (compression _{strain) 162 p-GaAs Y P 1} -Y barrier layer (tensile strain) 163 Co _0.5 Al _0.5 bulk layer (compressive strain) 164 n-GaAs _Y P _{1 -Y} barrier layer (tensile strain) 165 Co _0.5 Al _0.5 well layers (compression ^{_{strain) 166 n + -GaAs X P 1}} -X distortion compensation contact layer (tensile strain) 167 n-GaAs buffer 169 p-side electrode 170 first 1LD 171 Superlattice structure 172 Second LD 180 n-side electrode (first LD) 181 n-InP substrate 182 n-InP cladding layer 183 n-InGaAsP guide layer 184 InGaAsP / InGaAsP multiple quantum well active layer 185 p-InGaAsP guide layer 186 p- InP cladding layer 187 p ⁺ -In _0.53 Ga _0.47 As contact layer 188 NiIn _0.24 A _0.76 / p-In _0.53 Ga _0.47
As superlattice layer 189 NiIn _0.24 Al _0.76 bulk layer 190 InAlAs insulating layer 191 NiIn _0.24 Al _0.76 intermetallic compound layer 192 n-side electrode (second LD) 193 NiIn _0.24 Al _0.76 / n-In _0.53 Ga _0.47
As superlattice layer 194 n ⁺ -In _0.53 Ga _0.47 As contact layer 195 n-InGaAs / n-InP superlattice buffer layer 196 n-InP clad layer 197 n-InGaAsP guide layer 198 InGaAsP / InGaAsP multiple quantum well active layer 199 p -InGaAsP guide layer 200 p-InP cladding layer 201 p-In0.53Ga0.47As contact layer 202 p ⁺ -In0.53Ga0.47As contact layer 203 p-side electrode (second LD) 204 p-side electrode (first LD) 205 first LD 206 First superlattice structure 207 Second superlattice structure 208 Second LD

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-314852 (JP, A) JP-A-6-298595 (JP, A) JP-A-6-283807 (JP, A) 183614 (JP, A) JP-A-6-350198 (JP, A) JP-A-6-283806 (JP, A) 1994 (Heisei 6) The 55th Autumn Meeting of the Japan Society of Applied Physics 19p-MK-17p . 207 Appl. Phys. Lett. 61 [26] (1992) p. 3160−3162

Claims (12)

(57) [Claims] An intermetallic compound crystal and a semiconductor crystal are alternately combined, and the thickness of the intermetallic compound layer composed of the intermetallic compound crystal and the semiconductor layer composed of the semiconductor crystal, and the vacuum level of the intermetallic compound layer When, a superlattice structure in which one of the transmitted wave energy of the conduction band and the valence band level and the incident electrons or holes configured constructively the phase of said semiconductor layer
Wherein the superlattice structure comprises a semiconductor layer and the intermetallic
Between the thick film of the compound crystal and the intermetallic compound
Characterized by the fact that the thick crystal film is lattice-matched with the semiconductor substrate.
The structure to do. 2. The structure of claim 1 , wherein said semiconductor is
Structure a semiconductor layer conductivity type consisting of a body crystal is characterized in that as one of the n-type or p-type. 3. The conductivity type superlattice structure according to claim 1 comprising an n-type semiconductor layer of, 請 conductivity type including a p-type semiconductor layer of
Motomeko 1 superlattice structure according, characterized in that it is arranged across the thick film of the intermetallic compound crystal structure
Body . 4. The structure according to claim 3 , wherein said semiconductor is
The substrate is an InP substrate, and lattice-matched with the InP substrate.
The intermetallic compound is NiIn _0.24 Al _0.76 or CoIn
Structure which is characterized in that either _0.365 Al _0.635
Structure . 5. The structure according to claim 3 , wherein the semiconductor is
The body substrate is an InAs substrate, and the InAs substrate and the lattice
The matching intermetallic compound is NiIn _0.71 Al _0.29 or Co
It is characterized in that either an In _0.835 Al _0.165
Structure . 6. A superlattice structure according to claim 1,
Zotai is structure characterized by having a progressively variable is not structured at least one of the layer thickness of the intermetallic compound layer or the semiconductor layer. 7. The superlattice structure according to claim 1,
Structure Zotai is characterized by having a structure composed of a plurality of semiconductor layers having different band gaps of the semiconductor layer adjacent to the intermetallic compound layer. 8. The superlattice structure according to claim 1,
The structure has at least one of its composition and constituent elements described above.
Structure characterized by having the structure composed of a plurality of intermetallic compound layer different from the thick film of the intermetallic compound crystal. 9. A semiconductor device comprising the structure according to claim 1 between a semiconductor portion and an electrode of the semiconductor device. 10. A structure according to any one of claims 1 to 8.
And a semiconductor element alternately combined and stacked and integrated in a direction perpendicular to the semiconductor substrate. 11. A structure according to any one of claims 1 to 8.
And a semiconductor element alternately combined and stacked and integrated in a direction perpendicular to the semiconductor substrate, wherein the stacked
A semiconductor element, wherein a layer structure of at least one of the integrated semiconductor elements is different from a layer structure of another semiconductor element. 12. A structure according to any one of claims 1 to 8.
When, a one and a semiconductor device obtained by laminating and stacking in a direction perpendicular to the semiconductor substrate in combination with alternating semiconductor layers and a semiconductor element of high resistance of the semiconductor element in which the laminated-integrated, at least one semiconductor element Unlike the layer structure and layer structure of another semiconductor device, and the semiconductor layer of the high resistance
Therefore, the semiconductor element has a structure in which the semiconductor element is electrically driven independently.