JP3137106B2 - Method and apparatus for evaluating bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for evaluating a bipolar transistor, and more particularly to a method for evaluating a bipolar transistor which is excellent in high speed and high output.

[0002]

2. Description of the Related Art Bipolar transistors are excellent in high speed and high output, and in recent years, research and development of bipolar transistors using not only Si but also a compound semiconductor such as GaAs have been actively conducted. As an index of the high speed of such a bipolar transistor, the current gain cutoff frequency f _T
(Hereinafter, simply referred to as f _T) has a parameter called,
Approximately expressed by the following equation (1), a high-speed transistor as f _T is large.

[0003]

(Equation 3) Here, k is Boltzmann's constant, T is absolute temperature, q is electron charge, I _C is collector current, C _BE is emitter-base junction capacitance, C _BC is base-collector junction capacitance, R _E
Is the emitter parasitic resistance, R _C is the collector parasitic resistance, τ _B
Is the base transit time and τ _C is the collector space charge region transit time.

[0004] In recent years, bipolar transistors have been applied to mobile communication devices such as mobile phones, so that high-speed operation with low power consumption is required. Here, under low power consumption, that is, low collector current I
Under _C , (kT / qI _{C in} the denominator of equation (1)
) (C _BE + C _BC ) dominates.

In addition, since the base-collector is normally used with a reverse bias and the thickness of the depletion layer is long, C _BE is generally
Large enough compared to _BC . For this reason, f _T , which is an index of the high-speed performance of the bipolar transistor, has an emitter-emitter under low power consumption, that is, under a low collector current I _C.
It can be seen that it largely depends on the base junction capacitance C _BE . Therefore, it is very important to evaluate the emitter-base junction capacitance of a bipolar transistor quickly, simply, and accurately in order to determine its high speed.

A method of evaluating the emitter-base junction capacitance of a bipolar transistor, which is generally performed conventionally, will be described. FIG. 8 is a flowchart of a conventional evaluation method.
Shown in First, an emitter-base diode for evaluating the emitter-base junction capacitance is designed and manufactured separately from the bipolar transistor in the same wafer as the bipolar transistor (steps S11 and S12).

[0007] The value of the emitter-base junction capacitance of a bipolar transistor is usually on the order of 100 fF, which is very small. Therefore, in order to improve the accuracy of capacitance measurement, usually, a diode having a large area whose capacitance value is on the order of 1 pF is designed and manufactured. For this reason, a large area is occupied on the wafer.

FIG. 9 is a sectional view showing the evaluation diode. In FIG. 9, 4 is a base layer, 5 is an emitter layer, 7b is a base electrode, 7e is an emitter electrode, and 8 is an insulating layer. After completion of the fabrication, when the capacitance of the diode is measured (CV measurement) separately from the evaluation of the characteristics of the transistor itself (step S13), a capacitance-voltage characteristic as shown in FIG. 10 is obtained. In the bipolar transistor, the emitter-base is biased in the forward direction, so that the base-emitter voltage V _{BE in} the forward direction may be measured.

Finally, the area is converted from the capacitance value measured using this diode (step S14), and the value of the emitter-base junction capacitance at the desired base-emitter voltage V _BE is determined (step S15). . At this time, since the area generally does not match the mask design value due to side etching or the like at the time of fabrication, it is necessary to accurately determine the area in advance using a microscope or the like.

[0010]

A problem with the above prior art is that a diode for capacity evaluation occupies a large area on a wafer, in addition to a bipolar transistor. As a result, it is disadvantageous for mass production of bipolar transistors. Furthermore, labor and time are required for designing and manufacturing a diode for capacity evaluation.

An object of the present invention is to improve the productivity by simply and accurately evaluating the emitter-base junction capacitance, which is an important device parameter for determining the high speed of a bipolar transistor, without using a diode for capacitance evaluation. To provide a method and apparatus that leads to

[0012]

According to Means for Solving the Problems] The present invention includes the steps of measuring the DC current gain beta _0, the imaginary part X _0pt optimum source impedance of high frequency noise at the emitter differential resistance r _e and frequency f of the bipolar transistor, Using these measured values, the emitter-base junction capacitance C
And a step of calculating and evaluating the _BE .

The imaginary part X _0PT of the optimum source impedance of the noise is _obtained at a frequency equal to or less than ５ of the cutoff frequency of the bipolar transistor.

Further, according to the present invention, the DC current gain beta ₀ of bipolar transistors, means for measuring the imaginary part X _0pt optimum source impedance of high frequency noise at the emitter differential resistance r _e and the frequency f, which like measurements And a means for calculating and evaluating the emitter-base junction capacitance C _BE by using the above method.

The operation of the present invention will be described. Evaluate the noise characteristics and DC characteristics of the bipolar transistor and use the relational expression that exists between each parameter of the imaginary part of the optimum source impedance of the noise, DC current gain, emitter differential resistance and the emitter-base junction capacitance to evaluate the characteristics. This is to calculate and evaluate the emitter-base junction capacitance.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the principle of the present invention will be described using mathematical expressions. A relational expression between the imaginary part of the optimum source impedance, the DC current gain, the emitter differential resistance, and the emitter-base junction capacitance used in the present invention and a method for evaluating the emitter-base junction capacitance using this relational expression will be described.

As shown in the equivalent circuit of FIG. 11, as a noise model of a bipolar transistor, a noise model of a bipolar transistor by Hawkins, "by Hawkins,
Solid State Electronics, 1977
Year, Volume 20, p. 191 (SOLIDSTATE ELECTRONICS, VOL.
20, pp. 191, 1977) ”to which the effects of the emitter parasitic resistance R _EE , the collector parasitic resistance R _C, and the collector resistance r _C are added. As noise sources inside the device, thermal noise sources 18 to 20 due to each parasitic resistance in FIG. 11 and shot noises 21 and 21 at the emitter junction and the collector junction are shown.
2 is assumed.

Here, since noise in a high frequency band is considered, 1 / f noise and burst noise, which are low frequency noises, are ignored. From this equivalent circuit, a method for deriving a noise figure for a two-port device is described in "Rote, Proceeding I.R.E. Magazine, 1956, 44, 8
Calculation based on page 11 (PROCEEDING IRE, VOL.44, pp.811,1956) shows that the optimum source impedance Z which is the source impedance when the minimum noise figure is given.
_OPT (Z _OPT = R _OPT + jX _OPT : hereinafter, simply referred to as an optimum source impedance) is expressed as follows.

[0019]

(Equation 4) Here, α is a grounded base current gain, and α ₀ is its DC component. r _e is the emitter differential resistance, n in the formula (8)
Represents the n value of the collector current. F _α is the cutoff frequency of the current transmission rate (hereinafter simply referred to as cutoff frequency).

Here, the aforementioned (3) representing the imaginary part X _OPT of the optimum source impedance of the bipolar transistor
The approximation is performed focusing on the equation. At a frequency f in a high frequency region of 1/5 or less of the cutoff frequency of the bipolar transistor, the above-mentioned f _α ² ,
f _e ² is sufficiently larger than f ² . Therefore, Α in equation (4) and α in equation (5) can be approximated as A = α ₀ / (1−α ₀ ) = 1 / β ₀ α = α ₀ , respectively. As a result, equation (3) can be written as:

[0021]

(Equation 5) Thus, at frequencies in the high-frequency region of 1/5 or less of the cutoff frequency, the imaginary part _XOPT of the optimum source impedance of the bipolar transistor is represented by the frequency f, the emitter-base junction capacitance C _BE , the DC current gain β _0, and the emitter differential resistance it can be seen that determined only by the r _e. Conversely,
The imaginary part X _OPT optimum source impedance, the DC current gain beta ₀ and emitter differential resistance r measured in _e by performing the following using equations emitter-base junction capacitance C _BE
Can be evaluated.

[0022]

(Equation 6) FIG. 1 shows a flowchart of a method for evaluating the emitter-base junction capacitance of a bipolar transistor according to the present invention. First,
Noise is measured at a frequency in a high-frequency region equal to or lower than 1/5 of the cut-off frequency of the bipolar transistor to determine an imaginary part of the optimum source impedance. In general, the noise figure of a two-port device can be expressed as:

[0023]

(Equation 7) Therefore, four or more source impedances Z _s = R _s
Against + jX _s, measured noise figure F, formula (10)
, All the noise parameters (minimum noise figure F _min , optimal source impedance Z _OPT = R _OPT + jX _OPT , equivalent noise resistance R _n ) can be determined. This measurement is performed at a frequency in a high frequency band equal to or less than 1/5 of the cutoff frequency of the bipolar transistor.

Next, by performing DC measurements, determines the emitter differential resistance r _e and the DC current gain beta _0. The DC current gain β ₀ is expressed as follows.

Β ₀ = I _C / I _B (11) Therefore, the collector current I _{C is obtained} under the required bias.
And it may be measured base current I _B. Further, in order to obtain the emitter differential resistance r _e from the equation (8),
It is necessary to find the n value of the collector current. The collector current can be written as:

I _C = I ₀ exp (qV _BE / nkT) (12) Therefore, the emitter-base voltage V as shown in FIG.
_It is determined from the slope of the so-called Gummel plot in which the logarithmic value of _BE and the current are plotted.

As described above, by evaluating the noise characteristics and the DC characteristics, the imaginary part of the optimum source impedance, the DC current gain and the emitter differential resistance are determined, and between these parameters and the emitter-base junction capacitance. The emitter-base junction capacitance of the bipolar transistor can be evaluated using the simple relational expression (9b) that holds. This equation base-emitter collector current I _C which depends on the voltage V _BE contains in the form of emitter differential resistance r _e, as shown in the equation (8), the emitter-base junction capacitance of the bias dependency accurate Can be evaluated.

[0028]

Embodiments of the present invention will be described below.
The present invention relates to a GaAs heterojunction bipolar transistor.
(Hereinafter referred to as HBT)
You. The sample used was AlGaAs / GaAs HBT.
You. FIG. 2 shows a cross-sectional view thereof. This AlGaAs / Ga
As HBT is a collector contour made of n-type GaAs.
2 (500 nm, dopant Si: 3 × 10¹⁸/
cm^Three ), N-type GaAs (460 nm, dopant S
i: 5 × 10¹⁶/ Cm^Three ), The collector layer 3, p
Layer 4 of GaAs (80 nm, dopant
C: 4 × 10 ¹⁶/ Cm^Three ), N-type AlGaAs
Emitter layer 5 (220 nm, dopant Si: 3 × 1
0¹⁷/ Cm^Three ), N-type GaAs (120 nm, dopa)
Account Si: 5 × 10¹⁸/ Cm^Three ) And n-type InGaAs
s (100 nm, dopant Si: 2 × 10¹⁹/ Cm^Three 
 ) Is formed from the emitter contact layer 6
You.

With respect to this HBT, 2 μm × 20 μm ×
3 fingers (hereinafter referred to as sample 1) and 4 μm × 20
μm (hereinafter referred to as sample 2) emitter size element
I thought. In this sample, the bias range measured this time
(Emitter-collector voltage V_CE= 2V, base EMI
Voltage V_BEIs 1.25 V to 1.34 V), τ
_B + Τ_C Is about 3 ps, so the cutoff frequency is 50
It is about GHz. From this, the emitter-base junction capacitance
The above-mentioned expression (9) for evaluating the quantity value is satisfied.
A frequency less than or equal to 1/5 of the cutoff frequency
For this purpose, a frequency of about 1 to 2 GHz (this frequency band is
Performing noise measurement in the L band is sufficient.
It is.

Therefore, this time, noise measurement for evaluating the emitter-base junction capacitance was performed at a frequency of 2 GHz. First, the results of the noise measurement will be described. Figure 3 shows a frequency of 2GH
The optimum source impedance measured at z is shown on a Smith chart. Here, the emitter
The emitter-collector voltage that does not affect the base junction capacitance is fixed at V _CE = 2 V, and is 1.25 V to 1.34 V
Up to several base-emitter voltages V _BE .

Next, the results of the DC measurement will be described. Figure 4 is the base-collector current I _C and base current I _B of the sample 1
FIG. 7 is a diagram showing the dependence of the emitter voltage V _BE (Gummel plot). The measurement was performed with the emitter-collector voltage V _CE fixed at 2 V as in the case of the noise measurement. Thus, the DC current gain β ₀ and the n value were evaluated. In the range of the base-emitter voltage V _BE measured this time, I _C was in a linear region, and the value of n was 1.1 in both samples when evaluated based on equation (11). In this from the bias value to determine the emitter differential resistance r _e from the equation (8).

Further, the DC current gain β ₀ was obtained based on the equation (11) under the required bias. For example, β ₀
In the value V _BE = 1.30 V, the sample 1 91 (I _C
= 2.1 mA), the sample 2 100 (I _C = 1.4m
A).

Based on the imaginary part of the optimum source impedance, the DC current gain, and the emitter differential resistance obtained above, the emitter-base junction capacitance was obtained by using equation (9b). FIG. 5 is a diagram in which the emitter-base junction capacitance value obtained by the present method is plotted with respect to the samples 1 and 2 with respect to the forward base-emitter voltage V _BE . Samples 1 and 2 have the same epi structure, and Sample 1 is 1.5 times smaller than Sample 2.
It has twice the emitter area. For this reason, the emitter-base junction capacitance for the same base-emitter voltage V _BE should be 1.5 times that of sample 1 than that of sample 2. The result of FIG. 5 well reproduces this relationship.

The results of FIG.
It is a value that substantially matches the emitter-base junction capacitance value evaluated by fabricating the base diode, and there is no problem in accuracy. Since the value of the emitter-base junction capacitance of a bipolar transistor is usually very small, on the order of 100 fF, a diode having a large area such that the capacitance value is on the order of 1 pF is designed in the conventional capacitance measurement.
Had to be made. For this reason, a large area is occupied on the wafer.

However, in this method, since the diode for capacity evaluation does not occupy a large area on the wafer,
This is advantageous for improving productivity. For example, in the past, a diode for capacity evaluation occupied about 5% of the area of each shot on the wafer, but by using this evaluation method, a bipolar transistor can be manufactured in this area as well. Thus, the usage rate on the wafer could be improved by about 5%. Also,
This eliminates the need for designing and fabricating a diode for capacity evaluation, leading to a reduction in the time required for fabricating and evaluating a bipolar transistor.

In the above, the embodiment of the method for evaluating the emitter-base junction capacitance of the present invention has been described with respect to a GaAs heterojunction bipolar transistor. Of course, the emitter and base junction capacitance of the present invention is also applicable to a Si bipolar transistor and an InP heterojunction bipolar transistor. The method for evaluating the base junction capacitance may be performed.

FIG. 6 shows a device configuration for implementing the method for evaluating the emitter-base junction capacitance of a bipolar transistor according to the present invention. This evaluation device includes a device under test 9, a variable source impedance (tuner) 1
0, a noise source 11, a noise meter 12, a DC power supply 13, a switch 14, a control device 15, a computer 16, and a display 17. Measurement system is variable source impedance 1
0, a noise measurement line including a noise source 11 and a noise meter 12, and two lines for DC measurement.

A series of operations described below are performed by the controller 1
5 in a controlled and automated manner. First, the noise of the bipolar transistor of the device under test 9 is measured at a frequency in a high frequency band equal to or less than 1/5 of the cutoff frequency of the bipolar transistor. FIG. 7 shows a flowchart of the noise measurement. A bias is applied from the DC power supply 13 between the base and the emitter and between the collector and the base (step S
4). Then, the variable source impedance 10 is adjusted to change the source impedance value Z _S, and the noise figure F for four or more source impedance values is measured (step S5).

The measurement data is sent to the computer 15, where fitting is performed by using the equation (10) expressing the noise figure F as a function of the source impedance Z _S ,
The optimum source impedance of the noise is derived (step S6). This is repeated for the range of the base-emitter voltage for which the emitter-base junction capacitance is to be obtained. At this time, since the collector-base voltage does not affect the emitter-base junction capacitance, it may be fixed at a constant value.

Next, switching to a line for DC measurement,
The collector current and the base current of the bipolar transistor of the device under test 9 are measured while changing the base-emitter voltage from the DC power supply 13. The measurement data is calculated by computer 16
Is sent to the formula (11) and the ₀ and n value DC current gain β on the basis of (12) is calculated, further emitter differential resistance r _e of n values based on the equation (8) is calculated. In addition,
Either the noise measurement or the DC measurement may be performed first.

In the computer 16, a calculation is performed based on the equation (9b) using the imaginary part of the optimum source impedance, the DC current gain and the emitter differential resistance derived as described above, and the emitter-base junction capacitance is determined. The display of the analysis result is output to a display 17 connected to the computer 16.

[0042]

As described above, according to the present invention,
By simply performing noise measurement and DC measurement and performing calculations based on equation (9b), it is possible to easily and accurately evaluate the emitter-base junction capacitance, which is an important device parameter that determines the high speed of a bipolar transistor. There is an effect that can be. In the method of the present invention, a diode having a large area for capacity evaluation does not occupy a large area on a wafer unlike the conventional method for evaluating the emitter-base junction capacity of a bipolar transistor. Is expected to be mass-produced, and productivity improvement of about 5% or more is expected. In addition, the trouble of designing and manufacturing a diode for capacity evaluation can be omitted, which leads to a reduction in time for manufacturing and evaluating a bipolar transistor.

[Brief description of the drawings]

FIG. 1 is a flowchart of an emitter-base junction capacitance evaluation method according to the present invention.

FIG. 2 is a structural sectional view of a heterojunction bipolar transistor used in the embodiment of the present invention.

FIG. 3 is a Smith chart showing measurement results of optimal source impedances of samples 1 and 2.

FIG. 4 is a diagram showing the dependence of the collector current and the base current of Sample 1 on the base-emitter voltage.

FIG. 5 is a diagram showing the results of evaluation of the emitter-base junction capacitance of samples 1 and 2 according to the present invention.

FIG. 6 is a diagram illustrating the configuration of an apparatus for evaluating an emitter-base junction capacitance of a bipolar transistor according to an embodiment of the present invention.

FIG. 7 is a flowchart illustrating a method of noise measurement.

FIG. 8 is a flowchart of an emitter-base junction capacitance evaluation method according to a conventional method.

FIG. 9 is a cross-sectional view of an emitter-base diode for capacitance evaluation used in an emitter-base junction capacitance evaluation according to a conventional method.

FIG. 10 is a diagram showing a result of capacitance measurement (CV measurement) of an emitter-base diode.

FIG. 11 is a diagram showing an equivalent circuit of a bipolar transistor including a noise source.

FIG. 12 is a diagram showing a method for obtaining an n value from a DC measurement (Gummel plot) of a bipolar transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semi-insulating substrate 2 Collector contact layer 3 Collector layer 4 Base layer 5 Emitter layer 6 Emitter contact layer 7b Base electrode 7c Collector electrode 7e Emitter electrode 8 External base selective growth layer 9 Device under test 10 Variable source impedance 11 Noise source 12 Noise Meter 13 DC power supply 14 Switch 15 Control device 16 Computer 17 Display

Claims (6)

(57) [Claims] 1. A DC current gain beta ₀ of the bipolar transistor, the imaginary part of the optimal source impedance of the high frequency noise in the emitter differential resistance r _e and frequency f X _0pt
And a step of calculating and evaluating the emitter-base junction capacitance C _BE using these measured values. 2. The formula for calculating the emitter-base junction capacitance is: 2. The method for evaluating a bipolar transistor according to claim 1, wherein: 3. The method for evaluating a bipolar transistor according to claim 1, wherein the imaginary part X _0PT of the optimum source impedance of the noise is _obtained at a frequency equal to or less than ５ of a cutoff frequency of the bipolar transistor. 4. A DC current gain beta ₀ of the bipolar transistor, the imaginary part of the optimal source impedance of the high frequency noise in the emitter differential resistance r _e and frequency f X _0pt
And a means for calculating and evaluating the emitter-base junction capacitance C _BE using these measured values. 5. The formula for calculating the emitter-base junction capacitance is: The evaluation device for a bipolar transistor according to claim 4, wherein: 6. The evaluation device for a bipolar transistor according to claim 4, wherein the imaginary part X _0PT of the optimum source impedance of the noise is _obtained at a frequency equal to or less than ５ of a cutoff frequency of the bipolar transistor.