JP3134398B2 - Variable length coding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable-length coding circuit used for a high-efficiency coding apparatus of an image signal, for example.

[0002]

2. Description of the Related Art As shown in FIGS. 4 and 5, a conventional variable length coding circuit has a variable length code code for a coding input and a coding table for outputting the code length thereof. A code is input to a shifter, a control amount of the shifter is obtained by accumulating a code length, an output of the shifter is input to a register via a gate circuit, and an output of the shifter is fed back to the gate circuit. In the circuit having this configuration, the maximum operation speed is determined by the operation limits of the components such as the encoding table, the barrel shifter, and the adder, and the speed cannot be further increased.

FIGS. 6 and 7 show examples in which the speed is increased by parallelizing the circuits based on the variable length coding circuits shown in FIGS. 4 and 5. FIG. The data is alternately written into the FIFO for each predetermined number of coded inputs, and read from each FIFO at half the speed at the time of writing, and input to the variable length coding circuits in FIGS. 4 and 5, respectively. The output of each variable length coding circuit is again written to and read from the FIFO at twice the speed, and are alternately synthesized. However, in this method, as shown in FIGS. 6 and 7, two variable-length code outputs cannot be joined without excess or deficiency, so that there is a disadvantage that dummy data is inserted and transmission efficiency is reduced.

[0004]

The problems to be solved are that the conventional circuit cannot attain a high speed and has a drawback that the transmission efficiency is reduced.

[0005]

According to a first aspect of the present invention, an input data sequence is sequentially parallelized and alternately distributed.
Divided, the parallelism and distribution et respective data sequence was that have code conversion table and the code length table for variable length coding, the code conversion table output is fed to the shifter, respectively, the code length output shift amount Variable length code between parallel data supplied to the calculation circuit is connected without excess or shortage
In this manner, the shifter is controlled as described above, and each shifter output is stored in the register again through a gate circuit for register output.

A second means according to the present invention has a register for adding and accumulating the code length of each stage, and a subtraction circuit for correcting the shift amount from the output of the accumulation register. When the output is greater than or equal to 0, the output of the subtraction circuit is selected and used as the shifter control amount of the first stage, and the sum of the shifter control amount of the first stage and the code length up to the (R-1) th stage is calculated. A variable-length encoding circuit having a configuration in which the register output is written to a buffer and the feedback register to the gate circuit is switched when the subtraction result becomes 0 or more as the first-stage shifter control amount.

[0007]

[Action] According to this, it is possible to provide a high-speed variable-length coding circuit without inserting the dummy data.

[0008]

1 and 2 show an example of the basic configuration of the present invention. The coded input becomes a parallel signal for every two data in the serial / parallel conversion circuit 1 and is input to the coding tables 3 and 5, respectively. Each of the encoding tables 3 and 5 stores a variable-length code and its code length. The code is input to each of the shifters 6 and 7 and the output of the code length is used for calculating the shift amount. .

The shift amount calculating circuit adds the code lengths of the first and second stages (adders 8 and 9), and has a register 10 for accumulating the result. Is controlled by the sum of the output of the register 10 and the code length output of the first stage.
By this operation, the shift amount of the second-stage shifter 7 is always increased by the first-stage code length from the first-stage shifter 6, and the offset can be offset. That is, when the outputs of the first-stage and second-stage shifters 6 and 7 are combined by the gate circuits 11 to 14, the first-stage variable-length code and the second-stage variable-length code are connected clearly.

The principle of the present invention is to control the shifters 6 and 7 in this way so that variable length codes between parallel data can be connected without excess or deficiency. The outputs of the shifters 6 and 7 controlled in this way are the outputs of a group of registers 15 to 18 storing the outputs of the shifters 6 and 7 controlled in the same manner as before and the gate circuits 11 to 11.
The signals are combined at 14 and input to the registers 15 to 18 again.

1 and 2, when the effective variable length code for the group of registers 15 to 18 becomes 32 bits or more, that is, when the registers 15 and 16 become full, the contents of the variable length code are stored in the variable length code. And the gate circuits 11-1 from the registers 15-18.
4 is output to register 1 using MUXs 20 and 21.
Switch to 7 and 18.

The shifters 6 and 7 are controlled by feedback registers 15 to
The shift amount must be corrected due to the switching of the 18 outputs. This means that the cumulative result of the code length is corrected by switching the register. In this example, register 15
When the effective variable length code data of 32 bits or more is accumulated in the groups 18 to 18, the 32-bit data is stored in the buffer memory 19.
To the gate circuits 11 to 18 from the write registers 15 to 18
Although the feedback loop switching to 14 is performed, the write control to the buffer memory 19 and the feedback loop switching control are performed by the MSB of the code length accumulation register, and this MSB is excluded in the next shift amount calculation. The shift amount is corrected by adding and accumulating the lower bits with the next code length.

In the case of the examples of FIGS. 1 and 2, the serial-to-parallel conversion circuit 1 and thereafter operate at half the coding input speed, which is twice as large as the conventional example of FIGS. It can correspond to the speed input. Further, in the conventional examples shown in FIGS. 6 and 7, there is a drawback that dummy data may be inserted between variable-length codes. However, in the present invention, such dummy data is theoretically inserted. And there is no deterioration in transmission efficiency.

[0014] Thus, according to the above-described apparatus, in which it is possible to provide a high-speed variable length coding circuit without inserting a dummy de chromatography <br/> data.

Although FIGS. 1 and 2 show an example of a configuration in which two parallel circuits are used, it is generally possible to use n parallel circuits.
In this case, n stages of shifters capable of shifting by 2n times the maximum code length are prepared, and the feedback register after the gate circuit is also prepared by 2n times the maximum code length, and the effective data becomes 1/2 or more of the prepared feedback register. Then, the data is sequentially output to the buffer and the feedback register is switched.

Then, the n coded inputs are variable-length coded at a time and are connected by a gate circuit without excess or deficiency. As shown in FIG. 3, the shifter is controlled by a register output that accumulates the sum of the code lengths from the encoding tables of each stage and a subtraction circuit 22 that subtracts a fixed amount in order to correct the shift amount due to the feedback register switching. The output is appropriately switched by the MUX 23 to control the first-stage shifter, and the k-th stage shifter adds the code length up to the (k-1) -th stage to the first-stage shifter control amount. Control.

In FIGS. 1 and 2, since the shift amount was corrected to 64, it could be easily performed by ignoring the MSB. However, generally, a shift amount correcting circuit must be provided as shown in FIG. When the output of the shift amount correction circuit becomes 0 or more, the register output is buffered and the feedback register is switched, and the shifter control amount of the first stage is controlled by the output of the correction circuit.

[0018]

Effects of the Invention According to the present invention, it has become possible to provide a high-speed variable-length coding circuit without inserting the dummy data.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an example of a variable length encoding circuit according to the present invention.

FIG. 2 is a diagram for explaining this.

FIG. 3 is a diagram showing an example of a generalized variable length encoding circuit according to the present invention;

FIG. 4 is a configuration diagram of a conventional variable length encoding circuit.

FIG. 5 is a diagram for explaining this.

FIG. 6 is a configuration diagram of another conventional variable-length encoding circuit.

FIG. 7 is a diagram for explaining this.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Serial-parallel conversion circuit 3, 5 Coding table 6, 7 Shifter 8, 9 Adder 10 Register 11-14 Gate circuit 15-18 Register group 19 Buffer memory 20, 21 MUX

Claims (2)

(57) [Claims] 1. A with successively parallel input data sequence
Sorting alternately, the parallelism and distribution et respective data sequence was that have code conversion table and the code length table for variable length coding, the code conversion table output is fed to the shifter, respectively, the code length output The variable length code between parallel data supplied to the shift amount calculation circuit is
A variable-length encoding circuit configured to control the shifters so that they are connected to each other, and store the output of each shifter in this register again through a gate circuit with the register output. 2. A register for adding and accumulating the code length of each stage, and a subtraction circuit for correcting a shift amount from the output of the accumulation register, when the result is negative, outputs the accumulation register output.
If it is 0 or more, the output of the subtraction circuit is selected to be the shifter control amount of the first stage, and the shifter control amount of the first stage and the (R
-1) A variable configuration in which the sum of the code lengths up to the first stage is used as the shifter control amount of the first stage, and when the subtraction result becomes 0 or more, the register output is written into the buffer and the feedback register to the gate circuit is switched. Long encoding circuit.