JP3133179B2 - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JP3133179B2 JP3133179B2 JP04334926A JP33492692A JP3133179B2 JP 3133179 B2 JP3133179 B2 JP 3133179B2 JP 04334926 A JP04334926 A JP 04334926A JP 33492692 A JP33492692 A JP 33492692A JP 3133179 B2 JP3133179 B2 JP 3133179B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- chip
- gold plating
- layer
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Chemically Coating (AREA)
- Other Surface Treatments For Metallic Materials (AREA)
- Die Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体用パッケージに
関するもので、特にシリコン半導体チップのパッケージ
のマウントに当たりＡｕ−Ｓｉ共晶反応を利用する半導
体用パッケージに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to a semiconductor package utilizing an Au-Si eutectic reaction in mounting a package of a silicon semiconductor chip.
【０００２】[0002]
【従来の技術】従来半導体用パッケージは、通常基材の
メタライズ層にニッケルめっき又は銅めっきを施し、そ
の上に金めっきを施して構成される。上記ニッケルめっ
き又は銅めっきを下地とした半導体用パッケージは、チ
ップをパッケージヘダイボンディングした後のエイジン
グ処理の際に、下地のニッケルめっきや銅めっき或はメ
タライズ層が金めっき面に拡散してシリコンチップの剥
離やボンディング性の劣化が起こった。従って、コスト
高になるにもかかわらず金めっき層を通常４〜５μ等に
厚くすることが行われている。2. Description of the Related Art Conventionally, a semiconductor package is generally formed by applying a nickel plating or a copper plating to a metallized layer of a base material and then applying a gold plating thereon. In the case of a semiconductor package having the above-described nickel plating or copper plating as a base, when the chip is die-bonded to the package, during aging treatment, the base nickel plating or copper plating or metallization layer is diffused to the gold plating surface and the silicon chip is formed. Peeling and deterioration of bonding property occurred. Therefore, despite the increase in cost, the gold plating layer is usually thickened to 4 to 5 μm or the like.
【０００３】[0003]
【発明が解決しようとする課題】この発明は薄い金めっ
き層でも性能劣化が起こらないようにした半導体用パッ
ケージを提供するものである。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package in which performance degradation does not occur even with a thin gold plating layer.
【０００４】[0004]
【課題を解決するための手段】この発明はシリコン半導
体チップがＡｕ−Ｓｉ共晶反応でチップマウント部にマ
ウントされ、かつチップマウント部は表面に金めっき層
を有する半導体用パッケージにおいて、前記チップマウ
ント部の金めっき層の下地として厚み０．０１〜１０μ
のＦｅ含有量が重量比で０．１〜５０％のＮｉ−Ｆｅ合
金層を設けたことを特徴とする半導体用パッケージを提
供するものである。この発明は金属面上に金めっきが施
された半導体用パッケージに関するものであるが、適用
できる金属面としては特に制限がなく、通常の電子部品
を構成する金属、例えば銅，ニッケル，ニッケル合金，
アルミニウム等でよく、更にセラミック基板表面をタン
グステン，モリブデン等もしくはこれらの混合物を主体
とした材料でメタライジングしたものであっても良い。
Ｎｉ−Ｆｅ合金層はＦｅ含有量が重量比で０．０１〜５
０％で残部がＮｉであればその製作方法に制限がなく、
電気めっき，無電解めっき等のめっき方法や、蒸着，ス
パッタリング等でもかまわない。Ｎｉ−Ｆｅ合金層の厚
みは０．０１〜１０μであり、０．０５〜３μがより望
ましい。また、Ｎｉ−Ｆｅ合金層のＦｅ含有量は重量比
で０．３〜５０％が特に好ましい。Ｆｅ含有量が０．１
％より少なくなると耐熱性が悪くなり、かつ５０％より
多くなると密着強度が劣るようになる。このようなＮｉ
−Ｆｅ合金層を形成したならば公知の方法で厚み１．５
〜２μの金めっきを施せば十分である。According to the present invention, there is provided a semiconductor package in which a silicon semiconductor chip is mounted on a chip mount portion by an Au-Si eutectic reaction, and the chip mount portion has a gold plating layer on a surface thereof. 0.01-10μ thickness as a base of gold plating layer
And a semiconductor package provided with a Ni-Fe alloy layer having a Fe content of 0.1 to 50% by weight. The present invention relates to a semiconductor package in which a metal surface is plated with gold, but there is no particular limitation on a metal surface to which the metal can be applied.
Aluminum or the like may be used, and the surface of the ceramic substrate may be metallized with a material mainly containing tungsten, molybdenum, or a mixture thereof.
The Ni—Fe alloy layer has an Fe content of 0.01 to 5 by weight.
If 0% and the balance is Ni, there is no limitation on the manufacturing method,
A plating method such as electroplating or electroless plating, or vapor deposition or sputtering may be used. The thickness of the Ni—Fe alloy layer is 0.01 to 10 μm, and more preferably 0.05 to 3 μm. The Fe content of the Ni—Fe alloy layer is particularly preferably 0.3 to 50% by weight. Fe content is 0.1
%, The heat resistance deteriorates, and if it exceeds 50%, the adhesion strength becomes poor. Such Ni
-Once the Fe alloy layer has been formed, a thickness of 1.5
It is sufficient to apply ~ 2μ of gold plating.
【０００５】[0005]
【作用】以上のようにして製作したこの発明による半導
体用パッケージは金めっきが従来品より薄くても従来品
と同様な性能を得ることができる。その理由は従来品は
下地として例えばニッケルめっきを施した場合ニッケル
の金への拡散があると想像されるが、この発明によれば
下地としてＮｉ−Ｆｅ合金層があり鉄を含んでいるた
め、金への下地層からの拡散が大幅に抑制され、金めっ
き層の純粋性が保たれるからではないかと推察される。The semiconductor package according to the present invention manufactured as described above can obtain the same performance as the conventional product even if the gold plating is thinner than the conventional product. The reason is presumed to be that the conventional product has a diffusion of nickel into gold when the base is plated with nickel, for example, but according to the present invention, the base has a Ni-Fe alloy layer and contains iron, It is speculated that diffusion of gold from the underlayer is greatly suppressed, and the purity of the gold plating layer is maintained.
【０００６】[0006]
【実施例】以下この発明の実施例について説明する。タ
ングステンを主体とするメタライズ印刷された標準的な
セラミックパッケージに、ワット浴によりニッケルを５
〜７μ、その上に日本高純度化学株式会社から市販され
ているＮｉ−Ｆｅめっき液によりＮｉ−Ｆｅ合金層をＦ
ｅ含有率０．５％で１μめっきして金めっきの下地とし
た。次に日本高純度化学株式会社からテンペレジストＥ
Ｘ（商標）として市販されている金めっき液により厚み
１．５μの金めっきを施した実施例１の製品を５個製作
した。また、比較例１としてＮｉ−Ｆｅ合金層がなくそ
の他は実施例１と同様にしたものを５個製作した。Embodiments of the present invention will be described below. In a standard metallized printed ceramic package consisting mainly of tungsten, nickel
Μ7 μm, and the Ni—Fe alloy layer was further coated with a Ni—Fe plating solution commercially available from Nippon Kojundo Chemical Co., Ltd.
1 μm was plated at an e content of 0.5% to provide a base for gold plating. Next, Temperaresist E from Japan High Purity Chemical Co., Ltd.
Five products of Example 1 were plated with gold having a thickness of 1.5 μm using a gold plating solution commercially available as X (trademark). Further, as Comparative Example 1, five samples were manufactured in the same manner as in Example 1 except that there was no Ni—Fe alloy layer.
【０００７】実施例１と比較例１の各々に温度条件４５
０℃でチップをダイボンディングしてＡｕ−Ｓｉ共晶反
応でチップマウント部にマウントし、エージングテスト
として、３００℃で５８時間後のチップのプッシュプル
強度を測定し、チップの剥れの発生の有無を確認した。
その結果実施例１のものはプッシュプル強度が５６Ｋｇ
／ｃｍ2 以上であり、チップの剥れはなく良品と判断さ
れた。比較例１のものはプッシュプル強度がそれぞれ
７．３，１０．９，３．３，２．０，６．０Ｋｇ／ｃｍ
2 で何れも剥れが発生して不良品と判断された。[0007] Each of Example 1 and Comparative Example 1 had a temperature condition of 45.
The chip was die-bonded at 0 ° C., mounted on the chip mount by Au-Si eutectic reaction, and as an aging test, the push-pull strength of the chip was measured after 58 hours at 300 ° C. to prevent chip peeling. The presence or absence was checked.
As a result, Example 1 had a push-pull strength of 56 kg.
/ Cm 2 or more, and the chip was not peeled off. In Comparative Example 1, the push-pull strength was 7.3, 10.9, 3.3, 2.0, and 6.0 Kg / cm, respectively.
In both cases, peeling occurred and all were judged to be defective.
【０００８】[0008]
【発明の効果】この発明による半導体用パッケージは前
述したように金めっき層の下地にＮｉ−Ｆｅ合金層が形
成してあるから、良好な性能を維持しながら金めっき層
を薄くすることができて著しく安価になるという経済的
効果を有している。As described above, since the Ni-Fe alloy layer is formed under the gold plating layer in the semiconductor package according to the present invention, the gold plating layer can be thinned while maintaining good performance. Has the economic effect of being significantly cheaper.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/52 H01L 21/58 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/52 H01L 21/58
Claims (1)
反応でチップマウント部にマウントされ、かつチップマ
ウント部は表面に金めっき層を有する半導体用パッケー
ジにおいて、前記チップマウント部の金めっき層の下地
として厚み０．０１〜１０μのＦｅ含有量が重量比で
０．１〜５０％のＮｉ−Ｆｅ合金層を設けたことを特徴
とする半導体用パッケージ。In a semiconductor package having a silicon semiconductor chip mounted on a chip mount portion by an Au-Si eutectic reaction and a chip mount portion having a gold plating layer on a surface, a base of the gold plating layer of the chip mount portion is provided. A semiconductor package comprising a Ni—Fe alloy layer having a thickness of 0.01 to 10 μm and an Fe content of 0.1 to 50% by weight.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04334926A JP3133179B2 (en) | 1992-11-24 | 1992-11-24 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04334926A JP3133179B2 (en) | 1992-11-24 | 1992-11-24 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06163609A JPH06163609A (en) | 1994-06-10 |
| JP3133179B2 true JP3133179B2 (en) | 2001-02-05 |
Family
ID=18282790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04334926A Expired - Fee Related JP3133179B2 (en) | 1992-11-24 | 1992-11-24 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3133179B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002256444A (en) * | 2001-03-05 | 2002-09-11 | Okuno Chem Ind Co Ltd | Wiring board |
-
1992
- 1992-11-24 JP JP04334926A patent/JP3133179B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06163609A (en) | 1994-06-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |