JP3132446B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to the involvement in the production method of the semiconductor equipment, in particular, relates to a method of manufacturing a semiconductor equipment provided with a plug for connecting the upper and lower layers of the multilayer wiring.

[0002]

2. Description of the Related Art In a semiconductor device having a multilayer wiring,
Usually, a plug is formed at a portion connecting the upper layer wiring and the lower layer wiring. In the conventional plug making method, as shown in FIG. 21, after forming a lower wiring pattern 223, an interlayer insulating film 211 is deposited, and a via hole 221 reaching the lower wiring is opened by a normal exposure method and anisotropic etching. In this method, a metal such as tungsten or aluminum is buried in the via hole 221 by a chemical vapor deposition method or the like to form a plug 224.

In this method, when a position shift occurs with respect to a lower wiring pattern 223 in an exposure step at the time of opening the via hole 221, as shown in FIG.
In the anisotropic etching for opening the opening 21, the wiring pattern 2
The etching proceeds to the insulating film 202 in the lower layer 23 and the wiring or the Si substrate 201 in the lower layer, which causes a defect such as a short circuit of the wiring. For this reason, conventionally, the wiring portion connected to the via hole has been widened with allowance for misalignment. However, in recent miniaturized semiconductor integrated circuit devices, there is a tendency that there is no margin for misalignment in a portion of the wiring pattern that comes into contact with the via hole in order to increase the integration of the wiring pattern. Japanese Patent Application Laid-Open No. 7-326670 discloses a structure in which a cavity is provided between wirings for the purpose of reducing the capacitance between wirings. In this case, as shown in FIG. The cavities 230 formed therebetween are connected to each other, and when the chemical vapor deposition method is used for embedding the plug, the embedding material may enter the cavities 230 between the wirings, which may cause disconnection or short circuit due to improper embedding.

As a method of forming a connection plug for preventing such a defect due to misalignment, there is an example as disclosed in Japanese Patent Application Laid-Open No. 60-198846. In this example, as shown in FIGS. 25 and 26, after a wiring metal layer 304 made of aluminum is deposited, a tungsten layer 306 is continuously deposited, and a wiring pattern 323 is formed by a normal exposure method and anisotropic etching. Next, the resist used here is exposed again to leave only the resist 310 in the plug portion, and the plug 324 is formed by selective anisotropic etching of tungsten. According to this method, it is possible to form a plug for connecting the lower layer wiring and the upper layer wiring without causing a defect due to misalignment at the time of exposure of the lower layer wiring pattern and the plug pattern.

However, in the method of using tungsten, molybdenum, titanium, or the like for the plug as in this example, the resistance of the plug portion becomes high, and especially when a fine plug is used, it becomes difficult to speed up the circuit operation. Further, in such a structure, the electromigration resistance is deteriorated as compared with the case where aluminum is used for both the wiring material and the plug material.

An object of the present invention is to improve the drawbacks of the prior art described above, in particular, to provide a semiconductor equipment manufacturing method having a high density multilayer wiring reliable low resistance.
Another object of the present invention is to provide a method for manufacturing a semiconductor equipment having a small capacitance between the wiring patterns.

[0007]

Since the present invention SUMMARY OF] is to achieve the above object, basically, Ru der should be adopted technical construction as described below.

According to a first aspect of the method of manufacturing a semiconductor device according to the present invention, there is provided a method of manufacturing a semiconductor device in which a multilayer wiring of at least two or more layers is formed, wherein a first insulating film covering a semiconductor substrate is formed. A first step of depositing, a second step of depositing a first metal layer made of a refractory metal or a compound thereof on the first insulating film, and a step of depositing aluminum or an aluminum alloy on the first metal layer. Third depositing a second metal layer comprising
A fourth step of depositing a third metal layer on the second metal layer, and a fifth step of depositing a fourth metal layer made of aluminum or an aluminum alloy on the third metal layer Process and
A sixth step of depositing a fifth metal layer on the fourth metal layer, a seventh step of depositing a second insulating film on the fifth metal layer, and the second insulating film An eighth step of forming a photoresist pattern thereon, and patterning the second insulating film using the photoresist pattern, and using the patterned second insulating film as a mask, A ninth step of etching the fifth metal layer and the fourth metal layer to expose the third metal layer to form a connection plug, and a tenth step of oxidizing the patterned sidewalls of the fourth metal layer A step of forming a resist pattern for substantially covering the fourth metal layer and forming a desired wiring pattern; and forming the third metal layer and the second metal layer based on the resist pattern. First
12th step of forming a wiring pattern by etching the metal layer of
And a thirteenth step of depositing a second insulating film over the entire surface after removing the resist pattern, and a first step of polishing the surface of the second insulating film to expose the fifth metal layer.
And fourth step, Ru der those containing.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device according to the present invention has a structure in which at least two or more aluminum wiring layers are formed and an upper wiring layer and a lower wiring layer are connected by a connection plug. Since it is formed of aluminum or an aluminum alloy and an oxide layer is formed on the side wall of the connection plug, high-integration multilayer wiring is possible without increasing a margin for misalignment.
Since misalignment between the wiring pattern and the plug can be prevented, and aluminum or an aluminum alloy can be used for the plug, a semiconductor device having low resistance and high reliability can be realized.

In a semiconductor device having an air gap formed in an insulating film for covering a space between wirings for reducing a capacitance between wirings, when the insulating film is deposited, an aspect ratio of a cross section of a portion where the insulating film is deposited is at least one. Since the ratio of the thickness of the insulating film to the distance between the wirings is 1.5 or more, that is, 1.5 or more, a large air gap can be formed, and as a result, the capacitance between the wirings can be reliably reduced.

Further, in a semiconductor device in which an air gap for reducing the capacitance between wirings is formed in an insulating film covering between wirings, an insulating film is formed on the wirings along the wirings, and Since the film thickness is 30 to 60% of the film thickness of the aluminum film, a large air gap can be formed, and as a result, the capacitance between wirings can be reliably reduced.

[0012]

EXAMPLES Hereinafter, specific examples of the manufacturing method of the semiconductor equipment according to the present invention with reference to the drawings will be described in detail. FIG.
FIG. 7 to FIG. 7 are diagrams showing a first specific example of the present invention. In particular, a semiconductor in which at least two or more aluminum wiring layers are formed and an upper wiring layer and a lower wiring layer are connected by a connection plug. In the device, there is shown a semiconductor device in which the connection plug 24 is formed of aluminum or an aluminum alloy, and an oxide layer 9 is formed on a side wall of the connection plug 24.

According to a method of manufacturing a semiconductor device of the present invention, there is provided a semiconductor device in which at least two or more wiring layers are formed and an upper wiring layer and a lower wiring film are connected by a connection plug. Is formed, a semiconductor device is formed in which the connection between the lower layer wiring and the connection plug is formed in a self-aligned manner. Further, in the semiconductor device forming a multilayer wiring of at least two layers, the semiconductor device upper surface 1 is covered. A first step of forming a first insulating film 2, a second step of depositing a first metal layer 3 made of a refractory metal or a compound thereof on the first insulating film 2, A third step of depositing a second metal layer 4 made of aluminum or an aluminum alloy on the second metal layer 3, and a fourth step of depositing a third metal layer 5 on the second metal layer 4. , An aluminum layer on the third metal layer 5 Fourth metal layer made of an aluminum alloy 6
A fifth step of depositing a fifth metal layer on the fourth metal layer 6.
A sixth step of depositing a second metal layer 7, a seventh step of depositing a second insulating film 21 on the fifth metal layer 7, and a photoresist pattern 8 on the second insulating film 21. An eighth step of patterning the second insulating film 21 using the photoresist pattern 8; and using the patterned second insulating film 21 as a mask to form the fifth A ninth step of etching the metal layer 7 and the fourth metal layer 6 to expose the third metal layer 5 and form the connection plug 24, and oxidizing the side walls of the patterned fourth metal layer 6 A tenth step of forming a resist pattern 10 for substantially covering the fourth metal layer 6 and forming a desired wiring pattern 23;
And the third step based on the resist pattern 10.
A twelfth step of etching the metal layer 5, the second metal layer 4, and the first metal layer 3 to form the wiring pattern 23, and removing the resist pattern 10 to form the second insulating film 1
1 shows a method of manufacturing a semiconductor device including: a thirteenth step of depositing the first insulating film over the entire surface; and a fourteenth step of polishing the surface of the second insulating film 11 to expose the fifth metal layer 7. ing.

The present invention will be described more specifically.
On a semiconductor substrate 1 having an element region such as an S transistor, a first insulating film 2 covering the element region is formed to a thickness of about 0.8 to 1 μm.
Formed. After forming a connection port and a plug for connecting the element and the wiring layer, a first metal layer 3 made of titanium nitride or the like is formed to a thickness of 50 nm, and a second metal layer 4 made of aluminum or an aluminum alloy is formed to a thickness of 50 nm. The third metal layer 5 made of titanium nitride or the like is 100 nm, the fourth metal layer 6 made of aluminum or an aluminum alloy is 1000 nm, the fifth metal layer 7 made of titanium nitride or the like is 50 nm, and the mask oxide film 21 is formed. 200 nm is formed sequentially (FIG. 1). Next, a photoresist process is performed, and the mask oxide film 21 is etched by anisotropic dry etching while leaving the resist mask 8 in a portion to be a plug. For this etching, for example, an etchant containing CHF3 as a main component is used, and the etching is stopped at the fifth metal layer 7. This mask oxide film 21
Using the as a mask, the fifth and fourth metal layers 7 and 6 are etched by anisotropic dry etching to form plugs 24 (FIG. 2). The etching is stopped at the third metal layer 5 using an etchant containing Cl2 as a main component. Next, the side surface of the plug 24 is oxidized by anodic oxidation to form an oxide film, and the alumina layer 9 is formed (FIG. 3). Subsequently, a resist mask 10 of a wiring pattern is formed by a photoresist process (FIG. 4), and a third, second,
The first metal layer is etched by anisotropic dry etching to form a wiring pattern (FIG. 5). Note that in this case, the photoresist 10 has a misalignment L with respect to the plug 24.
Has occurred. The etching conditions are the same as those of the plug etching, but the plug 24 is prevented from being etched from the side wall when the wiring pattern is etched by the alumina layer 9 formed on the side wall of the plug 24. Thereafter, after removing the photoresist 10, a second insulating film 11 is deposited on the entire surface (FIG. 6), and the plug 24 is chemically and mechanically polished.
The second insulating film 11 is polished until the upper portion of the second insulating film 11 is exposed (FIG. 7).

The left side of FIG. 27 shows the resistance (shown by a black circle) and the yield (shown by a white circle) of a conventional plug in which a convex tungsten plug is formed on a lower wiring, and the center shows the resistance. The right side shows the resistance value and the yield of the conventional plug formed by embedding an aluminum plug, and the right side shows the resistance value and the yield of the plug of the present invention. As can be seen from this figure, a problem caused by misalignment between the wiring pattern and the plug is prevented without increasing a margin for misalignment, and a highly reliable wiring structure with low resistance is realized.

FIGS. 8 to 18 are views showing a second embodiment of the present invention. FIG. 8 shows a first example of a semiconductor device in which a multilayer wiring of at least two layers is formed. A second step of forming a first metal layer 33 on the first insulating film 32; a second step of depositing a first metal layer 33 on the first insulating film 32; A third step of depositing a film, and a third step on the second insulating film.
A fourth step of depositing an insulating film 35 of the second type, and connecting holes 36 for connecting the lower wiring layer and the upper wiring layer to the second insulating film 3.
4 and a third step of burying a metal 37 in the connection hole 36 after the third insulating film 35 is formed.
A photoresist pattern 38 is formed on the metal 37 of the connection hole 36 including the upper surface of the third insulating film 35 and the second insulating film 3 using the photoresist pattern 38.
A step of selectively etching the third insulating film 3 and the metal 37 in the connection hole 36 and the etched third insulating film 3.
5, using the second insulating film 34 as a mask, the first metal layer 3
A third step of patterning the third insulating film 3, an eighth step of depositing a fourth insulating film 39 on the entire surface, and forming a cavity 40 in the fourth insulating film 39; A ninth step of polishing the surface to expose the third insulating film 35 is shown.

The details of the second specific example will be described in detail. As shown in FIG. 8, a metal film layer 33 serving as a lower wiring is formed on a substrate 31 with an insulating film 32 interposed therebetween. A silicon oxide film (insulating film) 34 is further formed on
A silicon nitride film 35 is formed on the silicon oxide film 34 (FIG. 9). Next, using photolithography and dry etching, a connection hole 36 for electrically connecting the lower wiring and the upper wiring is formed (FIG. 10), and a metal such as tungsten is buried to form a metal column 37 (FIG. 10). (FIG. 11).

As a result, the lower wiring 33 and the upper wiring 41
Are electrically connected by a metal column 37. Next, using a photolithography method and a dry etching method, a resist pattern 38 for a lower wiring is formed (FIG. 12), and the silicon oxide film 34 and the silicon nitride film 35 are selectively removed (FIG. 13). At this time, since there is a limit in the photolithography method, even if the resist pattern 38 comes off from the metal pillar 37 (L is the amount of misalignment) and the metal pillar 37 is exposed to the etching atmosphere, the metal such as tungsten will It is not etched by a fluorocarbon-based gas for etching the oxide film 34 and the silicon nitride film 35.

Next, the etched silicon oxide film 3
A wiring pattern is formed on the metal layer 33 by dry etching using the silicon nitride film 35, the silicon nitride film 35, and the metal pillars 37 as masks (FIG. 14). At this time, the silicon oxide film 34, the silicon nitride film 35, and the metal 37 such as tungsten are not etched by the chlorine-based gas for etching the metal layer 33.

Further, after forming the lower wiring, a chemical vapor deposition (hereinafter referred to as C) using plasma for applying a high-frequency electric field to the substrate.
The silicon oxide film 39 is formed by using a bias ECR-CVD method, which is one of the methods (abbreviated as VD). FIG. 18 is a sectional view showing a schematic configuration of a bias ECR-CVD apparatus. As shown in the figure, a microwave introduction port 62 is provided in the upper part of the plasma chamber 61, from which microwaves are sent. The plasma chamber 61 is provided with gas introduction ports 59 (a), 59 (b) and an exhaust port 63, by which a reaction gas or the like is supplied and unnecessary gas is exhausted. Susceptor 6 in plasma chamber 61
0, on which a substrate 5 which is a workpiece is provided.
1 is mounted. The susceptor 60 is connected to a high frequency power supply 64 for RF bias. Further, a main coil 65 and an auxiliary coil 66 are provided, and a magnetic field is formed by these. Here, plasma is generated by applying microwaves while supplying oxygen (O ₂ ) gas from the gas supply port 59 (a). In this state, a silane gas is supplied together with argon from the gas supply port 59 (b) to form the silicon oxide film 39, and at the same time, a high frequency electric field is applied to the susceptor 60 to simultaneously perform etching with argon gas plasma. Do. The specific film forming conditions at this time are as follows: silane flow rate is 50 sccm, oxygen flow rate is 75 sccm, argon flow rate is 70 sccm, microwave output is 2000 W, and RF bias output is 1400.
W, the growth temperature is about 350 ° C.

The silicon oxide film 39 formed under these conditions
In the case of the large cavity 40, the aspect ratio of the wiring interval (the ratio of the thickness of the insulating film to the wiring interval) is 1.5 or more.
Can be formed. Next, the silicon oxide film 39 is flattened by a chemical mechanical polishing method (hereinafter abbreviated as CMP method). At this time, the silicon nitride film 35 functions as a CMP stopper, and can form a uniformly flat surface. Further, after the planarization, the upper wiring 41 is formed, and by repeating these steps, a multilayer wiring structure of two or more layers can be formed.

As described above, the connection metal pillar is formed before the lower wiring, and the lower wiring is formed in a self-aligned manner, thereby preventing misalignment between the lower wiring and the metal pillar and also providing a gap between the wiring. By forming the air gap 40, the capacity between the wirings can be reduced. In addition, since the connecting metal pillar is always on the lower wiring, contact with the air gap does not occur, and a highly reliable multilayer wiring structure can be realized.

As described above, the embodiment of the present invention has been described in connection with the case where the metal wiring has two layers, but the case where there are two or more layers may be used. Furthermore, although a cavity is taken as an example to be formed at the wiring interval, an organic film, a porous silicon oxide film, a fluorine-added silicon oxide film, or the like may be used. FIG.
FIG. 20 is a view showing a third specific example of the present invention. FIG. 20 shows a semiconductor device in which an air gap is formed in an insulating film covering between wirings in order to reduce the capacitance between wirings. A first step of forming an interlayer insulating film 72, a second step of forming an aluminum film 73 on the interlayer insulating film 72, and a third step of forming a silicon oxide film 74 on the aluminum film 73 A fourth step of forming a photoresist film 75 on the silicon oxide film 74 and patterning the silicon oxide film 74; and forming the aluminum film 7 using the silicon oxide film 74 as a mask.
A fifth step of patterning 3 and insulating film 76 over the entire surface;
And an eighth step of forming an air gap 77 in the insulating film 76.

Next, a third embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. Referring to the figure, a MOS transistor is formed on a P-type silicon substrate 71. Thereafter, a silicon oxide film (BPSG film) 72 containing phosphorus and boron is formed as an interlayer insulating film by a CVD method. After opening the contact hole, an aluminum film 73 containing 0.5% of copper is formed to a thickness of 600 nm by a sputtering method to form a first layer wiring. A silicon oxide film 74 is formed on the entire surface by plasma CVD as a hard mask for patterning aluminum wiring. Next, a wiring pattern is formed with a photoresist 75 by photolithography, and the silicon oxide film 74 is etched by dry etching such as reactive ion etching (RIE) using a gas such as CF ₄ or CHF ₃ to form a hard mask 91. It is formed (FIG. 19C). After removing the photoresist 75 by oxygen plasma ashing, BCl ₃
The first film 81 is formed by patterning the aluminum film 73 by dry etching such as reactive ion etching (RIE) using a gas such as the above and a hard mask 91 (FIG. 20A). Next, as shown in FIG. 20B, an oxide film 76 is formed as a wiring interlayer film by a plasma CVD method or the like. At this time, when the film is formed under the condition of poor coverage, the oxide film on the upper portion of the hard mask on the wiring comes into contact with each other before the groove between the adjacent wirings is filled with the oxide film in the portion where the wiring interval is narrow, and the relative dielectric constant Thus, the air gap 77 is formed so that the capacitance between adjacent wirings can be reduced. In the conventional method that does not use a hard mask, the shape of the air gap depends on the wiring metal film thickness and the wiring interval, and the volume of the air gap cannot be sufficiently increased above the wiring metal. In the case of the present invention, by setting the thickness of the hard mask 91 to 30% to 60% of the thickness of the wiring metal 81, an air gap is formed on all the side walls of the wiring, and the capacity reduction effect can be increased. If it is less than 30%, the air gap is not sufficiently formed, and if it exceeds 60%, problems such as thinning of the wiring occur.

Next, after the interlayer oxide film 76 is flattened by chemical mechanical polishing (CMP), a via hole is opened in the oxide film 76 by dry etching such as RIE, and a plug is formed in the via hole with tungsten or the like. .
Thereafter, an aluminum film is formed by a sputtering method, and a second-layer aluminum wiring is formed by photolithography and dry etching similarly to the first-layer wiring.

Next, a third embodiment of the present invention will be specifically described with reference to the drawings. A MOS transistor is formed on a P-type silicon substrate 71. Thereafter, a silicon oxide film (BPSG film) 72 containing phosphorus and boron is formed as an interlayer insulating film by a CVD method. After opening the contact hole, an aluminum film 73 is formed to a thickness of 600 nm by a sputtering method to form a first layer wiring. A silicon oxide film 74 is formed on the entire surface by plasma CVD as a hard mask for patterning aluminum wiring. Next, a wiring pattern is formed with a photoresist 75 by photolithography, and the silicon oxide film 74 is etched by dry etching such as reactive ion etching to form a hard mask 91. After removing the photoresist 75 by oxygen plasma ashing, the first layer wiring 81 is formed by patterning the aluminum film 73 by dry etching such as reactive ion etching using a gas such as BCl ₃ . Next, as shown in FIG. 20B, an interlayer insulating film 76 is formed by a plasma CVD method or the like. As the insulating film 76, a fluorine-containing oxide film (Si
OF) or fluoridated amorphous carbon. At this time, by forming the film under conditions of poor coverage, the oxide film on the upper portion of the upper hard mask between the adjacent wires comes into contact with each other before the trench between the adjacent wires is filled with the oxide film in a portion where the space between the wires is narrow, and an air gap is formed. 77 is formed. Next, after the interlayer oxide film 76 is planarized by chemical mechanical polishing (CMP), a via hole is opened in the oxide film by dry etching such as RIE, and a plug is formed in the via hole with tungsten or the like. Thereafter, an aluminum film is formed by a sputtering method, and a second-layer aluminum wiring is formed by photolithography and dry etching similarly to the first-layer wiring.

[0027]

Semiconductor equipment manufacturing method of the present invention exhibits, at least two or more layers of aluminum interconnection layer is formed, in the semiconductor device connected to the upper wiring layer and the lower wiring layer in the connection plug, the connection Since the plug is made of aluminum or an aluminum alloy and an oxide layer is formed on the side wall of the connection plug, high-integration multilayer wiring is possible without increasing a margin for misalignment, and furthermore, a wiring pattern and Poor misalignment of the plug can be prevented,
Also, since aluminum or aluminum alloy can be used for the plug,
A semiconductor device having low resistance and high reliability can be realized.

Also, in a semiconductor device having an air gap formed in an insulating film covering between wirings made of an aluminum film in order to reduce the capacitance between wirings, when the insulating film is deposited, the aspect ratio of the cross section of the deposited portion is reduced. Is at least 1.5 or more, that is, the ratio of the thickness of the insulating film to the wiring interval is 1.5 or more, so that a large air gap can be formed, and as a result, the capacitance between the wirings can be reliably reduced. .

Further, in a semiconductor device in which an air gap is formed in an insulating film covering between wirings made of an aluminum film in order to reduce the capacitance between wirings, an insulating film is formed on the wirings along the wirings, and Since the thickness of the insulating film is 30 to 60% of the thickness of the aluminum film, a large air gap can be formed, and as a result, the capacitance between wirings can be reliably reduced.

[Brief description of the drawings]

FIG. 1 is a view showing a process of a first specific example of a semiconductor device of the present invention.

FIG. 2 is a view showing a step following the step shown in FIG. 1;

FIG. 3 is a view showing a step following the step shown in FIG. 2;

FIG. 4 is a view showing a step following the step shown in FIG. 3;

FIG. 5 is a view showing a step following the step shown in FIG. 4;

FIG. 6 is a view showing a step following the step shown in FIG. 5;

FIG. 7 is a view showing a step following the step shown in FIG. 6;

FIG. 8 is a view showing a process of a second specific example of the semiconductor device of the present invention.

FIG. 9 is a view showing a step following the step shown in FIG. 8;

FIG. 10 is a view showing a step following the step shown in FIG. 9;

FIG. 11 is a view showing a step following the step shown in FIG. 10;

FIG. 12 is a view showing a step that follows the step of FIG. 11;

FIG. 13 is a view showing a step following the step shown in FIG. 12;

FIG. 14 is a view showing a step following the step shown in FIG. 13;

FIG. 15 is a view showing a step following the step shown in FIG. 14;

FIG. 16 is a view showing a step following the step shown in FIG. 15;

FIG. 17 is a view showing a step following the step shown in FIG. 16;

FIG. 18 shows a bias CR- used in the second specific example.
It is sectional drawing of a CVD apparatus.

FIG. 19 is a view showing a process of a third specific example of the semiconductor device of the present invention.

FIG. 20 is a view showing a step following the step shown in FIG. 19;

FIG. 21 is a diagram showing a conventional technique.

FIG. 22 is a view showing a step following the step shown in FIG. 21.

FIG. 23 is a view showing a step following the step shown in FIG. 22;

FIG. 24 is a view showing a step following the step shown in FIG. 23.

FIG. 25 is a view showing a step following the step shown in FIG. 24;

FIG. 26 is a view showing a step following the step shown in FIG. 25;

FIG. 27 is a graph comparing the present invention with the prior art.

[Explanation of symbols]

 1, 31, 71 semiconductor substrate 2 first insulating film 3 first metal layer 4 second metal layer 5 third metal layer 6 fourth metal layer 7 fifth metal layer 8, 10, 38, 75 Photoresist 9 Oxide film (oxide layer) 11 Second insulating film 21 Mask oxide film 23 Wiring pattern 24 Plug 32, 76 Insulating film 33 Lower wiring metal layer 34, 39, 72, 74 Silicon oxide film 35 Silicon nitride film 36 Connection Hole 37 Metal pillar 40, 77 Air gap (cavity) 73 Aluminum film 76 Interlayer insulating film 81 First layer wiring 91 Hard mask

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-111052 (JP, A) JP-A-3-192721 (JP, A) JP-A-9-55431 (JP, A) JP-A-9-99 64172 (JP, A) JP-A-1-296644 (JP, A) JP-A-63-98134 (JP, A) JP-A-7-221180 (JP, A) JP-A-61-208850 (JP, A) JP-A-7-283308 (JP, A) JP-A-63-272050 (JP, A) Patent 2948588 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/3205- 21/3213 H01L 21/768

Claims (1)

(57) [Claims] 1. A multi-layer wiring of at least two layers is formed.
Forming a first insulating film covering a semiconductor substrate in a method of manufacturing a semiconductor device.
A refractory metal or a compound thereof on the first insulating film.
A second step of depositing a first metal layer, and a second step of depositing aluminum or an aluminum alloy on the first metal layer.
A third step of depositing a second metal layer, and a fourth step of depositing a third metal layer on the second metal layer.
And forming a third layer made of aluminum or aluminum alloy on the third metal layer.
A fifth step of depositing a fourth metal layer, and a sixth step of depositing a fifth metal layer on the fourth metal layer.
And a seventh step of depositing a second insulating film on the fifth metal layer.
And extent, forming a photoresist pattern on the second insulating film
Then, the second insulating layer is formed by using the photoresist pattern.
An eighth step of patterning the edge film, and using the patterned second insulating film as a mask,
The fifth metal layer and the fourth metal other than the connection plug portion
Etching the layer, exposing the third metal layer and connecting plug
Forming a ninth step, and oxidizing a sidewall of the patterned fourth metal layer
Tenth step , forming a desired wiring pattern substantially covering the fourth metal layer
Eleventh step of forming a resist pattern for performing
If, based on said resist pattern the third metal layer, the second
Etching the metal layer and the first metal layer to form a wiring pattern
A twelfth step of forming and, after removing the resist pattern, completely removing the second insulating film.
A thirteenth step of depositing on the surface, and polishing the surface of the second insulating film to expose the fifth metal layer.
A fourteenth step of discharging
Manufacturing method of body device.