JP3130866B2 - ATM switch permanent stay address detection circuit and permanent stay address detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a permanent stay address detection circuit and a permanent stay address detection method for detecting a permanent stay address in a shared buffer of a shared buffer type ATM switch.

[0002]

2. Description of the Related Art An ATM switch of a shared buffer system is:
To reduce buffer capacity, multiple delay clocks exist.
Share buffers in Lass. Delaying shared buffers
The used area for each class is not fixed, and unused addresses are assigned.
I am using it. The shared buffer temporarily stores ATM cells.
Cell shared buffer to save and cell shared buffer address
There are two types of area management shared buffers for managing
There is an existing ATM switch.

[0003] In this ATM switch, a cell sharing buffer is used.
Buffer address and area management shared buffer address
In order to keep the connection of all the addresses, it takes the chain configuration to call the next use address (see FIG. 2), when an error such as chain is shortcut occurs before using the address, a shortcut The remaining address is permanently stored in the buffer, and the throughput of the ATM switch is reduced.

For this reason, it is necessary to monitor the occurrence of permanent stagnation. In the prior art, a table for checking the use state of the address is provided, and a use flag in the table is set at the time of writing in the management buffer, and all addresses are used. At the time period expected to be used, the use flag of the table is monitored to check the use state of all addresses.

[0005]

As described above, in the prior art, a use flag of a table for checking the use state of an address is monitored at a time period in which all addresses are expected to be used. The use status of all addresses was checked, but the problem in this case is that the buffer to which the address is written has a plurality of delay class queues and is read from the address of the high priority delay class queue. , Reading the low priority delay class queue
If it has been completely priority control type to be read only when no cell in the high-priority delay classes, low priority delay classes
Difficult to predict longest period read from skew
There was a problem that.

An object of the present invention is to use all addresses.
An object of the present invention is to provide a permanent staying address detection circuit and a permanent staying address detection method capable of detecting a staying address after confirming that the address has been deleted.

[0007]

SUMMARY OF THE INVENTION A permanent stay address detection circuit according to the present invention includes a cell shared buffer unit having a function of temporarily storing an ATM cell for switching, and an area for managing write and read addresses of the cell shared buffer unit. An unused address of the management shared buffer unit and the cell shared buffer unit, and a cell shared buffer standby address FIF used sequentially from the unused address.
ATM which stores an unused address of the area management shared buffer unit and an area management shared buffer standby address FIFO which is used sequentially from the unused address.
In a permanent stay address detection circuit for detecting a permanent stay address in the shared buffer unit of the switch, a use status table that is initialized at the start of detection of the permanent stay address and checks an address written in the area management shared buffer unit. A monitoring control unit that performs detection start control of a permanent staying address and searches for an unused address in the use status table, and manages the number of addresses currently stored in the area management shared buffer unit in real time for each queue unit. And a delay counter provided for each of the output ports and the delay class queues. At the time of the detection start control from the monitoring control unit, the retention count in the area management shared buffer unit is latched from the retention count counter. A final address determination counter that decrements the number for each read, and all queues An address circulating counter that starts counting after the counter value of the final address determination counter has become zero, and after the address circulating counter has counted all addresses, the monitoring control unit sets the usage status table. , The address staying in the buffer is detected based on the use flag in the field.

According to the present invention, the monitoring status of the use status of the buffer address corresponds to the buffer address which is used aperiodically and randomly and the cycle in which all the addresses go round is indefinite. After reliably recognizing one cycle, the address staying in the buffer is detected by the use flag in the table for monitoring the use state of the buffer address.

[0009]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a permanent staying address detection circuit according to the present invention, and FIG. 2 is a diagram for explaining an address chain of a cell shared buffer unit and an area management shared buffer unit.

In FIG. 1, reference numeral 1 denotes a permanent stay address detection circuit of the present invention, 2 denotes a cell shared buffer, 3 denotes an area management shared buffer, 5 denotes an area management shared buffer standby address FIFO, and 6 denotes a cell shared buffer standby address. FI
FO.

The cell sharing buffer unit 2 has a function of temporarily storing ATM cells for switching. The write and read addresses of the cell shared buffer 2 are managed from the area management shared buffer 3.

The area management shared buffer unit 3 is a shared buffer system having a capacity equal to the cell capacity of the cell shared buffer unit 2. As shown in FIG. 2, the area management shared buffer unit 3 has a plurality of logical queues 34 for each ATM cell output port and delay class in order to manage the ATM cell storage address in the cell shared buffer unit 2. ing.

The address connectivity of the logical queue 34 is maintained by the address chain by the address chain.
The address (C050) of the cell shared buffer unit 2 in which cells are stored in one area (A000) and the address (A100) of the area management shared buffer unit 3 to be used next are 2
Information. When the address (A000) held in the RD address register 33 is read, the RD address (A100) to be used next is read and the RD address is read.
The address is held in the address register 33 and becomes the next address to be used. The WR address register 32 also holds the next address to be used, and maintains the connectivity of the randomly used address.

Cell shared buffer standby address FIFO6
Stores an unused address of the cell shared buffer unit 2,
A FIFO memory used sequentially from unused addresses is used.

Area management shared buffer standby address FIF
O5 stores an unused address of the area management shared buffer unit 3, and F used sequentially from the unused address.
IFO memory is used.

The permanent staying address detection circuit 1 detects an address stored in the area management shared buffer unit 3 that is out of the address chain for some reason and stays unused without being used. It comprises an all-address circulating counter 11, a use status table 12, a monitoring control unit 13, a final address determination counter 14, and a stay number counter 15.

The monitoring control unit 13 performs control to start permanent staying address monitoring and searches for an unused address in the usage status table.

The stay number counter 15 manages the number of addresses currently stored in the area management shared buffer unit 3 in real time for each queue.

The use status table 12 checks the address written (used) in the area management shared buffer unit 3. The start / end of the check is determined by the monitoring control unit 13
Is controlled by From the start to the end of the check, the same ad
No matter how many times the address is used, write the flag to the use state
Only and reset to unused state only at next start
You. If the address is stagnant,
It remains unused.

The all-address circulating counter 11 detects that all addresses have circulated and the use status table 12 has been checked, and notifies the monitoring control unit 13. The counting is started after the last address is determined by the last address determination counter 14.

The last address determination counter 14 has a counter for each output port and each delay class queue, and latches the number of stays in the area management shared buffer unit 3 at the time of start control from the monitoring control unit 13. The latched number of stays is decremented each time the data is read, the address at which the count value of all queues has become 0 is determined to be the last address read, and the start of the all address cyclic counter 11 is notified to the monitor control unit 13.

Next, an address chain of the cell shared buffer section and the area management shared buffer section will be described with reference to FIG. 2, and then a method for detecting a permanent stay address will be described.

DATA in one address of the area management shared buffer 3 has an address written in the cell shared buffer 2 and an address of the area management shared buffer 3 to be read next. For example, when the data held by the address (A000) is the address (C050) of the cell shared buffer unit 2 and the address (A100) of the area management shared buffer unit 3 to be used next, (A000)
When (A100) is read, the read (A100) is held in the RD address register 33 and used to read the next address. When (A100) is read, (A040) is read and held in the RD address register 33. Construct the chain.

The unused address has a simple configuration.
The management address (A000) for which the reading has been completed is written, and is used in the order of writing. In FIG. 2,
Although only one queue is shown, the actual inside of the area management shared buffer is logically divided into queues equal to the number of output ports × the number of delay classes, and the chains of each queue maintain connectivity.

The permanent stay address detection method is a method for detecting the stay of cells in a buffer, which occurs when the connectivity of a chain is cut off, and its processing flow is shown in FIG.

In step A1, the monitoring control unit 13 performs detection process start control. In step A8, after the start control from the monitoring control unit 13, the use state table 12 is initialized and the use state monitoring is started. That is, when the detection process is started in the state of FIG. 2, (A003) at the head of the area management shared buffer standby address FIFO 5 and (C004) at the head of the cell shared buffer standby address FIFO 6
Start monitoring from.

In step A2, in order to recognize the last address, the area management shared buffer 3
The value of the staying number counter 15, which is the address staying at the address, is latched by the final address determination counter 14 for each queue.

At steps A3 and A4, the area management shared buffer standby address FIFO5 and the cell shared buffer standby address FIFO
In order to detect the last address written in O6, the count value of the last address determination counter 14 of the corresponding queue is decremented every time reading from the area management shared buffer unit 3,
The address when the count value of all queues becomes '0' is recognized as the last address. That is, in FIG. 2, (A040) held in the WR address register 32 is the final address.

In steps A5, A6, and A7, the address use order after the last address is written in the area management shared buffer standby address FIFO5 and the cell shared buffer standby address FIFO6 is used in the order of unused. The number of addresses read from the standby address FIFO is counted by the all address counter 11, and when the number of all addresses is counted, it is determined that the last address has been used.

In step 9, since the use status of all the addresses has been confirmed, the monitoring control unit 13 recognizes the unused address based on the flag of the use status table 12, and detects the address which is permanently stored. .

As described above, in this embodiment, the last address determination counter 14 starts processing in response to the detection start signal from the monitoring control unit 13, and the all address cyclic counter 11 counts using the last address detection as a trigger. To start. When the all-address circulating counter 11 counts the number of all addresses, it is determined that all addresses are circulated, and a permanent staying address is detected by searching for an unused address in the use status table 12. The usage status table 12 is triggered by the detection start signal from the monitoring control unit 13 to check an address to be written into the buffer. If there is an unused address at the time when the address has completed one round, it is determined that the address is permanently stored.

[0033]

As described above, in the prior art, the address which has stayed in the time period in which all the addresses are expected to be used is detected. Although there was a problem that it was not possible to judge whether or not the address was staying, in the present invention, since the address which stayed was detected after confirming that all the addresses circulated, it was possible to reliably detect the address which stayed. is there.

Further, according to the present invention, not only permanent residence but also an address lost for some reason can be detected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a permanent residence address detection circuit of the present invention.

FIG. 2 is a diagram illustrating an address chain of a cell shared buffer unit and an area management shared buffer unit.

FIG. 3 is a processing flowchart showing an embodiment of a permanent staying address detection method of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Permanent stay address detection circuit 2 Cell shared buffer unit 3 Area management shared buffer unit 5 Area management shared buffer standby address FIFO 6 Cell shared buffer standby address FIFO 11 All address cyclic counter 12 Usage status table 13 Monitoring control unit 14 Final address determination counter 15 Stay number counter 32 WR address register 33 RD address register 34 Logical queue

Claims (4)

(57) [Claims] 1. A shared buffer type ATM switch, comprising: a cell shared buffer unit having a function of temporarily storing an ATM cell for switching, wherein a write / read address of the cell shared buffer unit is managed by an area management shared buffer unit. A permanent stay address detection circuit for detecting a permanent stay address in the shared buffer, a use status table which is initialized at the start of detection of the permanent stay address and checks an address written to the area management shared buffer unit, A final address determination counter that latches the number of stays of addresses stored in the area management shared buffer unit at each queue unit at the start of detection of a permanent stay address, and decrements the latched stay number for each read. Final address determination for all queues A counter that starts counting after the counter value of the counter reaches zero, and after counting all addresses by the address circulating counter, stays in the buffer according to the use flag in the use status table. A permanent staying address detection circuit, which detects an address in the memory. 2. A cell shared buffer unit having a function of temporarily storing an ATM cell for switching, an area management shared buffer unit for managing write and read addresses of the cell shared buffer unit, and an unused address of the cell shared buffer unit. And the cell shared buffer standby address FIFO used sequentially from the unused address
ATM that stores an unused address of the area management shared buffer unit and an area management shared buffer standby address FIFO that is used sequentially from the unused address.
In a permanent stay address detection circuit for detecting a permanent stay address in the shared buffer unit of the switch, a use status table which is initialized at the start of detection of a permanent stay address and checks an address written in the area management shared buffer unit; A monitoring control unit that performs detection start control of a permanent staying address and searches for an unused address in the use status table; and manages the number of addresses currently stored in the area management shared buffer unit in real time for each queue unit. And a delay counter provided for each output port and each delay class queue. At the time of detection start control from the monitoring control unit, the number of stays in the area management shared buffer unit is latched from the stay number counter, and the latched A final address determination counter that decrements An address circulating counter that starts counting after the counter value of the last address determination counter of the ー has reached zero, and after the number of all addresses has been counted by the address circulating counter, the monitoring control unit performs A permanent staying address detection circuit for detecting an address staying in a buffer according to a use flag in a status table. 3. A shared buffer type ATM switch according to claim 1, further comprising a cell shared buffer unit having a function of temporarily storing an ATM cell for switching, wherein a write / read address of said cell shared buffer unit is managed by an area management shared buffer unit. In the method for detecting a permanent resident address in a shared buffer, a usage state table for checking an address written in the area management shared buffer is initialized, and an address stagnated in the area management shared buffer is initialized. The number of stays of each queue is latched for each queue, and the number of stays of the corresponding queue is subtracted every time reading from the area management shared buffer unit. When the number of stays of all queues becomes zero, counting is started. When the number of addresses has been counted, the A permanent staying address detection method characterized by recognizing an unused address and detecting an address staying permanently. 4. A cell shared buffer unit having a function of temporarily storing an ATM cell for switching, an area management shared buffer unit for managing write and read addresses of the cell shared buffer unit, and an unused address of the cell shared buffer unit. And the cell shared buffer standby address FIFO used sequentially from the unused address
ATM that stores an unused address of the area management shared buffer unit and an area management shared buffer standby address FIFO that is used sequentially from the unused address.
In the permanent retention address detection method for detecting a permanent retention address in the shared buffer unit of a switch, a use status table for checking an address written in the area management shared buffer unit is initialized, and each output port and each delay class queue The number of staying addresses in the area management shared buffer at the start of detection is latched by a final address determination counter, and each time the address is read from the area management shared buffer, the count of the last address determination counter of the corresponding queue is counted. After the count value of the last address determination counter of all queues becomes zero, the all address cyclic counter starts counting, and when the all address cyclic counter has counted the total number of addresses, Unused addresses can be specified by flags in the status table. Recognizes, permanent residence address detecting method and detecting an address that is permanently retained.