JP3129102B2 - Data bus monitor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data bus monitor device in which a controller comprising a microprocessor or the like monitors an operation result written in a RAM to analyze whether or not the operation of the controller is normal.

[0002]

2. Description of the Related Art An engine control system (hereinafter referred to as ECCS)
) And anti-lock brake systems (hereinafter referred to as AB
S), the calculation of the engine speed, wheel rotation speed, and the like is performed by the controller 10 (hereinafter, ECU: Electric Controller).
ol Unit). As shown in FIG. 10, a conventional ECU 200 of this type generally has a CPU
201, a ROM 202 and a RAM 203;
The PU 201 performs various calculations based on the program stored in the ROM 202 and stores the calculation results in the RAM 203.
To be stored. Therefore, by analyzing the contents of the RAM 203, it can be determined whether or not the operation of the ECU 200 is normal. A device that performs such an analysis is generally called a data bus monitor device.

As shown in FIG. 10, a conventional data bus monitor device 100 includes a plurality of monitor units 101 for monitoring data written in a specific RAM area, and each monitor unit 101 is provided with an address decoder. 1
02, latch 103, D / A converters 104 and 7
It has a segLED 105. Address decoder 102
Is connected to the address bus of the CPU 201 in the ECU, and the latch 103 is connected to the data bus of the CPU 201 in the ECU. When the CPU 201 outputs a predetermined address value to the address bus, the output of the address decoder 102 changes, and the data on the data bus at the time of the change is held by the latch 103.

The data held by the latch 103 is displayed in real time by a 7-segment LED 105, converted into an analog value by a D / A converter 104, input to a well-known data logger 106, and printed as analog numerical data. Be out.

As described above, the conventional data bus monitor device 100 is configured so that when the CPU 201 in the ECU rewrites a specific area of the RAM 203, the rewritten data is automatically latched. Data changes can be monitored in real time.

[0006]

[Problems to be Solved by the Invention] Recent EC for ECCS
U and ABS ECUs have complicated control algorithms, and these ECUs have a very large RAM capacity for storing calculation results. For this reason, it is necessary to monitor a large amount of RAM area in order to analyze the arithmetic operation of the ECU in detail.

However, in the conventional data bus monitor device, it is necessary to provide the monitor unit 101 including the address decoder 102, the latch 103, the D / A converter 104, and the 7-segment LED 105 for each address of the RAM 203 to be monitored. When the RAM area to be increased increases, the circuit scale of the entire data bus monitor increases accordingly. As the circuit scale increases, the power consumption increases in proportion to it, and the mounting area of the device also increases, so it is not easy to use this type of data bus monitor device for vehicles where the mounting space is originally severely limited. .

Further, since the address bus and data bus of the CPU 201 in the ECU are connected to the respective monitor units 101 in the data bus monitor device 100, when the number of monitor units 101 is large, the address bus or the data bus is driven. There is a possibility that the capacity limit may be exceeded (the number of fan-outs may be exceeded), and the signal amplitude may be reduced or the apparatus may be susceptible to noise.

Further, the conventional data bus monitor device is
In many cases, after latching the data output from the CPU 201, the data is once converted to an analog value and then collected by a data logger or the like. Therefore, the analog value may intermittently fluctuate greatly, thereby lowering the reliability of data. That is, in a place that is susceptible to noise, it is desirable to perform data analysis with the digital value as it is without converting it to an analog value.

An object of the present invention is to provide a data bus monitor device capable of analyzing in detail the operation results of high-performance and various types of controllers without adding or replacing components such as an address decoder. .

[0011]

The present invention will be described with reference to FIGS. 1 and 5 showing an embodiment.
Monitor the data written to the controller 201
Applied to a data bus monitor that analyzes the operation of
When the controller 201 writes data to the RAM 203, the dual-port RAM 1 writes data at substantially the same timing.
And electrical characteristics, including timings of an address signal, a data signal, and a write control signal, which are interposed between the controller 201 and the dual port RAM 1 and output from the controller 201, are changed according to the type of the dual port RAM 1. Interface means 2; control means 3 for continuously reading data at the same address in dual port RAM 1 a plurality of times; and processing the read data only when the read data matches continuously for a predetermined number of times; The above object is achieved by providing display collecting means 7 and 8 for displaying or collecting the data processed by 3. The invention according to claim 2 is applied to a data bus monitor device that monitors data written by the controller 201 to be inspected in the RAM 203 and analyzes the operation of the controller 201.
03 having a storage capacity equal to or larger than the storage capacity of the controller 2
01 writes data to the RAM 203, the dual-port RAM 1 that writes data at substantially the same timing, and an address signal, a data signal, and a write control signal that are inserted between the controller 201 and the dual-port RAM 1 and output from the controller 201. Interface means 2 for changing the electrical characteristics including the respective timings according to the type of the dual port RAM 1, and control means 3 for reading out the data written in the dual port RAM 1 at a predetermined timing and processing the written data.
The above object is achieved by providing an analyzer 9 for analyzing data processed by the control means 3.
According to a third aspect of the present invention, in the data bus monitor device according to the first or second aspect, the dual port RA is provided.
A read / write duplication detecting means 11 for sending an interrupt signal to the control means 3 when reading and writing are simultaneously instructed to the same address of M1 is provided.
The control means 3 is configured to delay the read timing of the dual port RAM 1. According to a fourth aspect of the present invention, in the data bus monitor device according to the second aspect, data of the same address of the dual port RAM 1 is continuously read a plurality of times, and the read data matches a predetermined number of times continuously. Only, the control means 3 is configured to process the read data.

[0012]

According to the first aspect of the present invention, the controller 20 is provided.
1 writes the same data to the dual-port RAM 1 having a storage capacity equal to or larger than the storage capacity of the RAM 203 at substantially the same timing as when writing data to the RAM 203. The interface means 2 interposed between the controller 201 and the dual port RAM 1 converts the electrical characteristics including the timings of the address signal, data signal, and write control signal output from the controller 201 to the type of the dual port RAM 1. Change accordingly. The data written in the dual port RAM 1 is
The data at the same address is read out a plurality of times in succession, and the data is processed only when the read out data matches the predetermined number of times in succession. The processed data is displayed or collected by the display collection means 7 and 8. Is done. According to the second aspect of the present invention, the data written in the dual port RAM 1 is read out and processed at a predetermined timing by the control means 3, and the processed data is analyzed by the analysis device 9. According to the third aspect of the present invention, if simultaneous reading and writing are to be performed on the same address of the dual port RAM 1, the read / write duplication detecting means 11 sends an interrupt signal to the control means 3. Then, when the interrupt signal is input, the control means 3 delays the read timing of the dual port RAM 1. The control means 3 according to the fourth aspect of the present invention reads the data at the same address of the dual port RAM 1 continuously plural times, and processes the read data only when the read data matches a predetermined number of times continuously. Do.

In the means and means for solving the above problems which explain the constitution of the present invention, the drawings of the embodiments are used for easy understanding of the present invention. However, the present invention is not limited to this.

[0014]

1 shows a data bus monitor 1 according to the present invention.
It is a block diagram of one Example of 00A. In FIG.
Reference numeral 1 denotes a CPU 201 in the ECU (hereinafter, referred to as a CPU in the ECU) which stores a RAM 203 in the ECU (hereinafter, an RA in the ECU).
M) is written in the dual-port RAM. As shown in FIG. 2, this dual port RAM 1
CPU in the ECU having a storage capacity not less than
1 can write data to the dual-port RAM 1 without any loss of data in any area of the RAM 203 in the ECU.

Reference numeral 2 denotes an ECU interface section interposed between the CPU 201 in the ECU and the dual port RAM 1, and receives an address signal, a data signal, and a write enable signal output from the CPU 201 in the ECU. Since the write timing of the RAM 203 in the ECU and the write timing of the dual port RAM 1 are generally different from each other, the write timing is changed by the ECU interface unit 2 and the dual port RAM 1 is changed.
Ensure that data can be written.

For example, when the timing at which the CPU 201 in the ECU outputs data for writing to the RAM 203 in the ECU is shown in FIG. 3A and the timing for writing to the dual port RAM 1 is shown in FIG. 3B, the timing shown in FIG. Since data cannot be normally written to the dual port RAM 1, the ECU interface unit 2
After the timing is changed as shown in (b), the data is written to the dual port RAM 1. The RAM 2 in the ECU
If the voltage level of the dual port RAM 03 differs from that of the dual port RAM 1, the ECU interface unit 2 also adjusts the voltage level.

Reference numeral 3 shown in FIG. 1 denotes a CPU (hereinafter referred to as a monitor CPU) for reading data stored in the dual port RAM 1 and processing the data. E
The data written to the RAM 203 in the CU includes additional information such as a code identification bit and an error determination bit. Even if the data is displayed on a 7-segment LED or the like while including the additional information, the content of the data is difficult to understand. . Therefore, in the CPU 3 in the monitor, the dual port RAM 1
The auxiliary information is extracted from the data stored in the. And the data is processed based on the additional information. Also, E
Since the writing format of data having a word length or more differs depending on the type of the CPU 201 in the CU, the writing format is unified in the CPU 3 in the monitor.

Reference numeral 4 denotes a timer connected to the CPU 3 in the monitor. Every time a predetermined time is measured by the timer 4, the CPU 3 in the monitor reads the contents of the dual port RAM 1. Instead of having the timer 4 separately from the CPU 3 in the monitor, a timer included in the CPU 3 in the monitor itself may be used.

5 is a ROM for storing an operation program of the CPU 3 in the monitor, 6 is a RAM for storing data processed by the CPU 3 in the monitor, 7 is a 7 seg LED for displaying data processed by the CPU 3 in the monitor, and 8 is a CP in the monitor.
D / which converts the data processed by U3 into analog data
A converter. Reference numeral 9 denotes a personal computer for analyzing data processed by the CPU 3 in the monitor. The CPU 3 in the monitor and the personal computer 9 are connected via a PC interface unit 10. The personal computer 9 performs data waveform display, data analysis, data storage, and the like.

The data bus monitor 100 shown in FIG.
A has three types of bus lines denoted by L1, L2 and L3, of which the bus line L1 is synchronized with the operation timing of the CPU 201 in the ECU, the bus line L2 is synchronized with the operation timing of the dual port RAM1, L
3 is synchronized with the operation timing of the CPU 3 in the monitor.

Hereinafter, the operation of the first embodiment of the data bus monitor 100A configured as shown in FIG. 1 will be described.
When the CPU 201 in the ECU writes data to an arbitrary address in the RAM 203 in the ECU, the CPU 201 in the ECU 201
The address signal, data signal and various control signals output from the ECU are timing-converted by the ECU interface unit 2 and the same data is written to the dual-port RAM 1 at substantially the same timing as the writing to the RAM 203 in the ECU.

On the other hand, the CPU 3 in the monitor receives an interrupt from the timer 4 at regular intervals, and every time an interrupt occurs, the CPU 3 in the monitor reads the data stored in the dual port RAM 1 and extracts the attached information from the data. To process the data. At this time, the time interval at which the timer interrupt occurs is determined by the CPU 201 in the ECU.
If the time interval is longer than the time interval for rewriting the data in the AM 203, the CPU 3 in the monitor cannot monitor all the data written in the RAM 203 in the ECU.
The time interval at which a timer interrupt is generated is determined by the CPU 20 in the ECU.
1 is preferably shorter than the time interval for rewriting the data in the RAM 203 in the ECU. The data processed by the CPU 3 in the monitor is output to the 7-segment LED 7 and the D / A converter 8, and is displayed or collected at almost the same timing as written in the RAM 203 in the ECU.

On the other hand, when there is a data read request from the personal computer 9, the CPU 3 in the monitor
The data is sent to the personal computer 9 via the PC and various data analyzes are performed inside the personal computer 9. When sending data to the personal computer 9, the contents of the dual port RAM 1 may be sent directly, or the data after the CPU 3 in the monitor processes the data may be sent.

The dual-port RAM 1 has two types of ports for reading and writing data, and has a feature that data can be read and written from each port simultaneously. However, when data is simultaneously written from each port to the same address, dual port RAM
Due to the structure of (1), there is a possibility that a large amount of current flows and the internal element is broken. For this reason, the port connected to the CPU 201 in the ECU is dedicated to writing, and the CPU
It is desirable that the port connected to 3 be read-only.

When data is written from the other port to the same address while data is being read from one port, the dual port RAM 1 has a structure
The data at that address may be undefined. For this reason, a dual-port RAM 1 having a bus arbitration function of giving priority to a port that has accessed the dual-port RAM 1 first, giving a weight to a port accessed later, or prohibiting writing has also been commercialized. However, when the weight is applied, it takes extra time to read and write data, and the data processing performed by the CPU 3 in the monitor also takes time. Therefore, the in-monitor CPU 3 of this embodiment reads data from the dual port RAM 1 based on the flowchart of FIG. 4 described below. The CPU 3 in the monitor performs the processing of FIG. 4 every time an interrupt is received from the timer 4.

In step S1 of FIG. 4, data is read from the dual port RAM 1, and the data is stored in the internal register R. In step S2, the RAM in the monitor
The data of the internal register R is stored at the address A of No. 6. In step S3, the variable n is initialized to “1”.
The variable n is used to measure how many times the determination process in step S6 described below is repeated.

In step S4, data is read from the dual port RAM 1 and stored in the internal register R as in step S1. In step S5, "1" is added to the variable n. In step S6, it is determined whether or not the value of the internal register R matches the data stored at the address A of the RAM 6 in the monitor. If the determination is affirmative, the process ends, and if the determination is negative, step S7
Proceed to. In step S7, the value of the variable n is determined whether n _max or more. If the determination is affirmative, the process proceeds to step S8 to perform error processing, and if the determination is negative, the process proceeds to step 9. As the error processing, for example, a warning display indicating that the contents of the dual port RAM 1 could not be read correctly, a monitoring stop processing of the RAM 203 in the ECU, and the like are performed. In step S9, as in step S2, the data of the register R is stored at the address A of the RAM 6 in the monitor, and the process returns to step S4.

As described above, the CP in the monitor of the first embodiment is
U3 reads the contents of the dual-port RAM 1 at least twice, and if the read data matches twice consecutively, determines that the data has been read correctly, and performs data processing using the read data. On the other hand, if the data value is different each time even when reading is performed continuously for n _max times, the data processing is stopped and error processing is performed. That is, according to the processing of FIG. 4, when reading data from the dual port RAM 1, there is no need to wait, so that data can be read quickly. Further, since the data processing is performed only when the data read from the dual port RAM 1 successively matches a plurality of times, the data processing is not performed using erroneous data, and the reliability is improved.

According to the first embodiment described above, E
A dual port RAM 1 having a storage capacity equal to or larger than the storage capacity of the RAM 203 in the CU is provided in the data bus monitor device, and all the data written to the RAM 203 in the ECU by the CPU 201 in the ECU are written to the dual port RAM 1 almost in real time. The data written to any area of the RAM 203 in the ECU can be monitored without omission. Therefore, a failure or the like with extremely low reproducibility can be reliably detected. In addition, since all the data analysis processing is performed digitally, it is less susceptible to noise.

Further, since there is no need to provide a plurality of address decoders and latches, the circuit scale can be significantly reduced as compared with the conventional data bus monitor. Therefore,
It is particularly useful for automotive applications where the mounting space is severely limited. Further, since the ECU interface unit 2 is provided between the CPU 201 in the ECU and the dual port RAM 1, even if the write timing and voltage level of the RAM 203 in the ECU and the dual port RAM 1 are different,
Data written to the RAM 1 in the ECU can be reliably written to the dual port RAM 1.

Further, for example, when the CPU 201 in the ECU rewrites the data in the RAM 203 in the ECU so quickly that the data cannot be confirmed by human eyes, the ECU interface unit 2 can convert the timing to a speed that can be confirmed by human eyes. ECU by 7seg LED7 etc.
The state of change of the internal RAM 203 can be observed in detail. In addition, the CPU 201 in the ECU to be inspected and the ECU
When the type of the internal RAM 203 is changed, only the configuration of the ECU interface unit 2 needs to be changed, so that data analysis of various types of high-performance ECUs becomes possible.

Further, the data written in the RAM 203 in the ECU can be written in the dual port RAM 1 without affecting the operation of the CPU 201 in the ECU.
The operation program of the CPU in the ECU does not need to be changed. When it is necessary to analyze the data written in the RAM 203 in the ECU by the CPU 201 in the ECU in detail,
Since the data can be transmitted to the personal computer 9 via the PC interface unit 10, waveforms can be displayed on the display of the personal computer 9, complicated and sophisticated data analysis can be performed by the personal computer 9, and data can be stored on the hard disk of the personal computer 9. Can be.

Second Embodiment A second embodiment described below is a dual port RAM.
The hardware detects that data is simultaneously read from or written to the same address from the two ports of 1.

FIG. 5 is a block diagram of a second embodiment of the data bus monitor device 100B. The data bus monitoring device 100B of the second embodiment includes an ECU interface unit 2
The configuration is the same as that of FIG. 1 except that a read / write duplication determination unit 11 is newly provided between the CPU and the CPU 3 in the monitor.

FIG. 6 is a circuit diagram showing the details of the read / write duplication determination section 11. As shown in FIG.
Reference numeral 1 denotes an address match signal output unit 12, a D flip-flop 13 (hereinafter, referred to as DF / F), and an address selector 1.
4, a buffer 15 and an OR gate 16. The address match signal output unit 12 outputs a low-level signal when the same address value is input to two ports of the dual port RAM 1. The write enable signal NWE output from the ECU interface unit 2 is input to the clock terminal CLK of the DF / F 13.
The D terminal of the DF / F 13 changes to a low level when the output of the address match signal output unit 12 is at a low level and the read enable signal NRD output from the CPU 3 in the monitor is at a low level. The interrupt signal NDAR signal output from the Q terminal of the DF / F 13
U3, which is connected to the interrupt terminal of U3.
Is interrupted.

The address selector 14 is a CPU in the monitor.
3 is mapped on the main memory and the CPU in the monitor
When 3 outputs the mapped address, the address selector 14 outputs a low-level signal. When the address selector 14 outputs a low-level signal, the buffer 15 is enabled, and the DAR signal output from the NQ terminal of the DF / F 13 is input to the data input terminal of the CPU 3 in the monitor.

FIG. 7 shows an in-monitor CP when an interrupt is not input to the in-monitor CPU 3 (NDAR = high level).
FIG. 8 is a flowchart showing the operation of U3, and FIG.
When an interrupt enters U3 (NDAR = low level)
Is a flowchart showing the operation of the second embodiment, and the operation of the second embodiment will be described based on these flowcharts. It should be noted that the CPU 3 in the monitor immediately receives the interrupt as shown in FIG.
When no interrupt is issued, the process shown in FIG. 7 is performed at predetermined time intervals determined by a timer interrupt.

In step S101 of FIG. 7, the variable m is initialized to "1". This variable m measures the number of times the interrupt processing of FIG. 8 is continuously performed. That is, FIG.
After performing the interrupt processing of FIG.
Once the variable m is initialized to "1". In step S102 of FIG. 7, the data in the dual port RAM 1 is read and stored in the internal register R. Thereafter, the CPU 3 in the monitor performs data processing. On the other hand, when an interrupt signal is input to the monitor CPU 3, the monitor CP
U3 starts the interrupt processing of FIG.

First, in step S201, the interruption by the interruption signal NDAR is temporarily masked.
That is, even if an interrupt is input again, the interrupt is not accepted. In step S202, it is confirmed whether reading and writing are to be performed simultaneously at the same address. For this confirmation, the CPU 3 in the monitor outputs the address of the address selector 14 mapped to the main memory and sets the output of the address selector 14 shown in FIG. Detect signal level. If the DAR signal is at a high level, it is determined that reading and writing to the same address are performed simultaneously.

The process in step S202 is a protection process in the case where an interrupt is accidentally input for some reason.
If there is little possibility of malfunction, it may be omitted. In step S203, “1” is added to the variable m. In step S204, it is determined whether the variable m is _{equal to} or greater than mmax.
If the determination is affirmative, the process proceeds to step S205, where error processing is performed. On the other hand, if the determination in step S204 is negative, the process proceeds to step S206, where an interrupt input can be accepted, and the process returns.

The operation of the second embodiment described above can be summarized as follows.
3, a read / write duplication determination unit 11 is provided. When reading / writing is simultaneously instructed to the same address of the dual port RAM 1, the CPU 3 in the monitor is interrupted.
The CPU 3 in the monitor waits for the reading process of the dual port RAM 1 when an interrupt occurs. Further, the CPU 3 in the monitor measures the number of times interrupts are continuously taken, and if the number exceeds a predetermined number, determines that an abnormality has occurred and stops the data processing.

As described above, in the second embodiment, it is determined by the hardware whether reading or writing is instructed at the same address of the dual port RAM 1 at the same time, so that the determination can be made quickly and accurately. .

Third Embodiment A third embodiment is a modification of the second embodiment. The circuit configuration of the read / write duplication determination unit 11 of the second embodiment is different from that of the second embodiment. It is a simplification. FIG. 9 is a circuit diagram of the read / write duplication determination unit 11A of the third embodiment. As shown, the read / write duplication determination unit 11A includes an address match signal determination unit 12 and an OR gate 16.

In FIG. 9, when reading and writing are simultaneously instructed to the same address of the dual port RAM 1, a low level signal is output from the address coincidence signal judging section 12. At this time, when the ECU interface unit 2 outputs the low level write enable signal NWE, the NDAR signal output from the OR gate 16 becomes low level.
The NDAR signal is input to the wait terminal of the CPU 3 in the monitor.
PU3 stops reading the dual port RAM1.

As described above, the third embodiment uses the DF / F13
The circuit configuration is simpler than that of the second embodiment because of the absence of the address selector 14. However, when reading and writing are simultaneously instructed to the same address of the dual port RAM 1, the reading of the dual port RAM 1 is temporarily stopped, and the same processing as in the second embodiment can be performed. However, since there is no way to check even if the wait signal NDAR is erroneously input, the second embodiment is more desirable when operating in a noisy place or the like. In the third embodiment, if the CPU 201 in the ECU enters the writing process immediately after the CPU 3 in the monitor enters the reading process, the reading process may not be allowed to wait. 4, the contents of the dual port RAM 1 may be read a plurality of times.

The ECU interface unit 2 of each of the above embodiments
Although the example in which the timing and the voltage level of each signal are changed has been described, other electrical characteristics such as a change in the voltage amplitude may be changed. In the first embodiment, FIG.
And in the second and third embodiments, the circuits of FIGS. 6 and 9 are used to prevent simultaneous reading and writing to the same address of the dual port RAM 1. However, a dual port RAM having a bus arbitration function is used. May be.

In the embodiment configured as described above, E
The CU interface unit 2 uses the CP
U3 is a control means, 7 seg LED7 and D / A converter 8 are a display collection means, a personal computer 9 is an analysis device,
The read / write duplication determination unit 11 corresponds to the read / write duplication detection means.

[0048]

As described in detail above, claim 1
According to the invention described in the third aspect, all data written by the controller in the RAM is stored in the dual port RAM, so that even if the controller performs complicated and advanced calculations, the calculation results of the controller can be analyzed in detail. . In addition, since the electrical characteristics such as the timing of various signals output from the controller are changed according to the type of the dual-port RAM by the interface unit, data analysis of various types of controllers having different electrical characteristics can be performed. It can be used and has excellent versatility. further,
Due to the structure of the dual-port RAM, if data of the same address is simultaneously read and written, the read data may become indefinite. Therefore, when reading the contents of the dual-port RAM, the data of the same address is continuously read a plurality of times. Data processing is performed only when the read data matches a predetermined number of times consecutively. Therefore, even if the same address in the dual port RAM is simultaneously read and written, erroneous data is not read. According to the second, third, and fourth aspects of the present invention, the data processed by the control means is analyzed by the analysis device, so that waveform display, complicated data analysis, and the like can be performed. The results can be analyzed in detail. In particular, according to the third aspect of the present invention, when simultaneous reading and writing to the same address of the dual port RAM is attempted, an interrupt signal is input to the control means to delay the reading timing, so that the same address is simultaneously read and written. There is no fear. Claim 4
According to the invention described in (1), when reading the contents of the dual port RAM, the data at the same address is continuously read a plurality of times, and the data is processed only when the read data matches the predetermined number of times continuously. Therefore, even if the same address of the dual port RAM is simultaneously read and written, data can be read without error.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a data bus monitor device according to the present invention.

FIG. 2 is a diagram showing mapping of main memories of a CPU in an ECU and a CPU in a monitor.

FIG. 3 is a diagram showing write timings of a RAM in an ECU and a dual port RAM.

FIG. 4 is a flowchart showing read processing of a dual port RAM according to the first embodiment;

FIG. 5 is a block diagram of a data bus monitor device according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a second embodiment of a read / write duplication determination unit.

FIG. 7 shows a dual-port RA when an interrupt is not input
9 is a flowchart showing a reading process of M.

FIG. 8 shows a dual port RAM when an interrupt occurs.
5 is a flowchart showing a reading process of FIG.

FIG. 9 is a circuit diagram of a third embodiment of a read / write duplication determination unit.

FIG. 10 is a block diagram of a conventional data bus monitor device.

[Explanation of symbols]

 Reference Signs List 1 dual port RAM 2 ECU interface unit 3 CPU 4 timer 5 ROM 6 RAM 7 7 seg LED 8 D / A converter 9 personal computer 10 PC interface unit 100A data bus monitor device 200 ECU

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 11/34 G06F 11/22 350 G06F 13/00 301

Claims (4)

(57) [Claims] 1. A data bus monitor device for monitoring data written to a RAM by a controller to be inspected and analyzing the operation of the controller, wherein the data bus monitor device has a storage capacity equal to or larger than a storage capacity of the RAM, When writing data to the RAM, a dual port RAM that writes the data at substantially the same timing
And electrical characteristics including timings of an address signal, a data signal, and a write control signal which are interposed between the controller and the dual port RAM and output from the controller according to the type of the dual port RAM. Interface means for changing, and duplicating data at the same address in the dual port RAM.
Read several times in succession, and read the data
Only when there is a match, the read data is added.
A data bus monitor device, comprising: a control unit for performing an operation; and a display collection unit for displaying or collecting data processed by the control unit. 2. A controller to be inspected writes in a RAM.
Monitor the input data and solve the operation of the controller.
A data bus monitor device that has a storage capacity equal to or larger than the storage capacity of the RAM;
When the controller writes data to the RAM, the
Dual port RAM for writing the data in the memory
Between the controller and the dual port RAM
The address signal output from the controller
Signal, data signal and write control signal timing
The electrical characteristics including
An interface means for changing the data written in the dual port RAM,
At the timing of
Control means for performing machining and analysis for analyzing data processed by the control means
Data bus monitor device, characterized in that it comprises a device. 3. A data bus according to claim 1, wherein :
In the monitor device, the same address of the dual port RAM is simultaneously
When reading / writing is instructed to the control means, an interrupt signal is sent to the control means.
Read / write duplication detecting means for transmitting a signal, and the control means, when the interrupt signal is inputted,
Delay read timing of dual port RAM
Data bus monitor device, characterized in that that. 4. A data bus monitor device according to claim 2.
The control means may include the same address of the dual port RAM.
Address data is read continuously multiple times, and the read data
Only when the data match the specified number of times
Data bus characterized by processing the output data
Monitor device.