JP3128843B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus.

[0002]

2. Description of the Related Art In recent years, information processing apparatuses such as RISC microprocessors have a large-capacity register file to reduce the number of times of loading / storing a memory, thereby preventing a decrease in instruction execution efficiency due to memory access. .

An example of the configuration of a general-purpose register of the above-described conventional information processing apparatus will be described below with reference to the drawings. This conventional example is a microprocessor Am of the AMD company.
This is a configuration of a general-purpose register adopted in the 29000.

As a general-purpose register, the Am29000 has 64 global registers having absolute addresses and 128 local registers having relative addresses. FIG. 13 shows the address mechanism of the local register. In FIG. 13, reference numeral 21 denotes a 3-port register file, 22, 23, and 24 adders, and 25 a stack file.
This is a dedicated register for storing pointer data.

The operation of the address mechanism of the local register configured as described above will be described below.

First, as shown in FIG. 14, the instruction format of the operation instruction in the Am29000 has an operation code of 8 bits, and a general-purpose register is specified by 8 bits for each of two operand sources and operand destinations. If the value of the operand field is 0 or more and 127 or less, the local register is set to 12
If the number is 8 or more, the global register is accessed.

The 128 local registers add the register stack pointer and the register number specified as the instruction operand by an adder, and access the resulting value as the register number. Such a dynamic register address mechanism realizes a stack cache mechanism using a local register as a stack cache.

Now, in a computer of the VLIW or superscalar system, since only one context is processed in parallel at the same time, it is common that each operation unit shares a general-purpose register by multiporting. On the other hand, in a conventional parallel computer that processes a plurality of contexts in parallel, a general-purpose register set is prepared for each element processor, and one element processor directly accesses registers of another element processor. There was no. That is, although the element processors may share the memory, they do not share the register. Therefore, no technique has been reported in such a case.

[0009]

However, the above configuration has the following problems. First,
The number of global registers is fixed at 64. In addition, when a plurality of environments are stored in the global register, register access is performed using the absolute register number. Therefore, special consideration must be given to the arrangement of data on the register. Next, the local registers adopt dynamic addressing, thereby obtaining the possibility of dynamically relocating data on the registers, but the number of the registers is one.
It is limited to 28. Since the number of registers is closely related to the instruction length, there has been a problem that the number of accessible registers is generally determined by the length of the instruction field used for register specification.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides an information processing apparatus having a high degree of freedom in register use and high use efficiency.

In particular, the invention according to claim 1 provides an information processing apparatus capable of accessing a large number of registers without increasing the instruction word length and capable of freely setting global / local discrimination when using registers. Is what you do.

[0012] The invention according to claim 2 provides an information processing apparatus having a function of efficiently sharing the same register space in a plurality of contexts in a multiprocessor.

According to a third aspect of the present invention, there is provided an information processing apparatus which solves the problem of the number of register accesses in the first aspect by slightly increasing the amount of hardware.

According to a fourth aspect of the present invention, there is provided an information processing apparatus having a function of efficiently and selectively sharing data in a register in a plurality of contexts in a multiprocessor.

[0015]

According to a first aspect of the present invention, there is provided an information processing apparatus, comprising: a register file including a plurality of registers; a register for storing a register number for the register file; First operation means for calculating a first register number for the register file by operation of a register and a first value specified in an instruction operand field; and in the register file, Second operation means for obtaining a second register number for the register file by performing an operation on the contents of the register and the second value in the instruction operand field.

According to a second aspect of the present invention, there is provided an information processing apparatus comprising: a register file shared by a plurality of processors and comprising a plurality of registers; a register prepared for each of the processors and storing a register number for the register file; A first operation means provided for each processor for obtaining a first register number for the register file by performing an operation on the register and a first value specified in an instruction operand field; In the register file, a second register number for the register file is obtained by calculating the contents of the register having the first register number and a second value in the instruction operand field. Arithmetic means and the contents of one of the registers 2 And a copying means for copying the other registers of the serial register.

According to a third aspect of the present invention, there is provided an information processing apparatus comprising: a register file including a plurality of registers;
A register set for storing a register number for a file; and a register file obtained by calculating a value of one register in the register set specified by an instruction operand field and a value specified by the instruction operand field. Operation means for obtaining a register number for 1;

An information processing apparatus according to claim 4, wherein a register file shared by a plurality of processors and comprising a plurality of registers, and a register set prepared for each processor and storing a register number for the register file And the register, which is prepared for each processor and specified by an instruction operand field.
The value of one register in the set and the instruction operand
Calculating means for calculating a register number for the register file by calculating with a value specified by a field;
Copying means for copying the contents of the registers in one of the register sets to the registers of the other register set.

[0019]

According to the present invention, since the number of a register to be accessed is calculated using the contents of the register according to the above configuration, a large number of registers can be obtained without increasing the number of bits of a field for specifying a register in an instruction word. Can be used efficiently.

Further, a mechanism is provided in which the segment table is arranged on the register and the contents of the dedicated register indicating the position of the table are copied between the processors.
The task for sharing the segment table at high speed can be performed, and therefore, the overhead for sharing the same register space in a plurality of contexts can be reduced.

Further, by storing the segment table stored in the general-purpose register in the special-purpose register, the number of accesses to the general-purpose register at the time of register access is reduced, so that the address calculation of the register number can be speeded up. Therefore, it is possible to access the general-purpose register at higher speed.

In addition, since a mechanism for selectively copying information in the segment table between processors is provided, a task of partially sharing the register space between a plurality of contexts can be performed at high speed, and more flexibly and efficiently. It is possible to use a large-capacity register.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An information processing apparatus according to one embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an information processing apparatus according to a first embodiment of the present invention. In FIG. 1, 11
Is an instruction fetch unit, 12 is an instruction decoding unit,
13 is a register access unit, 14 is an operation unit, 15 is a load / store unit, 16 is a processor, and 17 is a register file.

The operation of the information processing apparatus configured as described above will be described. The processor 16 fetches an instruction in the instruction fetch unit 11, then decodes the fetched instruction in the instruction decoding unit 12, and, based on the decoded result, the register access unit 13, the operation unit 14, and the load / store. Execute the instruction in unit 15; When register access is performed in a load / store instruction and an operation instruction, the register access unit 13 controls the access.

FIG. 2 shows the register access unit 13
In the figure, reference numeral 41 denotes a 3-port register file, 42 denotes a multiplexer, 43 denotes an adder, 44 denotes a latch, and 45 denotes a segment table register.

The operation of the register access unit configured as described above will be described.

FIG. 3 shows an example of an instruction format of an operation instruction in the information processing apparatus according to the present invention, which is performed using a 3-bit segment table entry and a 5-bit offset for register designation of each operand. . Therefore, the maximum number of entries in one segment table is 8, and one segment is composed of 32 registers. FIG. 4 shows an outline of the register addressing mechanism. FIG. 4 shows an example in which attention is paid to only one source register specification, in which src1s represents a segment table entry and src1p represents an offset.
The segment table register 61 stores the location of the segment table 63 provided on the register file 62, and reads an entry in the segment table 63 by regarding src1s as an offset therefrom. Each entry in the segment table 63 stores a segment base, and performs data access using the sum of the segment base value of the entry specified by src1s and src1p as a register number.

The register file 41 of this embodiment shown in FIG. 2 is a set of 1024 registers, and requires 10 bits to identify the register. The segment table register 45 is a 7-bit dedicated register.
By bit concatenation with the 3-bit segment table entry number in the instruction word, a 10-bit register number is obtained. For this reason, the segment table (63) must be aligned on an 8-word boundary on the register file 41 (62). The register number thus obtained is used as an address input of the register file 41 through the multiplexer 42, and the read segment base value is temporarily held in the latch 44. Next, the latched segment base value and the offset in the instruction word are added to the adder 43.
, And accesses the register to be operated as the address of the register file.

As described above, according to this embodiment, a register file is divided into logical segments, a segment table for managing the segment is provided on a register, and a register addressing mechanism is provided. You can:

(A) Although 8 bits are used to designate one register in an instruction word and only 256 registers can be used at a time, the contents can be implemented by rewriting the contents of the entry in the segment table. You can access all the registers you are using.

(B) The global / local registers can be freely set for each segment, and the registers can be effectively used.

(C) Since segments may overlap each other, there is no restriction that 32 segments must be used as a set. For example, if the number of registers required locally in an application program is 20, the remaining Twelve registers can be used as global registers. Similarly, the segment table does not necessarily require eight entries of registers. For example, if three segments are sufficient, the remaining five
These registers can be used as general-purpose registers.

(D) By rewriting the segment table at the time of calling a function / procedure, a stack cache can be realized.

(E) By rewriting the segment table register, it is possible to handle a segment table having eight or more entries.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a configuration diagram of the register access unit in the second embodiment of the present invention. In FIG. 5, reference numeral 71 denotes a 6-port register file, 72 denotes an adder, and 73 denotes a segment table register. The operation is almost the same as that of the first embodiment. However, since the register file has six ports, there is no need to latch the segment base value, and the time required for accessing necessary data is reduced by the first time. It can be shortened compared to the embodiment.

In the first embodiment and the second embodiment, the portion for performing the bit connection may be replaced by an adder. In this case, there is no need to align the segment table with eight word boundaries. Also, the adders 43 and 72
May be removed and this part may be bit-connected.

Next, a third embodiment of the present invention will be described with reference to the drawings. The present embodiment employs a configuration in which a plurality of processors 16 share one large-capacity register file 17 as shown in FIG. Therefore,
The register file 17 is multi-ported and multi-banked to reduce the occurrence of register access contention from each processor 16.

The operation of the information processing apparatus configured as described above will be described. The operation of each processor 16 is the same as that described in the first embodiment.

As for the register access unit 13, the same addressing mechanism and configuration as those of the first embodiment are used in the individual processors 16 as shown in FIG. 2 (or FIG. 4). ) Differs in the configuration around the segment table register 45 (73).

Hereinafter, the different configuration will be described. FIG. 7 shows a connection configuration between segment table registers in each register access unit when the number of processors is four. In FIG. 7, 81, 8
2, 83 and 84 are segments of each processor, respectively.
The table register 85 is a multiplexer.

The configuration shown in FIG.
Registers are connected in a complete graph, and copying between the segment table and registers can be performed most quickly and flexibly. For example, the segment table register 82
Are stored in the segment table registers 81 and 8
3, 84 can be simultaneously copied. The contents of the segment table register 81 are stored in the segment
At the same time as copying to the table register 83, the contents of the segment table
It can also be copied to the table register 82.

As described above, according to this embodiment, a segment table for register segment management is provided on the register file, and a mechanism for copying the contents between the segment table registers of each processor is provided. Provision makes it possible to:

(A) The same register space can be shared on different processors at high speed.

(B) A segment table can be shared between processors, and a plurality of tables having the same contents are not provided, so that registers can be used efficiently.

Next, a fourth embodiment of the present invention will be described with reference to the drawings. The configuration of the information processing apparatus in this embodiment is the same as that of the third embodiment except that the connection configuration between the segment tables and registers shown in FIG. 7 is replaced with the configuration shown in FIG. In FIG. 8, 9
1, 92, 93 and 94 are segment table registers of each processor, 95 is a control circuit, and 96 is an instruction decoding unit of each processor.

In FIG. 8, the segment table registers 91, 92, 93 and 94 are constituted by latches in hardware, and the signals G0 and G of the control circuit 95 are provided.
Depending on whether the value of 1, G2, G3 is 1 or 0, each of them takes a transmission or holding state. The control circuit 95, based on a request signal from the instruction decoding unit 96 of each processor,
The value of each signal of G0, G1, G2, G3 is determined. FIG.
Shows the logic of the control circuit 95. In FIG. 9, it is assumed that the suffix of each signal name is expressed by a remainder of four. The request signal Ri from the instruction decoding unit 96 indicates how many other segment table registers to copy the contents of the segment table register of the own processor. For example, (R1, R2, R3, R4) = (0,
(0, 2, 0), (G1, G2, G3, G4) =
(1, 0, 0, 1), and the contents of the segment table register 93 are stored in the segment table register 9
4. Copy to 91. Also, (R1, R2, R3, R
4) = (1,0,1,0), then (G1, G2, G
3, G4) = (0, 1, 0, 1) and the segment
The contents of the table register 91 are copied to the segment table register 92, and at the same time, the contents of the segment table register 93 are copied to the segment table register.
Copy to register 94. In FIG. 9, a combination of request signals not shown in FIG. 9 results in an error.

In the third embodiment, when the number of processors is increased, the number of connections increases and the amount of hardware increases. However, in the fourth embodiment, as described above, each segment table By limiting the connection between registers, copying between segment table registers can be performed with a small amount of hardware.

Next, a fifth embodiment of the present invention will be described with reference to the drawings. The information processing apparatus of the present embodiment
This corresponds to an apparatus constituted by one processor and a register file shown in FIG.

FIG. 10 shows the configuration of the register access unit in this embodiment.
Port register file, 112 is an adder, 113
Is a multiplexer, and 114 is a segment base register.

The operation of the register access unit configured as described above will be described.

Similarly to the information processing apparatus of the first embodiment, the information processing apparatus of this embodiment employs the instruction format of the operation instruction shown in FIG. 3 and uses a 3-bit register for each operand. Assume that a segment table entry and a 5-bit offset are used. The information processing apparatus according to the present embodiment includes eight segment base registers 114, and the multiplexer 113 selects one of the eight segments base registers 114 using three bits for specifying a segment table entry. Each segment base
The register 114 stores the first register number of each register segment configured on the register file. Therefore, in the information processing apparatus according to the present embodiment, the segment table is not stored in the register file as in the information processing apparatuses according to the first and second embodiments. This is realized by using the base register 114. The base value and offset of the selected segment are summed by the adder 112 to determine the number of the register to be accessed.

As described above, according to this embodiment, since the register file is not accessed in the process of register addressing, the register file is accessed faster than in the information processing apparatuses of the first and second embodiments. Can access.

In the above embodiment, if the segments are aligned on the eight-word boundary, the adder 112 is removed, and
Bit connection may be performed.

Finally, a sixth embodiment of the present invention will be described with reference to the drawings. The information processing apparatus according to the present embodiment has a configuration as shown in FIG. 6, similarly to the information processing apparatus according to the third embodiment. In FIG. 6, each processor 1
6 uses the same register access unit 13 as that shown in the fifth embodiment.
The configuration around the segment base register 114 at 0 is different.

FIG. 11 shows a connection configuration between segment base registers in each register access unit when the number of processors is four. In FIG. 11, reference numeral 121 denotes a segment base register;
2 is a control circuit, 123 is a command decoding unit, 124, 1
25, 126 and 127 are processors.

The operation of the segment base register copy mechanism configured as described above will be described.

The control circuit 122 includes an instruction decoding unit 123
Performs the copy control of the segment base register based on the signal from. In the control circuit 122, R, M,
P and U are input signals, and G, Q and D are output signals. FIG. 12 shows the logic of the control circuit 122. In the figure, “:” indicates bit connection, and “*” indicates don't care. R is the number of processors to be copied. For example, if R = 2 in the processor 126, the contents of the segment base register 121 of the processor 126 are copied to the segment base registers 121 of the processors 127 and 124. Will be. However, at this time, instead of copying the contents of all eight segment base registers, this copying is selectively performed using the mask signal M. M is a signal of 8 (number of segment base registers) bits, each bit corresponding to an individual segment base register. Only the segment base register corresponding to the bit in which 1 is set in M is to be copied.
Signals P and Q are for propagating the value of M one after another in a processor connected in a ring as shown in FIG. Signals U and D are for transmitting a copy request between processors, and are both 3-bit (the number of processors minus 1) bits. For example, if R = 2 in the processor 126, the controller of the processor 126 outputs D = 110. In the processor 126, the first bit, second bit, third bit of D
The bits correspond to the processors 127, 124, and 125, respectively. The processor 127 receives the value of D in the processor 126 as U. Important to the processor 127 is the first bit of U,
The bits and below propagate to the processor 124 as they are. Specifically, 0 is bit-connected to the value 10 that is equal to or less than the second bit, and D = 100. That is, in the processor 127, the first bit, the second bit, and the third bit of D correspond to the processors 124, 125, and 126, respectively. Either P or M is output to the signals G and Q by the signal R or U. Each segment base register consists of a latch,
Only the segment register corresponding to the bit in which the flag is set captures the value. Other combinations exist in addition to the input combinations shown in FIG. 12, but those other than FIG. 12 are errors.

As described above, according to the present embodiment, the segment base register of each processor is ring-connected between the processors, and a control circuit for copying is provided. A selective copy of the segment base register can be made.

Although the information processing apparatus in the third, fourth, and sixth embodiments has been described as being composed of a plurality of processors, the present invention is limited to the case where these processors are physically plural. is not. Even in a pipelined MIMD computer that interleaves each instruction of a plurality of instruction streams that can be executed in parallel and processes them with one physical instruction pipeline, if attention is paid to the processing of each instruction stream, a logical processor can be realized. It can be regarded as having a plurality. Therefore, the present invention can be applied even in this case,
It is not excluded from the scope of the present invention.

The present invention is not limited to the above-described embodiment, and various modifications can be made based on the gist of the present invention, and these are not excluded from the scope of the present invention.

[0062]

As described above, the present invention provides a register addressing mechanism based on a register segment and an inter-processor copy control circuit for dedicated registers used in the register addressing mechanism.
A large-capacity register file can be used efficiently and flexibly by one or more processors.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an information processing apparatus according to a first embodiment of the present invention;

FIG. 2 is a configuration diagram of a register access unit of the information processing apparatus according to the first embodiment.

FIG. 3 is an explanatory diagram of an instruction format of the information processing apparatus according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram of a register addressing mechanism of the information processing apparatus according to the first embodiment.

FIG. 5 is a configuration diagram of an information processing apparatus according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of a register access unit of an information processing apparatus according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a connection configuration between segment table registers according to a third embodiment of the present invention;

FIG. 8 is a connection configuration diagram between segment table registers according to a fourth embodiment of the present invention.

FIG. 9 shows a segment table in the fourth embodiment.
Relationship diagram showing logic of copy control device between registers

FIG. 10 is an explanatory diagram of a register addressing mechanism of an information processing apparatus according to a fifth embodiment.

FIG. 11 shows a segment according to a sixth embodiment of the present invention.
Connection diagram between table and register

FIG. 12 is a relationship diagram showing the logic of a copy control device between segment tables and registers in the sixth embodiment.

FIG. 13 is a configuration diagram of a register addressing mechanism of a conventional information processing apparatus.

FIG. 14 is an explanatory diagram of a command format of a conventional information processing apparatus.

[Explanation of symbols]

11 Instruction Fetch Unit 12 Instruction Decoding Unit 13 Register Access Unit 14 Operation Unit 15 Load / Store Unit 16 Processor 17 Register File 41 Register File 42 Multiplexer 43 Adder 44 Latch 45 Segment Table Register 61 Segment Table register 62 Register file 63 Segment table 71 Register file 72 Adder 73 Segment table register 81, 82, 83, 84 Segment table register 85 Multiplexer 91, 92, 93, 94 Segment table register 95 copy control circuit 96 instruction decoding unit 111 register file 112 adder 113 multiplexer 114 segment Base register 121 segment base register 122 copy control circuit 123 instruction decoding unit 124, 125, 126, 127 Processor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 9/30-9/355 G06F 12/00-12/06

Claims (3)

(57) [Claims] 1. A register file including a plurality of registers, a register storing a register number for a register in the register file , a register storing the register number, and a first register specified by an instruction operand field. First operation means for calculating a first register number for the register file by operation with a value; and in the register file, the contents of a register corresponding to the first register number and the instruction operand
An operation with a second value in the field causes the register
Second operation means for obtaining a second register number for the file, wherein when the instruction operand is a register designation, the register file having the second register number obtained by the second operation means register information processing apparatus that accesses the. 2. A register file shared by a plurality of processors and comprising a plurality of registers; and a register file prepared for each of the processors,
A register for storing a register number for a register in the memory, and a register prepared for each processor and storing the register number
First operation means for obtaining a first register number for the register file by operation of a register to be executed and a first value specified in an instruction operand field; and a second computing means for obtaining a second register number to said register file by operation of the second value in the first register number and corresponding content with the instruction operand fields of the register, the register and a copying means for copying the contents of one register of the register for storing the number in the other registers of the registers for storing the register number, in the case of operand register specification instruction to be executed in each processor correspond with the second register number obtained by said second arithmetic means Information processing devices that access the registers in the serial register file. 3. is shared by multiple processors, the register file comprising a plurality of registers, for each of the processor, stores the register number register
And a register set prepared for each of the processors, and calculating the value of one register in the register set specified by the instruction operand field and the value specified by the instruction operand field. comprising calculating means for determining a register number to the register file, and a copy means for copying the contents of the registers in one register set of the register set in the register in the other of said register set, each processor operand of the instruction to be executed in the in the case of the register specified, register information processing apparatus that accesses the in the register file with register number obtained by said computing means.