JP3127980B2 - Motion compensation arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion compensation arithmetic unit used for detecting motion between images in a moving image encoding process.

[0002]

2. Description of the Related Art A moving image has a plurality of temporally continuous frames. The motion compensation operation device is a device that detects a position in a moving image from which a pixel block in a certain frame has moved in another frame. FIG. 4 shows a template 1 and a search area 2 to be detected.
Is shown. Here, template 1 is a pixel block in a certain frame, and search area 2 is a pixel block in another frame.

A rectangular area of any size can be considered for both the template 1 and the search area 2. Hereinafter, a case where the template 1 has 4 pixels × 4 lines and the search area 2 has 12 pixels × 12 lines will be described. . a _{0, 0} ~a _{3, 3}
The pixels in the template _{1, x 0, 0 ~x b} , b ( expressed this subscript in hexadecimal.) Is a pixel in the search region 2. In this specification, a unit of the number of pixels in the horizontal direction is called a pixel, and a unit of the number of pixels in the vertical direction is called a line.

FIG. 5 is a diagram for explaining a method of motion detection by the full search method. The entire area of 4 pixels × 4 lines that can be taken from the search area 2 is cut out, and the difference between the pixel in the area of 4 pixels × 4 lines and the pixel at the corresponding position in the template 1 is calculated as the difference absolute value. Alternatively, evaluation is performed using a difference square value or the like, and the sum of the evaluation values is obtained. One pixel or one
The entire area of 4 pixels × 4 lines shifted in line, that is, 8
This sum is calculated for 64 (= 8) areas, and it is assumed that the template 1 has moved from the area having the smallest sum.

[0005] Since what is used as the evaluation formula is not the essence of the present invention, the case where the absolute difference value is used will be described below. Further, the motion compensation arithmetic device according to the present invention is often realized by a synchronous circuit, but the synchronous circuit normally operates in synchronization with CK (clock). Therefore, the unit of operation is hereinafter referred to as CK.

FIG. 6 is a diagram showing a configuration of a difference absolute value sum calculation part in the first conventional example of the motion compensation arithmetic unit. P _ij (i = 0 to 3, j = 0 to 3) indicated by reference numeral 3 is a circuit (arithmetic unit) for calculating the absolute value of the difference between the template 1 and the corresponding pixel in the search area 2. The pixels in the search area 2 which correspond to the pixels in the one-to-one correspondence, hold the pixels a _ij in the template 1, and broadcast (supply) for each row are taken in for each CK, and the difference absolute value Is calculated. 4 is a register, 5 is an adder, and 6 is a summing circuit.

FIG. 7 is a timing chart for calculating the sum of absolute differences between the area of 4 pixels × 4 lines cut out from the upper left corner of the search area 2 and the pixels in the template 1 in the apparatus of FIG. FIG. As shown, 0CK
, 1CK, 2CK, 3CK in the first row,
The sum of the absolute difference values in the second, third, and fourth columns is calculated.
The partial sum S _i of each row is obtained at CK. And 4CK
Their sum is taken by eye.

FIG. 8 is a diagram for explaining a delay line 7 for supplying pixels in the search area 2 to the apparatus of FIG. Of the pixels in the search area 2 broadcasted (supplied) at the same time for four rows, the pixels in the top row are discarded, and the pixels in the remaining three rows are each 1
The signals are sequentially input to the delay line 7 on the row. These pixels are 12
After CK, it is used again for calculating the absolute difference sum.

[0009] The above-mentioned motion compensation arithmetic unit is described in, for example, T. Yoshino, S. Foster, J. Lee, L. Cheng, V. Ponukumat.
i, A.Khazeni, R.Hinchley, K.Pang, ∧A 54MHz Motion Est
imation Engine for Real-Time MPEG Video Encoding ",
1994 IEEE Proceedings of Consumer Electronics, PP.7
It is described in 6-77.

FIG. 9 is a diagram showing a configuration of a difference absolute value sum calculation part in the second conventional motion compensation arithmetic unit. P
The functions of _ij 3, register 4, and adder 5 are the same as those of the above-mentioned first conventional example.

FIG. 10 shows a search area 2 in the apparatus shown in FIG.
FIG. 7 is a diagram showing timings when calculating a sum of absolute difference values between a region of 4 pixels × 4 lines cut out from the upper left corner of FIG. S _{0: j} in the drawing means the sum of the partial sums S _i of each row from the first row to the (j−1) th row. In the apparatus shown in FIG. 9, the input of the pixels in the search area 2 is delayed by 1 CK for each row,
The timing at which the partial sum S _i of each row is obtained is set to 1 for each row.
CK is delayed by CK, and the partial sum S _{i of} each row is sequentially added from the 4th CK to the 7th CK.

FIG. 11 is a diagram for explaining the delay line 8 for supplying the pixels in the search area 2 to the apparatus of FIG. The number of delay CKs of the delay line 8 is different from that shown in FIG.
It is one. This is because the number of pixels in the search area 2 in the horizontal direction is 12
One less.

The second conventional example of the motion compensation arithmetic unit is described in, for example, E. Chan, S. Panchanathan, ∧Motion Est.
imation Architectuer for Video Compression ", IEEE
Trans.on Consumer Electronics, Vol.39, No.3, PP.292-2
97, 1993.

[0014]

However, in the first conventional example, there is a problem that the summation circuit 6 having a complicated structure and a large delay time is required to add the partial sums Si of the respective rows. . Further, in the second conventional example, since the partial sums Si of the respective rows are sequentially added while being delayed by the register 4 for each 1CK, the delay time of this portion is small, but the structure is not yet a completely repetitive structure.

The size of the template is a pixels × b.
When the size of the line and the search area is c pixels × d lines,
In the first conventional example, the delay line of c words is (b-
1) In the second conventional example, (b-1) delay lines of (c-1) words are required, and there is a problem that the amount of hardware of the delay lines is large.

The present invention has been made in view of the above points, and an object of the present invention is to realize a portion for evaluating a difference between pixel values as a one-dimensional array having a simple and completely repetitive structure.
Another object of the present invention is to provide a motion compensation operation device in which the amount of hardware of the delay line is reduced.

[0017]

For this purpose, the present invention provides a template consisting of a pixel block of a pixel × b line in a certain frame and a c pixel × d in another frame.
In a motion compensation operation device including an operation device for evaluating a difference in value between pixels at corresponding positions between an a pixel × b line pixel block cut out from a search area formed of line pixel blocks, (B-1) delay means for delaying pixels by (ca) unit time are connected in series,
A delay means array for sending out a total of b pixels per unit time in total from the input pixels and the outputs of the delay means, and a group of b arithmetic elements comprising a number of arithmetic elements having the same configuration,
Means for holding the pixels present at the corresponding positions among the pixels of the a pixel × b line in the template in the a × b arithmetic units, and a one-to-one output from the delay means array
Means for supplying each of the b pixels sent to the corresponding b operation unit groups to all the operation units in the individual operation unit group, and the individual operation units hold the supplied pixels and the operation units The value difference between the pixels in the template and
An arithmetic unit array having means for adding the evaluation result of the arithmetic unit itself to the sum of the evaluation results input from the arithmetic unit at the previous stage and sending the result to the next arithmetic unit after one unit time It was configured to include

[0018]

According to the present invention, the size of the template is a pixel.times.
When the size of the b line and the search area is c pixels × d lines, a × b number of arithmetic units for evaluating the difference in pixel values and means for adding the arithmetic results of the arithmetic units and sending the result to the subsequent stage are repeated. It can be configured as a one-dimensional array having a side-by-side structure. Further, although the hardware amount of the delay line is (b-1), the number of words is reduced to (ca) words.

[0019]

Embodiments of the present invention will be described below. FIG. 1 is a diagram showing a configuration of a difference absolute value sum calculating circuit portion in the motion compensation operation device of the embodiment. P _ij 3 is a computing unit for calculating the absolute difference value, and four computing units of the same configuration are arranged, each of which holds a pixel x _{i, j} in the template 1 Have been. Then, the outputs of the individual arithmetic units 3 are added by the adder 5 to the operation result sent from the adder 5 at the preceding stage, and sent to the adder 5 at the next stage. The transmission to the next stage is performed via the register 4 for each CK.

FIG. 2 is a timing chart for calculating the sum of absolute differences between the pixel of the template 1 and the area of 4 pixels × 4 lines cut out from the upper left corner of the search area 2 in the apparatus of FIG. It is a figure for explaining. In the apparatus of this embodiment, the input of the pixels in the search area 2 is delayed by 4CK for each row, so that the timing of obtaining the partial sum S _{i of} each row is delayed by 4CK for each row. In this case, the calculation of the next lower row starts at the next CK at which the partial sum S _{i of} each row is obtained. Therefore, in this embodiment, since the partial sum S _{i of} each row can be added to the absolute value of the difference at the head of the next row, a one-dimensional array structure having continuous rows can be obtained.

FIG. 3 is a diagram for explaining the delay line 9 for supplying pixels in the search area 2 to the apparatus of this embodiment. The number of delay CKs of the delay line 9 is eight, which is four less than the number of pixels 12 in the horizontal direction of the search area 2.

In the above, the unit of the number of pixels in the horizontal direction is called a pixel, and the unit of the number of pixels in the vertical direction is called a line. The unit may be regarded as a pixel, and the same effect can be obtained even if the horizontal direction and the vertical direction are reversed. Also, in order to reduce the number of operations, pixels in a frame are often sub-sampled into a template and a search area. According to the present invention, the same effect can be obtained in this case.

As described above, according to the present invention,
When the size of the template is a pixels × b lines and the size of the search area is c pixels × d lines, the arithmetic unit for evaluating the difference of the pixel value and the arithmetic result of each arithmetic unit are added and sent to the subsequent stage. There is an effect that it can be realized as a one-dimensional array having a structure in which a × b units are repeatedly arranged. Further, there is an effect that the hardware amount of the delay line can be reduced to (c−a) words × (c−1).

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a difference absolute value sum calculation part in a motion compensation operation device according to an embodiment of the present invention.

FIG. 2 is a diagram showing timings for calculating an absolute difference sum between a pixel of a template and a region of 4 pixels × 4 lines cut out from an upper left corner of a search region in the apparatus of FIG. 1;

FIG. 3 is a diagram for explaining a delay line that supplies a pixel in a search area to the device of FIG. 1;

FIG. 4 is a diagram showing a template to be subjected to motion detection and a search area.

FIG. 5 is a diagram for explaining a method of motion detection by a full search method.

FIG. 6 is a diagram showing a configuration of a difference absolute value sum calculation part in the motion compensation operation device according to the first conventional example.

FIG. 7 is a diagram for explaining timing when calculating a sum of absolute differences between a pixel in a template and a region of 4 pixels × 4 lines cut out from the upper left corner of the search region in the apparatus of FIG. 6; It is.

FIG. 8 is a diagram for explaining a delay line that supplies pixels in a search area to the device of FIG. 6;

FIG. 9 is a diagram showing a configuration of a difference absolute value sum calculation part in the motion compensation operation device according to the second conventional example.

FIG. 10 is a diagram for explaining the timing when calculating the sum of absolute difference values between a region of 4 pixels × 4 lines cut out from the upper left corner of the search region and pixels in the template in the apparatus of FIG. 9; It is.

11 is a diagram for explaining a delay line that supplies pixels in a search area to the device of FIG. 9;

[Explanation of symbols]

1: Template of 4 pixels × 4 lines 2: Search area of 12 pixels × 12 lines 3: Circuit for calculating absolute difference between template and corresponding pixel of search area 4: Register 5: Adder 6: Summation Circuit 7: 12 word delay line 8: 11 word delay line 9: 8 word delay line

Claims (1)

(57) [Claims] 1. A template consisting of a pixel block of a pixel × b line in a frame and a pixel of a pixel × b line cut out from a search area consisting of a pixel block of c pixel × d line in another frame In a motion compensation arithmetic unit including an arithmetic unit for evaluating a difference in value between pixels at corresponding positions between a block and a block, a delay unit for delaying an input pixel by (ca) a unit time is provided by (b-1) A delay means array connected in series and sending out a total of b pixels per unit time from the input pixel and the output of each delay means, and b arithmetic operation units consisting of a arithmetic operation units having the same configuration Means for holding the pixels present at the corresponding positions among the pixels of the a pixel × b line in the template in the a × b arithmetic units, and a one-to-one output from the delay means array. With Means for supplying each of the b pixels sent to the b operation units to all of the operation units in the individual operation unit group, and the individual operation units are stored in the supplied pixels and the operation units. After evaluating the difference in value between the pixels in the template and the sum of the evaluation results input from the preceding stage computing unit, the evaluation result of the computing unit itself is added. A motion compensating device comprising: a computing device array having a sending unit; and a computing device comprising: