JP3127955B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device such as a MOS transistor in which a diffusion layer and a wiring are connected via a single crystal silicon layer provided on the surface of the diffusion layer. The present invention relates to an apparatus and a method for manufacturing the same.

[0002]

2. Description of the Related Art Due to the high integration of semiconductor devices due to miniaturization of semiconductor elements, for example, in DRAMs, the storage capacity has been increased four times in three years. High integration of semiconductor devices is not achieved simply by miniaturization of semiconductor elements. Wiring for interconnecting semiconductor elements and finer contact holes interposed between the wiring and the semiconductor elements are not provided. Is essential. Due to the requirement that the semiconductor element and the contact hole be formed with the minimum processing size (= F) defined by the design rule at that time, various structures related to the contact hole called a self-aligned contact hole have been proposed. I have.

[0003] The inventor of the present invention held the International Electron Devices, Inc. held in December 1995.
At the meeting, 665 of the proceedings IEDM-95
As described on pages 668 to 668 (lecture number 27.4.1), a new proposal for a self-aligned contact hole was made. This proposal proposes a method in which a single crystal silicon layer is self-aligned with an exposed surface of a diffusion layer provided on the surface of a silicon substrate having a main surface of {100} by anisotropic (not isotropic) selective epitaxial growth. Is formed. For example, anisotropic selective epitaxial growth of a single-crystal silicon layer on an N-type diffusion layer is performed by ultra-high vacuum chemical vapor deposition (ultra-high vacuum) on the order of 10 ⁻⁷ Pa.
m ・ chemical1 ・ vapor ・ depositi
on; UHV-CVD) apparatus, for example, at a temperature of 700 ° C. using disilane (Si ₂ H ₆ ) and phosphine (PH ₃ ) as a main source gas and a doping gas. The single-crystal silicon layer at this time is (<11
It grows mainly in the <100> direction perpendicular to the main surface of the silicon substrate (compared to the <0> direction).

Further, the present inventor has studied appropriate conditions for anisotropic selective epitaxial growth based on the above-mentioned report, and based on these, furthermore, designed a 0.25 μm design epitaxial growth.
Rule (minimum processing dimension; F = 0.25 μm (250n
m)) A trial production of a DRAM was performed. Referring to FIGS. 20 to 24 which are a schematic plan view and a schematic sectional view of a DRAM, a DRAM utilizing this anisotropic selective epitaxial growth method has a COB structure in which a capacitor is provided above a bit line. The DRAM is as follows. At this time, the mask alignment margin (= α) in the photolithography process is 5
It is about 0 nm. Here, FIGS. 20 and 21 are schematic plan views in a hierarchical manner, FIG. 20 is a diagram showing a positional relationship between an active region, a gate electrode serving also as a word line, and the single crystal silicon layer, and FIG. FIG. 3 is a diagram showing a positional relationship among an electrode, a single crystal silicon layer, a bit line, and a storage node electrode. FIGS. 22 to 24 are schematic cross-sectional views taken along lines AA, BB, and CC in FIGS. In FIG. 20 and FIG. 21, the widths of the gate electrode and the bit line are shown to be smaller than the actual ones in order to facilitate understanding of these positional relationships.

The main surface of the P-type silicon substrate 301 is $ 10
0 °, and the specific resistance of the P-type silicon substrate 301 is 5Ω ·
cm. The orientation flat of the silicon wafer on which the P-type silicon substrate 301 is formed has sides in the <110> direction. P-type silicon substrate 301
The active region 302 on the surface of the substrate is surrounded by an element isolation region.
Field oxide film 305 and field oxide film 305
And a P ⁻ -type diffusion layer 304 (functioning as a channel stopper and a punch-through stopper) provided on the bottom surface of the substrate. Active regions 302 are regularly arranged on the main surface of P-type silicon substrate 301, and active regions 3 are formed.
The periphery of 02 is composed of sides in the <110> direction (in other words, the active region 302 is defined by the sides in the <110> direction). The minimum width (≒ channel width) and minimum interval of the active region 302 are both F (= 0.25 μm).
(250 nm)). A gate electrode 311 also serving as a word line having a thickness of about 150 nm crosses the surface of the active region 302 through a gate oxide film 306 having a thickness of about 8.5 nm provided by thermal oxidation on the surface of the active region 302. are doing. At least immediately above the active region 302, the gate electrode 311 is orthogonal to the active region 302. The width (gate length), interval, and wiring pitch of the gate electrode 311 are F, F, and 2F (= 0.5 μm (5
00 nm)). The gate electrode 311 has a thickness of 50
A tungsten silicide film having a thickness of about 100 nm is laminated on an N ⁺ type polycrystalline silicon film having a thickness of about nm. N
⁺ -Type polycrystalline silicon film is made of dichlorosilane (SiH
CV at about 700 ° C. using ₂ Cl ₂ ) and phosphine (PH ₃ ) as a source gas and a doping gas, respectively.
It is formed by Method D. The tungsten silicide film is formed by sputtering.

The upper surface of the gate electrode 311 is directly covered with a silicon oxide film cap 312 having a thickness of about 70 nm. A gate electrode 311 is formed on the surface of the active region 302.
100n in a self-aligned manner with the field oxide film 305.
N ⁻ type diffusion layers 313a, 313 having a junction depth of about m
13b is provided. N ^- type diffusion layers 313a, 313
3b is formed by ion implantation of phosphorous or arsenic of about 2 × 10 ¹³ m ⁻² at 30 keV. Gate electrode 31
1 and the side surface of the silicon oxide film cap 312
It is directly covered with a silicon oxide film spacer 314 of about 0 nm (= d). Gate oxide film 306 provided on the surface of active region 302 is removed in a self-aligned manner with field oxide film 305 and silicon oxide film spacer 314, and N ⁻ -type diffusion layers 313a and 313b in these regions are removed.
Surface is exposed. The width of these exposed surfaces in the direction narrowed by the two gate electrodes 311 is 150 nm (= F−
The width of these exposed surfaces at the portion sandwiched by the field oxide film 305 is about 250 nm (= F). The silicon oxide film forming the silicon oxide film cap 312 is initially formed of a silicon oxide film having a thickness of about 100 nm by a CVD method, and when the silicon oxide film spacer 314 is formed, the thickness of the silicon oxide film is reduced. Become. The height of the upper surface of the silicon oxide film cap 312 just above the active region 302 (P-type silicon substrate 301
Is approximately 230 nm from the main surface of the field oxide film 3).
The height is approximately 140 nm lower than the height of the upper surface of the silicon oxide film cap 312 right above the area 05 (about 370 nm from the main surface of the P-type silicon substrate 301).

The above-mentioned N ^- type diffusion layers 313a, 313b
Has a thickness (high) of about 500 nm and 1 × 10 ¹⁹
It is directly covered with N ⁻ -type single crystal silicon layers 316a and 316b having an impurity concentration of about m ⁻³ .
The exposed surfaces of the N ⁻ -type diffusion layers 313a and 313b have 70n
N ⁺ -type diffusion layer 315 having a depth (junction) of about m
a, 315b are provided. N ⁺ type diffusion layer 315
a and 315b are single crystal silicon layers 316a and 316b, respectively.
It is formed by solid phase diffusion of phosphorus from 316b. The source / drain regions 318a are N ^- type diffusion layers 313a,
It is composed of N ⁺ -type diffusion layer 315a and the single crystal silicon layer 316a, the source and drain regions 318b is the N ^- type diffusion layer 313b, and an N ⁺ -type diffusion layer 315b and the single crystal silicon layer 316b. Single crystal silicon layer 3
16a and 316b function as contact pads for a node contact hole and a bit contact hole, respectively, which will be described later. Single crystal silicon layer 31
The main upper surfaces of 6a and 316b are P-type silicon substrates 301.
Of the single-crystal silicon layers 316a and 316b are parallel to the main surface of the P-type silicon substrate 30.
1 has a {110} plane perpendicular to the main surface. Further, the single crystal silicon layers 316a and 316b are
05 slightly above the bird's beak and near the upper end of the silicon oxide film spacer 314. Strictly, the upper surface and the side surfaces of the single crystal silicon layers 316a and 316b do not directly intersect with each other. Intersect via facets (stacked on top). In the following description, unless otherwise specified, the facet is assumed to be included in a part of the upper surface.

The single-crystal silicon layers 316a and 316b are
Using a UHV-CVD apparatus, a temperature of 625 ° C., 1 × 1
Under a pressure of about 0 ^-2 Pa, disilane having a flow rate of about 2.0 sccm and (hydrogen (H
₂ ) with doping gas (comprising phosphine diluted to 1%). At this time, <10} of {100} plane of single crystal silicon layers 316a and 316b parallel (and perpendicular) to the main surface of P-type silicon substrate 301
The growth rate in the 0> direction is about 10 nm / min. When the base is a silicon oxide film, the single crystal silicon layer 3
The growth rate of the {110} plane in the <110> direction of 16a and 316b is about 1/20 of the growth rate of the {100} plane in the <100> direction. The extension width of the single crystal silicon layer 316a and the like on the field oxide film 305 is 25n (narrower than the mask alignment margin (α = 50 nm)).
m, and the extension width of the single crystal silicon layer 316a or the like over the vicinity of the upper end of the silicon oxide film spacer 314 (narrower than α) is about 10 nm to 15 nm. Here, the periphery of active region 302 is made of a side in the <110> direction, and gate electrode 311 crosses active region 302 in the <110> direction.
16b mainly grows in the <100> direction perpendicular to the main surface of the P-type silicon substrate 301. If the direction around the active region 302 or the direction of the gate electrode 311 at the portion crossing the active region 302 includes <100> directions, a simple {100} plane parallel to these directions is used. The side surfaces of the crystalline silicon layer also grow selectively in a direction perpendicular to these directions, which is not preferable.

P including the N-channel MOS transistor
The silicon substrate 301 is covered with a first interlayer insulating film 321. The interlayer insulating film 321 is made of a silicon oxide-based insulating film such as a laminated film of a silicon oxide film and a BPSG film by a CVD method, and is formed by chemical mechanical polishing (CM).
P) and the like, and has an upper surface flattened. The thickness of the interlayer insulating film 321 on the upper surface of the single crystal silicon layer 316a and the like is, for example, about 300 nm. The single-crystal silicon layer 31 penetrates the interlayer insulating film 321 through the interlayer insulating film 321.
A bit contact hole 322 having a diameter of about F reaching 6b is provided. Bit contact hole 32
2 is filled with a contact plug 323 made of, for example, an N ⁺ type polycrystalline silicon film. Interlayer insulating film 3
The bit line 324 provided on the upper surface of 21 is directly connected to the contact plug 323 and connected to the source / drain region 318b. The bit line 324 is made of, for example, a tungsten silicide film having a film thickness of about 120 nm. The minimum line width and the minimum interval of the bit line 324 are both about F. 0.35 μm (= F + 2α), and the wiring pitch of the bit line 324 is 0.6 μm.
(= 2F + 2α).

The interlayer insulating film 32 including the bit line 324
1 is covered with a second interlayer insulating film 331. The interlayer insulating film 331 is also made of a silicon oxide based insulating film, and the thickness of the interlayer insulating film 331 on the upper surface of the bit line 324 is 300 n.
m, and the upper surface of the interlayer insulating film 331 is also flattened. The interlayer insulating films 331 and 321 having a diameter of about F
The node contact hole 332 provided through the
The single crystal silicon layer 316a is reached and is filled with a contact plug 333 made of, for example, an N ⁺ type polycrystalline silicon film. The storage node electrode 334 provided on the upper surface of the interlayer insulating film 331 has a thickness of, for example, 80
It is made of an N ⁺ type polycrystalline silicon film of about 0 nm, is directly connected to the contact plug 333, and is connected to the source / drain region 318a. The interval and the minimum width of the storage node electrodes 334 are about F and F + 2α. At least a part of the upper surface and the side surface of the storage node electrode 334 and the upper surface of the interlayer insulating film 331 are formed of a stacked film (commonly called an ONO film) including a silicon oxide film, a silicon nitride film, and a silicon oxide film. Membrane 3
35 directly covered. The equivalent silicon oxide film thickness of the capacitor insulating film 335 is about 5 nm. The surface of the capacitor insulating film 335 is directly covered with a cell plate electrode 336 made of, for example, an N ⁺ type polycrystalline silicon film having a thickness of about 150 nm. The surface of the cell plate electrode 336 is directly covered with a surface protection film 341 made of a silicon oxide-based insulating film. Storage node electrode 33
The film thickness of the surface protective film 341 immediately above 4 is about 300 nm.

[0011]

If the aforementioned single crystal silicon layers 316a and 316b of the DRAM are formed by a known isotropic selective epitaxial growth method, the interval between the N ⁻ type diffusion layers 313a is about 350 nm. Therefore, the distance between the single crystal silicon layers functioning as contact pads with respect to the node contact holes is particularly reduced, and the height required to function as a contact pad (at least higher than the upper surface of the silicon oxide film cap 312). (Preferably). On the other hand, the single-crystal silicon layer formed by the above-described anisotropic selective epitaxial growth has a ｛1 in the <110> direction.
Compared to the growth rate of the 10｝ plane,
Since the growth rate of the 0 ° plane is high, as shown in FIGS. 20 and 21, etc., between the single crystal silicon layers 316a and 316b and between two adjacent single crystal silicon layers 316a. It is easy to provide required intervals so that short circuits do not occur.

However, this {110} direction in the <110> direction in the above-described anisotropic selective epitaxial growth.
A new problem arises in that "the {100} plane growth rate in the <100> direction is higher than the plane growth rate". This problem will be described with reference to FIG. 25 which is a schematic diagram.

In this anisotropic selective epitaxial growth,
The growth rate of the {110} plane in the <110> direction is <10
0> direction is about 1/20 of the growth rate of the {100} plane, and after the upper surfaces of the single-crystal silicon layers 316a and 316b reach near the upper end of the silicon oxide film spacer 314,
The growth of the {110} plane in the <110> direction of the single crystal silicon layers 316a and 316b extending near the upper end of the silicon oxide film spacer 314 is started. As a result, the overlap width of the single-crystal silicon layers 316a and 316b over the vicinity of the upper end of the silicon oxide film spacer 314 (and further on the upper surface of the silicon oxide film cap 312) is
The overlap width of the single crystal silicon layers 316a and 316b on the upper surface of the field oxide film 305 becomes smaller. In such a situation, for example, the node contact hole 32
When opening 2, if the mask alignment deviation δ (where 0 ≦ δ ≦ α) is not 0, especially the upper end of the silicon oxide film spacer 314 and part of the silicon oxide film cap 312 are also etched away. , Gate electrode 3
The film thickness of the silicon oxide film cap 312 and the silicon oxide film spacer 314 that cover the gate electrode 11 is locally reduced.
2 will be exposed at the bottom. Single crystal silicon layer 31
In order for 6a or the like to function sufficiently as a contact pad, it is necessary that only the upper surface of the single crystal silicon layer 316a or the like is exposed at the bottom of the node contact hole 322 or the like. Therefore, the single crystal silicon layer 316a and the like in this case are insufficient to function as contact pads. Therefore, the leak current between the source / drain region (in this case, the storage node electrode of the capacitor) and the gate electrode 311 increases, and furthermore, a short circuit between them easily occurs.

In this case, if a single-crystal silicon layer having a height of, for example, about 2 μm is provided by the anisotropic selective epitaxial growth, the single-crystal silicon layer is formed on silicon oxide film cap 312 by an amount corresponding to the mask alignment margin (α). The overlap width of the silicon layer can be secured. However, a single-crystal silicon layer having such a height is unrealistic because it impairs workability in a later step.

As with the problem of short circuit of the gate electrode, short circuit with the semiconductor substrate is also a problem. This problem will be described with reference to FIG. The minimum width and the minimum interval of the active region are about F and F + 2α (= 0.35 μm) in design dimensions. And the width of the field oxide film increases to F + 2α + 2β. The magnitude of β varies depending on the conditions for forming the field oxide film, but here β = 20 nm. As described above, the extension width of the single crystal silicon layer 316a and the like on the field oxide film 305 is about 25 nm. As a result, the width of the single crystal silicon layer 316 is about 0.26 μm. In such a situation, for example, when opening the node contact hole 322, the mask alignment deviation δ (where 0 ≦ δ ≦
If α) is not 0, in particular, the interlayer insulating film 321 and a part of the field oxide film 305 are also etched away, so that the film thickness of the field oxide film 305 is locally reduced. The portion is exposed at the bottom of the node contact hole 322.

[0016]

Accordingly, an object of the present invention is to provide a source / drain region including a diffusion layer and a single crystal semiconductor layer provided as a contact pad in a self-aligned manner on the surface of the diffusion layer. In a semiconductor device having a semiconductor device, a leak current and a short circuit between a wiring connected to these source / drain regions via a contact hole, a gate electrode, and a semiconductor substrate are easily suppressed, and a reality that does not hinder a subsequent process is provided. It is an object of the present invention to provide a semiconductor device having a typical single crystal semiconductor layer and a method for manufacturing the same.

[0017]

According to the present invention , there is provided a semiconductor device comprising: a gate insulating film formed on a semiconductor substrate;
A gate electrode formed on the gate insulating film and having an upper surface and side surfaces covered with an insulating film, a single crystal semiconductor layer formed on the semiconductor substrate adjacent to the insulating film covering the gate electrode, A first interlayer insulating film formed on the insulating film covering the gate electrode; and an etchant formed on the first interlayer insulating film and the single crystal semiconductor layer and different from the first interlayer insulating film. A second interlayer insulating film made of a material, a contact hole formed in the second interlayer insulating film and reaching the upper surface of the single crystal semiconductor layer, and connected to the single crystal semiconductor layer through the contact hole And wiring to be provided. The “etchant” here is a general term for an etching solution, an etching gas, and the like. For example, a semiconductor device which is a premise of the present invention includes a gate silicon oxide film formed on a silicon substrate, and a gate electrode formed on the gate silicon oxide film and having upper and side surfaces covered with the silicon oxide film. A single-crystal silicon layer formed on the silicon substrate adjacent to the silicon oxide film covering the gate electrode; a silicon nitride film formed on the silicon oxide film covering the gate electrode; A silicon oxide film formed on the single crystal silicon layer; a contact hole formed in the silicon oxide film and reaching the upper surface of the single crystal silicon layer; And a wiring to be connected.

[0018] The semiconductor device according to the present invention comprises an active region defined by the <110> direction of the side which is provided on the surface of the silicon substrate, the element isolation region on the surface of the silicon substrate surrounding the active region A field insulating film filling the groove, a gate electrode traversing the surface of the active region in the <110> direction via a gate oxide film provided on the surface of the active region, A silicon oxide film cap directly covering the upper surface of the gate electrode,
A silicon oxide film spacer that directly covers the side surface of the silicon oxide film cap and the gate electrode; a reverse conductivity type diffusion layer provided on the surface of the active region in a self-aligned manner with the gate electrode and the field oxide film; While directly covering the surface of the reverse conductivity type diffusion layer which is self-aligned with the silicon oxide film spacer and the field oxide film, # 1
A reverse conductivity type source / drain region formed of a reverse conductivity type single crystal silicon layer having a side surface composed of 10 planes and an upper surface composed mainly of {100} planes; the field oxide film and the silicon oxide film cap And a first interlayer insulating film deposited so as to cover the silicon oxide film spacer and expose the upper surface of the single crystal silicon layer, and to cover the first interlayer insulating film and the single crystal silicon layer while covering the first interlayer insulating film and the single crystal silicon layer. A second interlayer insulating film made of a material different from that of the first interlayer insulating film, a contact hole provided in the second interlayer insulating film and reaching the upper surface of the single crystal silicon layer, and the source / drain through the contact hole. And a wiring connected to the region.

Alternatively, the semiconductor device according to the present invention comprises an active region defined by <110> -side sides provided on a surface of a one-conductivity-type silicon substrate having a main surface of {100}; And a <110> direction on the surface of the active region through a LOCOS type field oxide film provided in an element isolation region on the surface of the silicon substrate and a gate oxide film provided on the surface of the active region. A silicon oxide film cap that directly covers the upper surface of the gate electrode, a silicon oxide film spacer that directly covers the silicon oxide film cap and the side surface of the gate electrode, the gate electrode and the field oxide. A reverse conductivity type diffusion layer provided on the surface of the active region in a self-aligned manner with the film, the silicon oxide film spacer and the field oxide film; A reverse conductivity type single crystal silicon layer which directly covers the surface of the self-aligned reverse conductivity type diffusion layer and has a {110} side surface and a main surface including a {100} top surface; Inter-layer insulating film deposited so as to cover the source / drain region and the field oxide film, the silicon oxide film cap and the silicon oxide film spacer, and to expose the upper surface and the side surface of the single crystal silicon layer. A second interlayer insulating film covering the first interlayer insulating film and the single-crystal silicon layer and having a material different from that of the first interlayer insulating film; and a second interlayer insulating film provided on the second interlayer insulating film. The semiconductor device includes a contact hole reaching the upper surface of the crystalline silicon layer, and a wiring connected to the source / drain region through the contact hole.

Preferably, the first interlayer insulating film is made of a silicon nitride film or a silicon nitride oxide film, and the second interlayer insulating film is made of a silicon oxide film or a silicon oxide film containing phosphorus or boron. More preferably,
The minimum distance between the gate electrodes is equal to the minimum diameter of the contact hole. More preferably, a minimum width of the active region defined by the field insulating film is equal to a minimum diameter of the contact hole.

According to a method of manufacturing a semiconductor device according to the present invention, a gate insulating film is formed on a semiconductor substrate, a gate electrode is formed on the gate insulating film, and upper and side surfaces of the gate electrode are covered with the insulating film. Forming a single crystal semiconductor layer on the semiconductor substrate adjacent to the insulating film covering the gate electrode, forming a first interlayer insulating film on the insulating film covering the gate electrode, Forming a second interlayer insulating film made of a material having an etchant different from that of the first interlayer insulating film on the film and the single crystal semiconductor layer, and forming an upper surface of the single crystal semiconductor layer on the second interlayer insulating film; A contact hole that reaches the hole is formed, and a wiring is connected to the single crystal semiconductor layer through the contact hole. For example, in the method of manufacturing a semiconductor device according to the present invention, a gate silicon oxide film is formed on a silicon substrate, a gate electrode is formed on the gate silicon oxide film, and upper and side surfaces of the gate electrode are formed of a silicon oxide film. Forming a single-crystal silicon layer on the silicon substrate adjacent to the silicon oxide film covering the gate electrode, forming a silicon nitride film on the silicon oxide film covering the gate electrode, A silicon oxide film is formed on the single crystal silicon layer, a contact hole reaching the upper surface of the single crystal silicon layer is formed in the silicon oxide film, and a wiring is connected to the single crystal silicon layer through the contact hole. Is what you do.

More specifically, in the method of manufacturing a semiconductor device according to the present invention, an active region defined by a <110> direction side on a surface of a silicon substrate of one conductivity type having a main surface of {100} is provided. Forming a groove in the surrounding element isolation region,
Forming an insulating film on the entire surface, leaving the insulating film only in the trench to form a field insulating film; forming a gate oxide film on the surface of the active region by thermal oxidation; Forming a silicon oxide film covering the surface of the conductor film, patterning the silicon oxide film and the conductor film, and moving the surface of the active region through the gate oxide film in the <110> direction. And a silicon oxide film cap that directly covers the upper surface of the gate electrode, and a reverse conductivity type diffusion layer is formed on the surface of the active region using the gate electrode and the field oxide film as a mask. Process and forming a silicon oxide film on the entire surface,
The silicon oxide film is etched back by anisotropic etching to form a silicon oxide film spacer directly covering the side surfaces of the silicon oxide film cap and the gate electrode. A step of removing the gate oxide film in a self-aligned manner and a reverse conductivity type single crystal higher than the height of the silicon oxide film cap on the surface of the reverse conductivity type diffusion layer by anisotropic selective epitaxial growth of single crystal silicon. A step of forming a silicon layer, forming a first interlayer insulating film on the entire surface, and forming the first interlayer insulating film by chemical mechanical polishing.
Polishing the interlayer insulating film and the single-crystal silicon layer to expose the surface of the single-crystal silicon layer without exposing the silicon oxide film cap; Forming a second interlayer insulating film,
Flattening the surface of the second interlayer insulating film; forming a contact hole reaching the single crystal silicon layer in the second interlayer insulating film; and forming the contact hole in the surface of the second interlayer insulating film. Forming a wiring connected to the single-crystal silicon layer through the semiconductor device.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, an element isolation region surrounding an active region defined by <110> -side sides on a surface of a one-conductivity-type silicon substrate having a main surface of {100} Forming a LOCOS type field oxide film on the surface of the active region by thermal oxidation, forming a conductor film on the entire surface, and forming a silicon oxide film covering the surface of the conductor film. The silicon oxide film and the conductor film are patterned to form a gate electrode that traverses the surface of the active region in the <110> direction via the gate oxide film and directly covers the upper surface of the gate electrode. Forming a silicon film cap and forming a reverse conductivity type diffusion layer on the surface of the active region using the gate electrode and the field oxide film as a mask; A silicon oxide film spacer is formed by directly etching the silicon oxide film cap and the side surface of the gate electrode by performing an etch back on the silicon oxide film by anisotropic etching. Removing the gate oxide film in a self-aligned manner with the field oxide film; and performing anisotropic selective epitaxial growth of single crystal silicon on the surface of the opposite conductivity type diffusion layer so as to be higher than the height of the silicon oxide film cap. Forming a reverse conductivity type single crystal silicon layer, forming a first interlayer insulating film on the entire surface, etching back the first interlayer insulating film and exposing the silicon oxide film cap without exposing the silicon oxide film cap; A step of exposing the upper surface and side surfaces of the crystalline silicon layer; Forming a second interlayer insulating film, flattening the surface of the second interlayer insulating film, and forming a contact hole reaching the single crystal silicon layer in the second interlayer insulating film; Forming a wiring connected to the single crystal silicon layer through the contact hole on the surface of the second interlayer insulating film.

[0024]

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIGS. 1 to 6 which are a schematic sectional view and a schematic plan view of a DRAM, a first embodiment of the present invention is an application of the present invention to a COB-structured DRAM. This DRAM has a design rule of 0.25 μm (minimum processing size; F = 0.25 μm (250 nm)).
It is formed under a mask alignment margin α of about nm, and is as follows. Here, FIG. 5 and FIG. 6 are schematic plan views that are hierarchized,
FIG. 5 is a diagram showing a positional relationship between an active region, a gate electrode serving also as a word line, and an N ⁺ type single crystal silicon layer.
FIG. 3 is a diagram showing a positional relationship among a gate electrode, a single crystal silicon layer, a bit line, and a storage node electrode. Also,
FIGS. 1 to 4 show the AA line, BB line, and CC of FIGS. 5 and 6, respectively.
FIG. 4 is a schematic cross-sectional view taken along line DD and line DD. 5 and 6
In order to facilitate understanding of these positional relationships, the width of the gate electrode and the width of the bit line are displayed smaller than they actually are.

The main surface of the P-type silicon substrate 101 is $ 10
0 °, and the specific resistance of this P-type silicon substrate 101 is 5
It is about Ω · cm. The orientation flat of the silicon wafer on which the P-type silicon substrate 101 is formed has sides in the <110> direction. P-type silicon substrate 10
1 is surrounded by an element isolation region, and the element isolation region is a trench 10 having a depth of about 300 nm.
3 and provided on the side and bottom surfaces of the groove 103 (functions as a channel stopper and a punch-through stopper)
And a P ⁻ type diffusion layer 104. Active area 1
Numerals 02 are regularly arranged on the main surface of the P-type silicon substrate 101, and the periphery of the active region 102 is composed of sides in the <110> direction (that is, the active region 102 is divided by the sides in the <110> direction). Will be). Active area 1
02, the minimum width (≒ channel width) and the minimum interval are both F
(= 0.25 μm (250 nm)). Film thickness 1
The gate electrode 111 also serving as a word line of about 50 nm
It crosses over the surface of the active region 102 via a gate oxide film 106 having a thickness of about 8.5 nm provided on the surface of the active region 102. At least right above the active region 102, the gate electrode 111 is orthogonal to the active region 102. The width (gate length), interval, and wiring pitch of the gate electrode 111 are F, F, and 2F (= 0.5 μm, respectively).
(500 nm)). The gate electrode 111 is formed of an N ⁺ -type polycrystalline silicon film having a thickness of about 50 nm and a thickness of 100 n.
An approximately m-thick tungsten silicide film is laminated. The upper surface of the gate electrode 111 is directly covered with a silicon oxide film cap 112 having a thickness of about 70 nm.
On the surface of the active region 102, N ⁻ -type diffusion layers 113a and 113b having a junction depth of about 100 nm are provided in a self-aligned manner with the gate electrode 111 and the field oxide film 105. Side surfaces of the gate electrode 111 and the silicon oxide film cap 112 are directly covered with a silicon oxide film spacer 114 having a thickness of about 50 nm (= d). Gate oxide film 1 provided on the surface of active region 102
Numeral 06 is removed in a self-aligned manner with the field oxide film 105 and these silicon oxide film spacers 114, and the surfaces of the N ⁻ type diffusion layers 113a and 113b are exposed. The width of these exposed surfaces in the direction sandwiched by the two gate electrodes 111 is about 150 nm (= F−2d), and the width of these exposed surfaces in the portion sandwiched by the field oxide film 105 is 2
It is about 50 nm (= F).

The exposed surfaces of the N ^- type diffusion layers 113a and 113b have a height (thickness) of about 400 nm and 1 × 10 ¹⁹ c
It is directly covered with N ⁺ type single crystal silicon layers 116a and 116b having an impurity concentration of about m ⁻³ .
The N ⁺ -type single-crystal silicon layers 116a and 116b are formed by anisotropic selective epitaxial growth (which will be described in detail later). Single-crystal silicon layers 117a and 117b
Must be higher than the height (about 230 nm) of the silicon oxide film cap 112 covering the gate electrode 111. The exposed surfaces of the N ⁻ -type diffusion layers 113a and 113b have a depth of (junction) of about 70 nm.
⁺ -Type diffusion layers 115a and 115b are provided. N ⁺
The type diffusion layers 115a and 115b are formed by solid phase diffusion of phosphorus from the single crystal silicon layers 117a and 117b, respectively. The single-crystal silicon layer 117a extends over the field oxide film 105 with a width of about 20 nm (having a form directly covering the upper surface of the field oxide film 105), and is slightly less than 10 nm above the vicinity of the upper end of the silicon oxide film cap 114. ~
It extends with a width of slightly more than 20 nm (having a form that directly covers the upper end portion of the silicon oxide film cap 114). The single crystal silicon layer 117b is also formed on the field oxide film 105 by 20
The silicon oxide film cap 114 extends with a width of about nm.
It extends over the vicinity of the upper end with a width of less than 10 nm to slightly more than 20 nm. The upper surfaces of the single-crystal silicon layers 117a and 117b are mainly composed of # 10 parallel to the main surface of the P-type silicon substrate 101.
Single-crystal silicon layers 117a, 117b
Is perpendicular to the main surface of the P-type silicon substrate 101.
It consists of 10｝ plane. In the present embodiment, the facet constituting the upper surface near the intersection between the side surface and the upper surface of the single crystal silicon layers 117a and 117b is substantially the field oxide film 105.
Exists only in the vicinity of the intersection with the side surface.

In this embodiment, the source / drain regions 1
Reference numeral 18a denotes an N ⁻ type diffusion layer 113a and an N ⁺ type diffusion layer 115.
a, a single-crystal silicon layer 117a. The source / drain region 118b is formed in the N ⁻ type diffusion layer 113.
b, N ⁺ type diffusion layer 115b, single crystal silicon layer 117b
It is composed of The N-channel MOS transistor formed on the main surface of the P-type silicon substrate 101 includes a gate oxide film 106, a gate electrode 111, and source / drain regions 118a. Since the distance between the adjacent single-crystal silicon layers 117a and the distance between the single-crystal silicon layers 117a and 117b are both about 210 nm, the adjacent source / drain regions 118
During the period a, the insulation separation between the source / drain region 118a and the source / drain region 118b is sufficiently ensured.

P including N channel MOS transistor
The silicon substrate 101 is covered with a first interlayer insulating film 119. The first interlayer insulating film 119 is, for example, C
A silicon nitride film or a silicon nitride oxide film formed by a VD method is planarized by chemical mechanical polishing (CMP) or the like, and only the surfaces of the single crystal silicon layers 117a and 117b are exposed.

The surfaces of the first interlayer insulating film 119 and the single crystal silicon layers 117a and 117b are
Covered by 1. The second interlayer insulating film 121 is made of, for example, a silicon oxide-based insulating film such as a laminated film of a silicon oxide film formed by a CVD method and a BPSG antinode. The thickness of the second interlayer insulating film 121 on the upper surfaces of the single crystal silicon layers 117a and 117b is, for example, about 300 nm. The second interlayer insulating film 121 is provided with a bit contact hole 122 having a diameter of about F which penetrates the interlayer insulating film 121 and reaches the single crystal silicon layer 117b. The bit contact hole 122 is filled with a contact plug 123 made of, for example, an N ⁺ type polycrystalline silicon film. The bit line 124 provided on the upper surface of the second interlayer insulating film 121 is directly connected to the contact plug 123 and connected to the source / drain region 118b. The bit line 124 is made of, for example, a tungsten silicide film having a thickness of about 120 nm.
Is about F, the line width of the bit line 124 at the bit contact hole 122 is about 350 nm (= F + 2α), and the bit line 12
The wiring pitch of No. 4 is about 600 nm (= 2F + 2α).

In this embodiment, the bit contact hole 1
Since the width of the single-crystal silicon layer 117b at the portion where the second contact 22 reaches is about 290 nm, the bit contact hole 122
May protrude from the single crystal silicon layer 117b and be opened. In that case, the first interlayer insulating film 119 functions as an etching stopper when opening the bit contact hole. That is, the bottom of the bit contact hole 122 is
2. It does not directly reach the silicon oxide film spacer 114 or the field oxide film 105, and
Exposing the upper surface of the gate electrode 111 or the surface of the P-type silicon substrate 101 to the bottom of the contact hole 122 is avoided. Therefore, it is easy to suppress a leak current and a short circuit between the bit line 124 (and the source / drain region 118b), the gate electrode 111, and the P-type silicon substrate 101.

The second interlayer insulating film 121 including the bit line 124 is covered with a third interlayer insulating film 131. The third interlayer insulating film 131 is also made of a silicon oxide based insulating film, and the third interlayer insulating film 1 on the upper surface of the bit line 124 is formed.
31 has a thickness of about 300 nm, and the upper surface of the third interlayer insulating film 131 is also flattened. The third interlayer insulating film 131 and the second interlayer insulating film 121 having a diameter of about F
Node contact hole 132 provided through
It reaches the single crystal silicon layer 117a and is filled with a contact plug 133 made of, for example, an N ⁺ type polycrystalline silicon film. The storage node electrode 134 provided on the upper surface of the third interlayer insulating film 131 has a thickness of, for example, 80
It is made of an N ⁺ type polycrystalline silicon film of about 0 nm, is directly connected to the contact plug 133, and is connected to the source / drain region 118a. The interval and the minimum width of the storage node electrodes 134 are about F and F + 2α. At least a part of the upper surface and the side surface of the storage node electrode 134 and at least a part of the upper surface of the interlayer insulating film 131 are directly covered with a capacitance insulating film 135 made of an ONO film. The equivalent silicon oxide film thickness of the capacitor insulating film 135 is about 5 nm. The surface of the capacitor insulating film 135 has a thickness of, for example, 150
It is directly covered with a cell plate electrode 136 made of an N ⁺ type polycrystalline silicon film of about nm. The surface of the cell plate electrode 136 is directly covered with a surface protection film 141 made of, for example, a silicon oxide-based insulating film. Surface protective film 141 immediately above storage node electrode 134
Has a thickness of about 300 nm.

Referring to FIGS. 7 to 10 and FIGS. 1 to 6 which are schematic cross-sectional views of manufacturing steps along the AA line and the CC line in FIGS. 5 and 6, the DRAM according to the present embodiment has It is formed as follows.

First, it has a main surface of {100},
Photoresist is applied to a region covering only the active region 202 on the main surface of the P-type silicon substrate 101 made of a silicon wafer having a specific resistance of about 5 Ω · cm and having an orientation flat including sides in the <110> direction. A film (not shown) is formed. The active regions 102 are defined by sides in the <110> direction (parallel and perpendicular to the orientation flat) on the main surface of the P-type silicon substrate 101.
It is regularly arranged on the main surface of the P-type silicon substrate 101 in the form of a mold. Using the photoresist film as a mask, the P-type silicon substrate 101 is etched to form a groove 103. Thereafter, using a photo-resist film as a mask, rotational ion implantation of boron of about 20 keV and about 5 × 10 ¹² cm ⁻² is performed, and a P ⁻ type diffusion layer 104 is formed on the side and bottom surfaces of the groove 103. After the photo-resist film is removed, a silicon oxide film is formed on the entire surface by the CVD method. The silicon oxide film is formed by the CMP, the trench 103 is filled, and a field insulating film 105 having a flat upper surface is formed. You. A gate oxide film 10 having a film pressure of about 8.5 nm is formed on the surface of the active region 102 by thermal oxidation.
6 are formed.

Next, for example, dichlorosilane and phosphine were used as a source gas and a doping gas, respectively.
An N ⁺ -type polycrystalline silicon film (not explicitly shown) having a thickness of about 50 nm is formed on the entire surface by the CVD method at about 00 ° C. Furthermore, a film thickness of 100 n is formed on the entire surface by sputtering.
m tungsten silicide film (not explicitly shown)
Is formed. Furthermore, a silicon oxide film having a thickness of about 100 nm is formed on the entire surface by the CVD method. These silicon oxide film, tungsten silicide film and N ⁺ type polycrystalline silicon film are sequentially patterned by anisotropic etching to form a tungsten polycide film (N ⁺
Gate electrode 11 made of a polycrystalline silicon film and a tungsten silicide film) and having a thickness of about 150 nm.
1 and a silicon oxide film cap 112 (with a thickness of about 100 nm) that selectively covers the upper surface of the gate electrode 111 are formed.

The N ⁻ -type diffusion layers 113 a and 113 b are self-aligned with the field oxide film 105 and the gate electrode 111, for example, by ion implantation of phosphorus of about 2 × 10 ¹³ cm ⁻² at 30 keV. Is formed.
The junction depth of N ⁻ type diffusion layers 113a and 113b is 100
nm. The distance between adjacent N ⁻ -type diffusion layers 113 a is about F, and the distance between N ⁻ -type diffusion layers 113 a and 113 ⁻ b is 0.25 μm (250 nm) (=
F). A silicon oxide film having a thickness of about 50 nm is formed on the entire surface by CVD. Etch back is performed by anisotropic etching using a fluorocarbon-based etching gas, and silicon oxide film spacers 11 are formed.
4 are formed. In this etch back, the silicon oxide film cap 112 is also exposed to the etching, and the silicon oxide film cap 112 has a thickness of 70 nm.
About. Further, in a self-alignment manner to the silicon oxide film spacers 114 and the field oxide film 105, the N ^- type diffusion layer 113a, a gate oxide film 106 on the surface of 113b is removed, these parts N ^- type diffusion layer 113a, 113
The surface of b is exposed. [FIGS. 1 to 6, FIG. 7 (a),
FIG. 9 (a)].

Next, using a UHV-CVD, First N ^-
After removing the natural oxide film formed on the exposed surfaces of the mold diffusion layers 113a and 113b, for example, at a temperature of 625 ° C., 1 × 10
Anisotropic selective epitaxial growth using a pressure of about ^-2 Pa, a flow rate of about 2.0 sccm of disilane and a doping gas of about 0.2 sccm (1% phosphine is diluted with hydrogen), N ⁺ -type (first silicon layers) single-crystal silicon layers 116a and 116b having a height (thickness) of about 300 nm are formed in a self-aligned manner on the exposed surfaces of the N ⁻ -type diffusion layers 113a and 113b. , N ^- -type diffusion layer 113a, the exposed surface of the 113b (the junction) depth 70nm approximately N ⁺ -type diffusion layer 115
a, 115b are formed. Under these conditions, the growth rate of the {100} plane (of the single crystal silicon layer) in the <100> direction is about 10 nm / min. At this time, the growth rate in the <110> direction of the {110} plane (of the single crystal silicon layer) crossing the surface of the silicon oxide film such as the field oxide film 105 is the growth rate of the {100} plane in the <100> direction. About 1/20 of the above. In this embodiment, the field oxide film 105 and the silicon oxide film spacer 11
N ^- type diffusion layers 113a, 113 formed in
Since the exposed surface 13b is surrounded by the sides in the <110> direction, these single crystal silicon layers 116a and 116b
b mainly grows selectively in the <100> direction perpendicular to the main surface of the P-type silicon substrate 101. [FIGS. 1 to 6,
7 (b) and 9 (b)].

[0038] The anisotropic selective epitaxial growth of the monocrystalline silicon layer, a growth temperature in the range of 500 ° C. to 800 ° C., preferably carried out at a pressure ranging from 10 ^-3 Pa~5 × 10 ^-2 Pa. When the growth temperature is lower than 500 ° C., single crystal silicon cannot be obtained, and when the growth temperature is higher than 800 ° C., it becomes difficult to dope conductive impurities such as phosphorus. Also, when the pressure deviates from this range, "anisotropic" growth becomes difficult. This "anisotropic" selectivity increases with increasing growth temperature and decreasing flow rate of disilane. Even if monosilane (SiH ₄ ) is used in place of disilane as a source gas, anisotropic selective epitaxial growth of a single crystal silicon layer is possible, but the growth temperature is 80 times higher than when disilane is used. The temperature shifts to a high temperature side of about 100C to 100C. In addition, even if dichlorosilane is used as a raw material gas, anisotropic selective growth of a single crystal silicon layer can be performed, but in this case, there is a problem that facets frequently occur.

Next, a film thickness of 250 n is formed on the surface by the CVD method.
m silicon nitride film 120 is deposited. [FIGS. 1 to 6, FIG. 7 (c), FIG. 9 (c)].

Thereafter, the silicon nitride film 12 is formed by CMP.
0 is polished to expose the upper surfaces of the single crystal silicon layers 116a and 116b, and the silicon nitride film 120 and the single crystal silicon layers 116a and 116b are polished together to form a flat surface. As a result, the thickness of the silicon nitride film 120 becomes 150 n on the silicon oxide film cap 112.
m, and the upper surfaces of the single crystal silicon layers 117a and 117b are equal to the surface height of the silicon nitride film 120. [FIGS. 1 to 6, FIG. 8 (d), FIG. 10 (d)].

Thereafter, for example, formation of a silicon oxide film, B
The formation of the PSG film, the reflow of the BPSG film, the CMP, and the like are performed, and the second interlayer insulating film 121 made of a silicon oxide-based insulating film having a flat upper surface is formed. Next, the second
Single-crystal silicon layer 117 penetrating through interlayer insulating film 121 of FIG.
A bit contact hole 122 reaching the upper surface of b is formed. The diameter of the bit contact hole 122 is 0.25μ.
When the misalignment is large in the photolithography process, the bottom of the bit contact hole 122 may protrude from the upper surface of the single crystal silicon layer 117b. The silicon oxide film is etched when the opening is formed, but the silicon nitride film or the silicon oxynitride film is hardly etched. CF ₄ + CH ₂ F
_{Since the two} mixed gas is used, the first interlayer insulating film 120 made of a silicon nitride film serves as an etching stopper, and the bit contact hole 131 does not reach the gate electrode 111 and the field insulating film 105. [FIGS. 1 to 6, FIG. 8 (e), FIG. 10 (e)].

Next, the bit contact hole 122 is filled with a contact plug 123 made of a conductor film such as an N ⁺ type polycrystalline silicon film. For example, a conductive film made of a tungsten silicide film or the like having a thickness of about 120 nm is formed by sputtering, and the conductive film is patterned to form a bit line 124.
Subsequently, a third interlayer insulating film 131 made of a silicon oxide based insulating film having a flat upper surface is formed. A node contact hole 132 penetrating through third interlayer insulating film 131 and third interlayer insulating film 121 and reaching the upper surface of single crystal silicon layer 117a is formed. Node contact hole 13
2 is also about 0.25μm (= F).
Even if the bottom of the node contact hole 132 protrudes from the upper surface of the single crystal silicon layer 117a due to a large misalignment in the lithography process, the first interlayer insulating film functions as an etching stopper similarly to the bit contact hole. In addition, the node contact hole 132 does not reach the gate electrode 111 and the field insulating film 105. [FIGS. 1 to 6, FIG. 8 (f), FIG.
(F)].

Next, the node contact hole 132 is filled with a contact plug 133 made of a conductor film such as an N ⁺ type polycrystalline silicon film. 8 film thickness over the entire surface
N ⁺ type polysilicon of about 00 nm is formed, and this is patterned to form a storage node electrode 134. Note that the storage node electrode 134 and the contact plug 133 may be formed of the same N ⁺ -type polycrystalline silicon film, and may be formed by one-time patterning. For example, a capacitor insulating film 135 made of an ONO film is formed, and a cell plate electrode 136 made of, for example, a 150 nm-thick N ⁺ -type polycrystalline silicon film is formed. Further, a surface protective film 141 is formed, and the DRA of the present embodiment is formed.
M is completed [FIGS. 1 to 6].

Referring to FIGS. 11 to 15 which are a schematic sectional view and a schematic plan view of a DRAM, a second embodiment of the present invention is based on a design rule of 0.25 μm (bit Applied to DRAM (in a normal stacked structure) where the lines are higher than the capacitors. The difference between this embodiment and the first embodiment lies in the vertical relationship between bit lines and capacitors and the structure of the element isolation region. This DRAM is as described below.
Here, FIGS. 14 and 15 are also schematic plan views in a hierarchical manner, and FIG. 14 is a diagram showing a positional relationship between an active region, a gate electrode serving also as a word line, and an N ⁺ type single crystal silicon layer. FIG. 15 is a diagram showing a positional relationship among a gate electrode, a single crystal silicon layer, a storage node electrode, and a bit line. FIGS. 11 to 13 show A in FIGS. 14 and 15.
FIG. 4 is a schematic cross-sectional view taken along line A, line BB, and line CC. In addition,
In FIGS. 14 and 15, the widths of the gate electrode and the bit line are each shown to be smaller than the actual values in order to facilitate understanding of these positional relationships.

The main surface of the P-type silicon substrate 201 is $ 10
0 °, and the specific resistance of this P-type silicon substrate 201 is 5
It is about Ω · cm. The orientation flat of the silicon wafer on which the P-type silicon substrate 201 is formed has sides in the <110> direction. The active region 202 on the surface of the P-type silicon substrate 201 is surrounded by an element isolation region.
A COS type field oxide film 205 and a bottom surface of the field oxide film 205 (channel stopper,
Functions as a punch-through stopper) P ^- and a diffusion layer 204. The active regions 202 are regularly arranged on the main surface of the P-type silicon substrate 201, and the periphery of the active region 202 is made of a side in the <110> direction (that is, the active region 202 is defined by a side in the <110> direction). That is).

Minimum width of active region 202 (≒ channel width)
The minimum interval is about F (= 250 nm). A gate electrode 211 serving also as a word line having a thickness of about 150 nm is provided on the surface of the active region 202 by 8.5 n.
It crosses over the surface of the active region 202 through a gate oxide film 206 having a thickness of about m. At least active area 2
Above 02, these gate electrodes 211 are orthogonal to the active region 202. The width (gate length), interval and wiring pitch of the gate electrode 211 are F, F and 2 respectively.
F (about 500 nm). The gate electrode 211 is made of an N ⁺ type polycrystalline silicon film having a thickness of about 50 nm and a thickness of 100 n.
An approximately m-thick tungsten silicide film is laminated.

The upper surface of the gate electrode 211 is directly covered with a silicon oxide film cap 212 having a thickness of about 70 nm. A gate electrode 211 is provided on the surface of the active region 202.
100 n in a self-aligned manner with the field oxide film 205.
N ⁻ type diffusion layers 213a, 213 having a junction depth of about m
13b is provided. The side surfaces of the gate electrode 211 and the silicon oxide film cap 212 have a thickness of 50 nm (=
It is directly covered with the silicon oxide film spacer 214 of about d). The gate oxide film 206 provided on the surface of the active region 202 is removed in a self-aligned manner with the field oxide film 205 and the silicon oxide film spacer 214, and the surfaces of the N ⁻ type diffusion layers 213a and 213b are exposed. 2
The width of these exposed surfaces in the direction sandwiched by two gate electrodes 211 is about F-2d, and the width of these exposed surfaces in the portion sandwiched by field oxide film 205 is F-2β (β = 2
It is about 0 nm (β is the length of a bird's beak). The height from the main surface of the P-type silicon substrate 201 to the upper surface of the silicon oxide film cap 212 on the active region 202 is 230
nm, and the sum of the silicon oxide film cap 212 on the field oxide film 205 up to the upper surface is about 370 nm.

The exposed surfaces of the N ⁻ -type diffusion layers 213a and 213b have a height (film thickness) of about 500 nm and 1 × 10 ¹⁹ c
It is directly covered with N ⁺ -type (single-crystal silicon layers 217a and 217b) having an impurity concentration of about m ⁻³ . The height (film thickness) of the single-crystal silicon layers 217a and 217b is at least equal to that of the gate. It must be thicker than the height (about 370 nm) of the silicon oxide film cap 212 covering the electrode 211. The exposed surface of the N ⁻ -type diffusion layers 213a and 213b has an N-type (junction) depth of about 70 nm.
⁺ Type diffusion layers 215a and 215b are provided. N ⁺
The type diffusion layers 215a and 215b are formed by solid phase diffusion of phosphorus from the single crystal silicon layers 217a and 217b, respectively. The single crystal silicon layers 217a and 217b are
It extends over the upper surface of the field insulating film 205 with a width of about 20 nm (having a form that directly covers the upper surface of the field insulating film 205), and extends over slightly over 10 nm over the vicinity of the upper end of the silicon oxide film cap 214. Silicon film cap 214
(With the appearance of directly covering the upper end). The upper surfaces of the single crystal silicon layers 217a and 217b are mainly composed of {100} planes parallel to the main surface of the P-type silicon substrate 201, and the side surfaces of the single crystal silicon layers 217a and 217b are
It consists of a {110} plane perpendicular to the main surface of mold silicon substrate 201. Also in the present embodiment, the single-crystal silicon layer 217a,
The facet constituting the upper surface in the vicinity of the intersection between the side surface and the upper surface of 217b is present only in the vicinity of the intersection with the side surface on the field insulating film 205 side.

In this embodiment, the source / drain regions 2
18a is an N ⁻ type diffusion layer 213a, an N ⁺ type diffusion layer 215
a, single-crystal silicon layers 217a and 217b. The source / drain region 218b includes an N ⁻ type diffusion layer 213b, an N ⁺ type diffusion layer 215b, and a single crystal silicon layer 217b. P-type silicon substrate 2
The N-channel MOS transistor formed on the main surface of the transistor 01 includes a gate oxide film 206, a gate electrode 211, and source / drain regions 218a and 218b. Since the distance between the adjacent single crystal silicon layers 217a and the distance between the single crystal silicon layers 217a and 217b are about 280 nm and slightly less than 210 nm, respectively, the distance between the adjacent source / drain regions 218a, 218a and source / drain region 2
18b is sufficiently secured.

P including N channel MOS transistor
The mold silicon substrate 201 is covered with a first interlayer insulating film 219. The first interlayer insulating film 219 is made of, for example, C
A silicon nitride film or a silicon nitride oxide film formed by a VD method;
a, 217b are exposed only on the upper surface and the upper side surface.
First interlayer insulating film 219 and single crystal silicon layer 217
The surfaces of a and 217b are covered with a second interlayer insulating film 221. The second interlayer insulating film 221 is, for example, CV
It is made of a silicon oxide-based insulating film such as a laminated film of a silicon oxide film and a BPSG antinode by the D method, and has an upper surface planarized by CMP or the like. Single crystal silicon layer 21
The film thickness of the second interlayer insulating film 221 on the upper surfaces of 7a and 217b is, for example, about 300 nm. On the second interlayer insulating film 221, a node contact hole 222 having a diameter of about F which penetrates through the second interlayer insulating film 221 and reaches the single crystal silicon layer 217a is provided. node·
The contact hole 222 is filled with a contact plug 223 made of, for example, an N ⁺ type polycrystalline silicon film. The storage node electrode 224 provided on the upper surface of the second interlayer insulating film 221 is made of, for example, an N ⁺ -type polycrystalline silicon film having a thickness of about 800 nm, is directly connected to the contact flag 223, Area 2
18a. Storage node electrode 23
The minimum interval and minimum width of No. 4 are about F and F + 2α.
At least a part of the upper surface and the side surface of the storage node electrode 224 and the upper surface of the second interlayer insulating film 221 are directly covered with the capacitive insulating film 225 made of the ONO film.
The equivalent silicon oxide film thickness of the capacitor insulating film 225 is about 5 nm. The surface of the capacitor insulating film 225 has a thickness of, for example, 15
It is directly covered with a cell plate electrode 226 made of an N ⁺ type polycrystalline silicon film of about 0 nm.

The cell immediately above the single crystal silicon layer 217b
The plate electrode 226 has an opening 2 having a diameter of about 400 nm.
27 are provided. The second interlayer insulating film 221 including the cell plate electrode 226 is
Covered by 1. The third interlayer insulating film 231 is also made of a silicon oxide based insulating film, and
The thickness of the third interlayer insulating film 231 on the upper surface of the cell plate electrode 226 covering the portion 24 is about 300 nm, and the upper surface of the third interlayer insulating film 231 is also flattened. Bit contact hole 232 having a diameter of about F
Is the third interlayer insulating film 23 at the opening 227
1, through the capacitor insulating film 225 and the second interlayer insulating film 221, reach the single crystal silicon layer 217a, and are filled with a contact plug 233 made of, for example, an N ⁺ type polycrystalline silicon film. The bit line 234 provided on the upper surface of the third interlayer insulating film 231 is
33, the source / drain region 218b
It is connected to the. The bit line 234 has a thickness of, for example, 120
The bit line 234 is formed of a tungsten silicide film having a thickness of about nm. The surface of the bit line 234 is directly covered with a surface protective film 241 made of, for example, a silicon oxide-based insulating film. The film thickness of the surface protection film 241 immediately above the bit line 234 is about 300 nm.

FIG. 16 to FIG. 19 and FIG.
15 to 15, the DRAM according to the present embodiment
Is formed as follows.

First, it has a main surface of {100},
On a main surface of a P-type silicon substrate 201 made of a silicon wafer having a specific resistance of about 50 Ω · cm and having an orientation flat including sides in the <110> direction, for example, a pad oxide film having a thickness of about 15 nm (see FIG. (Not shown), and a silicon nitride film (not shown) covering this pad oxide film is formed. On the surface of the silicon nitride film, a photoresist film (not shown) is formed in a region that covers only the active region 202 on the main surface of the P-type silicon substrate 201 only. The active region 202 is defined by sides in the <110> direction (parallel and perpendicular to the orientation flat) on the main surface of the P-type silicon substrate 201, and each active region has a rectangular shape and has a rectangular shape.
It is regularly arranged on the main surface of the mold silicon substrate 201. After the silicon nitride film is patterned using the photoresist film as a mask, boron ions of 50 keV and about 5 × 10 ¹² cm ⁻² are implanted using the photoresist film as a mask. After the removal of the photo-resist film, known selective oxidation is performed. As a result, a LOCOS type field oxide film 205 having a thickness of about 300 nm and a P ⁻ type diffusion layer 204 directly connected to the bottom surface of the field oxide film 205 are formed. After the silicon nitride film and the pad oxide film are removed, a gate oxide film 206 having a thickness of about 8.5 nm is formed on the surface of the active region 202 by thermal oxidation.

Next, an N ⁺ -type polycrystalline silicon film (not shown in the figure) having a thickness of about 50 nm is formed on the entire surface, and a tungsten silicide film (not shown in the figure) having a thickness of about 100 nm is formed on the entire surface. Is formed. Further, a silicon oxide film having a thickness of about 100 nm is formed on the entire surface by the CVD method. The silicon oxide film, the tungsten silicide film and the N ⁺ -type polycrystalline silicon film are sequentially patterned by anisotropic etching, and a gate electrode 21 of a tungsten polycide film having a thickness of about 150 nm is formed.
1 and the upper surface of the gate electrode 211 (film thickness 10
A silicon oxide film cap 212 (of about 0 nm) is formed. Field oxide film 205 and gate electrode 211
N ⁻ -type diffusion layers 213a and 213b are formed on the surface of active region 202 in a self-aligned manner. N ^- type diffusion layer 213
The depth of the junction between a and 213b is about 100 nm. The interval between adjacent N ⁻ -type diffusion layers 213a is about F,
The distance between the ⁻ type diffusion layer 213a and the N ⁻ type diffusion layer 213b is about F. A silicon oxide film with a thickness of about 50 nm is C
VD is formed on the entire surface, etched back by anisotropic etching, and the silicon oxide film spacer 21 is formed.
5 are formed. In this etch back, the silicon oxide film cap 212 is also exposed to etching, and the silicon oxide film cap 212 has a thickness of 70 nm.
About. In addition, the gate oxide film 206 on the surface of the N ⁻ -type diffusion layers 213 a and 213 b is removed in a self-aligned manner with the silicon oxide film spacer 215 and the field oxide film 205 (at the same time, the field insulating film 205 is formed to have a thickness equal to that of the gate electrode). 211, portions not covered by the silicon oxide film spacer 214 are thinned by about 30 nm), and the surfaces of the N ⁻ -type diffusion layers 213a and 213b are exposed in these portions [FIGS. 11 to 15 and 16 (a)]. , FIG.
(A)].

Next, in the same manner as in the first embodiment, first, the N ⁻ type diffusion layer 213 is formed using UHV-CVD.
After the native oxide film formed on the exposed surfaces of the a and 213b is removed, for example, disilane with a temperature of 625 ° C., a pressure of about 1 × 10 ⁻² Pa, a flow rate of about 2.0 sccm and 0.2
Anisotropic selective epitaxial growth with a doping gas at a flow rate of about sccm (1% phosphine diluted with hydrogen) allows the N ⁻ -type diffusion layer 213a,
The height (film thickness) is 4 in a self-aligned manner with the exposed surface of 213b.
N ⁺ -type (first silicon layer) single crystal silicon layers 216 a and 216 b of about 00 nm are formed, and the exposed surfaces of the N ⁻ -type diffusion layers 213 a and 213 b have a (junction) depth of about 70 nm. N ⁺ type diffusion layers 215a, 215
b is formed. [FIGS. 11 to 15, FIG. 16 (b),
FIG. 18 (b)].

In this embodiment, as in the first embodiment, the anisotropic selective epitaxial growth of the single crystal silicon layer is performed at a growth temperature in the range of 500 ° C. to 800 ° C.
It is preferable to carry out at a pressure in the range of 10 ⁻³ Pa and 5 × 10 ⁻² Pa. Further, even when monosilane is used as a source gas instead of disilane, anisotropic selective epitaxial growth of a single crystal silicon layer is possible, but the growth temperature at this time is 80 ° C. or higher than when disilane is used. The temperature shifts to a high temperature side of about 100 ° C.

Next, a silicon oxynitride film 219 having a thickness of 300 nm is deposited by a CVD method. [FIGS. 11 to 15,
16 (c) and 18 (c)].

The silicon oxynitride film 2 is etched back.
19, the single crystal silicon layer 21 is etched.
Etchback is performed until at least the upper surfaces of 6a and 216b are exposed and the silicon oxide film cap 212 is not exposed. [FIGS. 11 to 15, FIG. 17 (d), FIG.
(D)].

Thereafter, for example, formation of a silicon oxide film, B
The formation of the PSG film, the reflow of the BPSG film, the CMP, and the like are performed, and the second interlayer insulating film 221 made of a silicon oxide-based insulating film having a flat upper surface is formed. A node / contact hole 222 penetrating through second interlayer insulating film 221 and reaching the upper surface of single crystal silicon layer 217a is formed.
The diameter of the node contact hole 222 is 0.25 μm (=
F), the alignment deviation is large in the photolithography process, and the node contact hole 222
Even if the bottom of the first interlayer insulating film 220 protrudes from the upper surface of the single crystal silicon layer 217a, the first interlayer insulating film 220 functions as an etch stopper as in the first embodiment. [FIGS. 11 to 15, 17
(E), FIG. 19 (e)].

Next, the node contact hole 222 is filled with a contact plug 223 made of a conductor film such as an N ⁺ type polycrystalline silicon film. 8 film thickness over the entire surface
N ⁺ type polysilicon of about 00 nm is formed, which is patterned to form a storage node electrode 224. Note that the storage node electrode 224 and the contact plug 223 may be formed of the same N ⁺ -type polycrystalline silicon film, and may be formed by one-time patterning. For example, a capacity insulating film 135 made of an ONO film is formed, and a cell plate electrode 226 made of, for example, a 150 nm-thick N ⁺ -type polycrystalline silicon film is formed. An opening 227 having a diameter of about 400 nm is formed in the cell plate electrode 226 immediately above the single crystal silicon layer 217b by anisotropic etching. Subsequently, a third interlayer insulating film 2 made of a silicon oxide based insulating film having a flat upper surface
31 are formed. The portion where the opening 227 is formed penetrates through the third interlayer insulating film 231, the capacitor insulating film 225, and the second interlayer insulating film 221, and
A bit contact hole 232 reaching the upper surface of 7b is formed. The diameter of the bit contact hole 232 is also about F, and the misalignment becomes large in the photolithography process. The film 220 functions as an etch stopper. [FIGS. 11 to 15, 17 (f), 19 (f)].

Thereafter, a contact plug 223 made of a conductor film such as an N ⁺ -type polycrystalline silicon film is used.
The bit contact hole 232 is filled. For example, a tungsten film having a thickness of about 120 nm is formed by sputtering.
A conductor film made of a silicide film or the like is formed, and the conductor film is patterned to form a bit line 234. Further, a surface protection film 241 is formed, and the DRAM according to the present embodiment is completed. [FIGS. 11 to 15].

It is easy to apply the second embodiment to a DRAM having a COB structure. Further, the first embodiment (using an element isolation structure including a trench structure) is compared with a normal stacked DRAM (to which the second embodiment is applied (aside from the reduction of the effect)). It is also possible to apply. Although the first and second embodiments relate to an N-channel MOS transistor, respectively,
It is also possible to apply to an OS transistor.

[0063]

As described above, according to the present invention, a single crystal semiconductor layer is formed on a semiconductor substrate adjacent to an insulating film covering a gate electrode, and a first crystal semiconductor layer is formed on the insulating film covering the gate electrode.
Is formed, and a second interlayer insulating film made of a material having an etchant different from that of the first interlayer insulating film is formed over the first interlayer insulating film and the single crystal semiconductor layer. When the contact hole reaching the upper surface of the single crystal semiconductor layer is formed by etching the second interlayer insulating film,
The first interlayer insulating film can be used as an etching stopper. Therefore, when the contact hole is formed, even if there is a misalignment of the mask, the insulating film and the like existing under the first interlayer insulating film are not damaged. Current and short circuit between the gate electrode and the gate electrode and the like can be prevented. Further, since there is no need to increase the thickness of the single crystal semiconductor layer, there is no hindrance to the subsequent steps.

More specifically, it includes a reverse conductivity type diffusion layer and a reverse conductivity type single crystal silicon layer functioning as a contact pad provided in a self-aligned manner on the surface of the reverse conductivity type diffusion layer. Having a source / drain region of
In a MOS transistor of a reverse conductivity type provided on a one conductivity type silicon substrate having a main surface of {100}, a silicon oxide film cap for selectively directly covering an upper surface of a gate electrode is provided, and a gate electrode and a silicon oxide A silicon oxide film spacer that directly covers the side surface of the film spacer is provided. Further, a reverse conductivity type single crystal silicon layer directly connected to the surface of the self-aligned reverse conductivity type diffusion layer is provided on the silicon oxide film spacer. A drain region is formed, and the single crystal silicon layer functions as a contact pad. The single crystal silicon layer is formed by an anisotropic selective epitaxial growth method. Except for the single crystal silicon layer which is higher than the silicon oxide film cap, a first interlayer insulating film made of a silicon nitride film or a silicon oxynitride film covers the surface. As a result, by employing the present invention, it is easy to suppress a leak current and a short circuit between a wiring connected to these source / drain regions via the contact holes and a gate electrode or a substrate, and it is difficult to prevent a subsequent process. It is possible to have a single-crystal silicon layer of an optimum height.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view taken along line AA in FIGS. 5 and 6 showing a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view taken along line BB in FIGS. 5 and 6 showing the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view taken along the line CC in FIGS. 5 and 6, showing the first embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view taken along the line DD in FIGS. 5 and 6, showing the first embodiment of the present invention.

FIG. 5 is a schematic plan view showing the first embodiment of the present invention, and shows a positional relationship between an active region, a gate electrode serving also as a word line, and a single crystal silicon layer.

FIG. 6 is a schematic plan view showing the first embodiment of the present invention, showing a positional relationship among a gate electrode, a single crystal silicon layer, a bit line, and a storage node electrode.

FIG. 7 is a schematic cross-sectional view of the manufacturing process along the line AA in FIGS. 5 and 6 showing the first embodiment of the present invention.
The process proceeds in the order of (a), FIG. 7 (b), and FIG. 7 (c).

FIG. 8 is a schematic cross-sectional view of the manufacturing process along the line AA in FIGS. 5 and 6 showing the first embodiment of the present invention.
The process proceeds in the order of (d), FIG. 8 (e), and FIG. 8 (f).

FIG. 9 is a schematic cross-sectional view of a manufacturing step taken along line CC in FIGS. 5 and 6 showing the first embodiment of the present invention.
The process proceeds in the order of (a), FIG. 9 (b), and FIG. 9 (c).

FIG. 10 is a schematic cross-sectional view of a manufacturing step taken along line CC in FIGS. 5 and 6 showing the first embodiment of the present invention.
The steps proceed in the order of (d), FIG. 10 (e), and FIG. 10 (f).

FIG. 14 and FIG. 1 show a second embodiment of the present invention.
FIG. 5 is a schematic sectional view taken along line AA in FIG.

FIG. 14 and FIG. 1 show a second embodiment of the present invention.
FIG. 5 is a schematic sectional view taken along line BB in FIG.

FIGS. 14 and 1 show a second embodiment of the present invention.
FIG. 5 is a schematic cross-sectional view taken along line CC of FIG.

FIG. 14 is a schematic plan view showing a second embodiment of the present invention, and shows a positional relationship between an active region, a gate electrode serving also as a word line, and a single-crystal silicon layer.

FIG. 15 is a schematic plan view illustrating a second embodiment of the present invention, and illustrates a positional relationship among a gate electrode, a single crystal silicon layer, a bit line, and a storage node electrode.

FIG. 16 and FIG. 1 show a second embodiment of the present invention.
FIG. 17 is a schematic cross-sectional view of the manufacturing process taken along the line AA in FIG. 5, and the process proceeds in the order of FIG. 16 (a), FIG. 16 (b), and FIG.

FIGS. 14 and 1 show a second embodiment of the present invention.
FIG. 17 is a schematic cross-sectional view of the manufacturing process taken along line AA in FIG. 5, and the process proceeds in the order of FIG. 17D, FIG. 17E, and FIG.

FIGS. 14 and 1 show a second embodiment of the present invention.
FIG. 19 is a schematic cross-sectional view of a manufacturing step taken along line CC in FIG. 5, and the steps proceed in the order of FIG. 18A, FIG. 18B, and FIG.

FIGS. 14 and 1 show a second embodiment of the present invention.
FIG. 20 is a schematic cross-sectional view of the manufacturing process taken along the line CC in FIG. 5, and the process proceeds in the order of FIG. 19D, FIG. 19E, and FIG.

FIG. 20 is a schematic plan view showing a conventional technique, showing a positional relationship between an active region, a gate electrode serving also as a word line, and a single-crystal silicon layer.

FIG. 21 is a schematic plan view showing a conventional technique, showing a positional relationship among a gate electrode, a single crystal silicon layer, a bit line, and a storage node electrode.

FIG. 22 shows A in FIGS. 20 and 21 showing the prior art.
FIG. 3 is a schematic sectional view taken along line A.

FIG. 23 shows B in FIGS. 20 and 21 showing the prior art.
FIG. 3 is a schematic sectional view taken along line B.

FIG. 24 is a diagram showing a conventional technique;
It is a cross section schematic diagram in the C line.

FIG. 25 is a schematic cross-sectional view for explaining a problem with a conventional gate electrode.

FIG. 26 is a schematic cross-sectional view for explaining a problem with a conventional substrate.

[Explanation of symbols]

101, 201, 301 P-type silicon substrate 102, 202, 302 Active region 104, 204, 304 P ^- type diffusion layer 105 Field insulating film 106, 206, 306 Gate oxide film 111, 211, 311 Gate electrode 112, 212, 312 Silicon oxide film caps 113a, 113b, 213a, 213b, 313a,
313b N ^- type diffusion layers 114, 214, 314 Silicon oxide film spacers 115a, 115b, 215a, 215b, 315a,
315b N ⁺ type diffusion layers 116a, 116b, 117a, 117b, 216a,
216b, 217a, 217b, 316a1, 316b Single-crystal silicon layers 118a, 118b, 218a, 218b, 318a,
318b Source / drain region 119, 120, 219, 220 First interlayer insulating film 121, 221, 321 Second interlayer insulating film 131, 231, 331 Third interlayer insulating film 122, 232, 322 Bit contact hole 123 , 133, 223, 233, 323, 333 Contact plug 124, 234, 324 Bit line 132, 222, 332 Node contact hole 134, 224, 334 Storage node electrode 135, 225, 335 Capacitive insulating film 136, 226 336 Cell / plate electrode 141, 241, 341 Surface protective film 203 Groove 205, 305 Field oxide film 227 Opening

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/28-21/288 H01L 21/3205-21/3213 H01L 21/768 H01L 27/10

Claims (9)

(57) [Claims] 1. The semiconductor device according to claim 1, wherein the surface of the silicon substrate has a structure of <11.
An active region defined by sides in the <0> direction, a groove provided in the element isolation region on the surface of the silicon substrate surrounding the active region, and a field insulating film filling the groove.
A gate electrode traversing the surface of the active region in the <110> direction via a gate oxide film provided on the surface of the active region, a silicon oxide film cap that directly covers the upper surface of the gate electrode, A silicon oxide film spacer directly covering a side surface of the silicon film cap and the gate electrode; a reverse conductivity type diffusion layer provided on the surface of the active region in a self-aligned manner with the gate electrode and the field oxide film; A reverse conductivity type directly covering the surface of the reverse conductivity type diffusion layer which is self-aligned with the silicon film spacer and the field oxide film, and having a side surface composed of {110} surface and a top surface composed mainly of {100} surface. A source / drain region of the opposite conductivity type comprising a single crystal silicon layer of A first interlayer insulating film deposited so as to cover the insulating film spacer and to expose the upper surface of the single crystal silicon layer, and to cover the first interlayer insulating film and the single crystal silicon layer and to cover the first interlayer insulating film. A second interlayer insulating film of a different material from the film, a contact hole provided in the second interlayer insulating film and reaching the upper surface of the single crystal silicon layer, and connected to the source / drain region via the contact hole Semiconductor device comprising a wiring to be formed. 2. An active region defined by a side in the <110> direction provided on a surface of a silicon substrate of one conductivity type having a main surface of {100}, and a surface of the silicon substrate surrounding the active region. LOC provided in the element isolation region of
An OS type field oxide film, a gate electrode traversing the surface of the active region in the <110> direction via a gate oxide film provided on the surface of the active region, and directly covering the upper surface of the gate electrode A silicon oxide film cap, a silicon oxide film spacer directly covering the side surfaces of the silicon oxide film cap and the gate electrode, and a reverse provided on the surface of the active region in self-alignment with the gate electrode and the field oxide film. And directly covering the surface of the conductivity type diffusion layer and the surface of the reverse conductivity type diffusion layer which is self-aligned with the silicon oxide film spacer and the field oxide film.
A source / drain region of reverse conductivity type comprising a reverse conductivity type single crystal silicon layer having a side surface composed of a {0} plane and an upper surface composed mainly of a {100} plane; the field oxide film; the silicon oxide film cap; A first interlayer insulating film which covers the silicon oxide film spacer and is deposited so as to expose the surface and upper portions of the side surfaces of the single crystal silicon layer; A second material having a different material from the first interlayer insulating film.
And a contact hole provided in the second interlayer insulating film and reaching the upper surface of the single crystal silicon layer, and a wiring connected to the source / drain region through the contact hole. Semiconductor device. Wherein consists the first interlayer insulating film is a silicon nitride film or a silicon nitride oxide film, the second interlayer insulating film made of a silicon oxide film containing silicon film or phosphorus or boron oxide, claim 1 Or the semiconductor device according to 2 . Wherein said the minimum diameter of the smallest distance between the contact hole of the gate electrode are equal, the semiconductor device according to claim 1 or 2, wherein. Wherein said field insulation equal to the minimum diameter of the contact hole and the minimum width of the active areas sectioned by the film, a semiconductor device according to claim 1 or 2, wherein. 6. A method for forming a gate insulating film on a semiconductor substrate,
Forming a gate electrode on the gate insulating film, covering an upper surface and side surfaces of the gate electrode with an insulating film, forming a single crystal semiconductor layer on the semiconductor substrate adjacent to the insulating film covering the gate electrode; Forming a first interlayer insulating film on the insulating film covering the gate electrode; and forming a first interlayer insulating film on the first interlayer insulating film and the single crystal semiconductor layer using a material having an etchant different from the first interlayer insulating film. A second interlayer insulating film, a contact hole reaching the upper surface of the single crystal semiconductor layer is formed in the second interlayer insulating film, and a wiring is connected to the single crystal semiconductor layer through the contact hole. A method for manufacturing a semiconductor device. 7. A gate silicon oxide film is formed on a silicon substrate, a gate electrode is formed on the gate silicon oxide film, an upper surface and side surfaces of the gate electrode are covered with a silicon oxide film, and the gate electrode is covered. Forming a single crystal silicon layer on the silicon substrate adjacent to the silicon oxide film, forming a silicon nitride film on the silicon oxide film covering the gate electrode, and forming a silicon on the silicon nitride film and the single crystal silicon layer; A method of manufacturing a semiconductor device, comprising: forming an oxide film; forming a contact hole in the silicon oxide film to reach an upper surface of the single crystal silicon layer; and connecting a wiring to the single crystal silicon layer through the contact hole. 8. A groove is formed in an element isolation region surrounding an active region defined by a side in a <110> direction on a surface of a silicon substrate of one conductivity type having a main surface of {100},
Forming an insulating film on the entire surface, leaving the insulating film only in the trench to form a field insulating film; forming a gate oxide film on the surface of the active region by thermal oxidation; Forming a silicon oxide film covering the surface of the conductor film, patterning the silicon oxide film and the conductor film, and moving the surface of the active region through the gate oxide film in the <110> direction. And a silicon oxide film cap that directly covers the upper surface of the gate electrode, and a reverse conductivity type diffusion layer is formed on the surface of the active region using the gate electrode and the field oxide film as a mask. Forming a silicon oxide film on the entire surface, etching back the silicon oxide film by anisotropic etching to form the silicon oxide film cap and the gate electrode. Forming a silicon oxide film spacer directly covering the side surface of the silicon oxide film and removing the gate oxide film in a self-aligned manner with the silicon oxide film spacer and the field oxide film; Forming a reverse conductivity type single crystal silicon layer higher than the height of the silicon oxide film cap on the surface of the reverse conductivity type diffusion layer; forming a first interlayer insulating film on the entire surface; Polishing the first interlayer insulating film and the single-crystal silicon layer to expose the surface of the single-crystal silicon layer without exposing the silicon oxide film cap; Forming a second interlayer insulating film made of a material different from the above, and flattening the surface of the second interlayer insulating film; Forming a contact hole reaching the silicon layer, and forming a wiring connected to the single crystal silicon layer through the contact hole on the surface of the second interlayer insulating film. . 9. A step of forming a LOCOS type field oxide film in an element isolation region surrounding an active region defined by sides in a <110> direction on a surface of a silicon substrate of one conductivity type having a main surface of {100}. Forming a gate oxide film on the surface of the active region by thermal oxidation, forming a conductor film on the entire surface, forming a silicon oxide film covering the surface of the conductor film, and forming the silicon oxide film and the conductor Patterning a film to form a gate electrode traversing the surface of the active region in the <110> direction through the gate oxide film and a silicon oxide film cap directly covering the upper surface of the gate electrode; Forming a reverse conductivity type diffusion layer on the surface of the active region using the field oxide film as a mask, forming a silicon oxide film on the entire surface, and performing anisotropic etching. The silicon oxide film is etched back to form a silicon oxide film spacer that directly covers the side surfaces of the silicon oxide film cap and the gate electrode, and the silicon oxide film spacer and the field oxide film are self-aligned with each other. Removing the gate oxide film, and forming a reverse conductivity type single crystal silicon layer higher than the height of the silicon oxide film cap on the surface of the reverse conductivity type diffusion layer by anisotropic selective epitaxial growth of single crystal silicon. Forming a first interlayer insulating film on the entire surface, and etching back the first interlayer insulating film to expose the upper surface of the surface and side surfaces of the single crystal silicon layer without exposing the silicon oxide film cap; Forming a second interlayer insulating film having a material different from that of the first interlayer insulating film on the entire surface; Flattening the surface of the interlayer insulating film; forming a contact hole reaching the single crystal silicon layer in the second interlayer insulating film; and forming the contact hole on the surface of the second interlayer insulating film via the contact hole. Forming a wiring connected to the single-crystal silicon layer.