JP3121965B2 - Discharge panel drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discharge panel driving apparatus for adjusting a display color balance.

[0002]

2. Description of the Related Art FIG.
"20" of ID89-73 (issued on January 18, 1990)
Of the conventional discharge panel display device shown in Masahiko Seki et al., Wherein 1 is a front panel, 2 is a rear panel, 3 is a bank, and 4 is a bank. A priming space, 5 is a display cell, 6 is an auxiliary cell, 7 is a cathode, 8 is an anode, and 9 is an auxiliary anode.

FIG. 9 is a block diagram showing a control circuit of a matrix type display device as the discharge panel display device. In FIG. 9, reference numeral 11 denotes a display panel, 12 denotes a display control signal generator, 13 denotes a frame memory, 14 is a cathode drive circuit, 15 is a display anode drive circuit, and 16 is an auxiliary anode drive circuit.

FIG. 10 is a timing chart showing the operation of each of the electrodes 7 and 8 and the display cell 5 of the matrix type display device. FIG. 11 is a diagram showing the light emission time and gray scale between one feed in the matrix type display device. FIG. 4 is an explanatory diagram showing a control relationship.

Next, the operation will be described. First, an auxiliary discharge is generated between the auxiliary anode 9 to which a positive voltage is applied from a constant current source (not shown) and the cathode 7 to which the scanning pulse shown in FIG. 10 is applied. The metastable particles generated by this discharge diffuse from the auxiliary cell 6 to the display cell 5 through the priming space 4.

Thereafter, when light emission of the display cell 5 is required, a positive write pulse is applied to the anode 8 and a discharge is generated between the anode 8 and the cathode 7 to which the negative scan pulse is applied. .

After the scanning pulse, the cathode 7 maintains the sustain level for a certain period of time as shown in FIG. 10, so that in the display cell 5 in which discharge has occurred, the sustain pulse continuously applied to the display anode 8 causes a continuous pulse. Sustain discharge occurs. The sustain discharge is stopped by applying an erase pulse to the cathode 7.

Next, gradation control will be described. Now
One address of the frame memory 13 and the display panel 11
Of the frame memory 13 correspond to one-to-one dots.
It is assumed that the depth of one address is 8 bits.

Under the control of the display control signal generator 12,
Scanning of the cathode by the cathode drive circuit 14 is sequentially performed from top to bottom. When a positive voltage is applied to the auxiliary anode 9 by the auxiliary anode drive circuit 16 irrespective of the presence or absence of data display, an auxiliary discharge occurs, and the cathode scan is performed. , This auxiliary discharge also shifts sequentially from top to bottom.

Further, display data for one line is entirely read out and output to the anode 8 via the display anode drive circuit 15 in synchronization with the scanning timing. When the display data is valid,
A positive write pulse is applied to the anode 8, and a display discharge is performed by a priming effect immediately after the auxiliary discharge.

On the other hand, when the display data is invalid, the cathode 7
, No display discharge is performed.

When this operation is performed up to the last line at the bottom, one subfield ends. In this one subfield, display is performed for one bit out of the eight bits deep in the frame memory 13. Therefore, in this case, the number of subfields is eight, and the configuration contents of the subfields are shown in FIG.

In FIG. 11, first, the display scan of the bit having the highest weight, that is, the seventh bit of the most significant bit (MSB) is performed, and then the display scan of the bit having the lowest weight is performed. , The display scan of the 0th bit of the least significant bit (LSB) is shown.

In this case, in order to reflect the bit weight on the brightness of the display screen, the light emission maintaining period after writing is changed according to the bit weight. The control of the light emission sustain period is performed by the application timing of the erase pulse described above.
When the length of the light emission sustain period is represented by the number of sustain discharges by the sustain pulse, the seventh bit is 384 times, the sixth bit is 192 times in half, and the last 0th bit is 1/128 of the seventh bit and 3 times. Times.

According to this method, 25 bits with a depth of 8 bits are used.
Display of six gradations becomes possible. Assuming that the subfield “7” is 100%, the display duty is halved in order to 50% for the subfield “6”, and is 25% for one entire field.

[0016]

Since the conventional discharge panel display device is configured as described above, no measures are taken for color balance at the time of display, and some color balance is required for colorization. In the 256 gradation control, there is a problem that luminance is sacrificed.

[0017] according to claim 1 invention solution the above-mentioned problems
An object of the present invention is to provide a discharge panel driving device capable of performing a pulse width adjustment using a logic circuit with a unit of an operation frequency of a counter circuit with high accuracy.

[0018] The invention of claim 2 is an object to obtain a discharge panel drive device capable of obtaining a clear image by light emission luminance and the gradation number of the selected setting.

A third object of the present invention is to provide a discharge panel driving device capable of setting a good color balance by changing the relationship between the sustain pulses R, G, and B for each subfield.

A fourth object of the present invention is to provide a discharge panel driving device capable of setting a more accurate color balance.

[0021]

According to a first aspect of the present invention, there is provided a discharge panel driving apparatus, comprising: a waveform data generating circuit for outputting pulse data indicating a rising timing and a falling timing; And a first latch buffer for latching pulse data at a falling timing and a second latch buffer.
, And a first comparator and a second comparator for comparing output values of the first latch buffer and the second latch buffer with an ever-changing output value from the counter circuit. When the values compared by the first comparator match, the rising timing of the sustain pulse is set, and when the values compared by the second comparator match, the falling timing of the sustain pulse is set. As a reset.

According to a second aspect of the present invention, there is provided a discharge panel driving apparatus which selects a number of gradations for obtaining a predetermined light emission luminance, based on an output of the number of gradation selection circuit.
A field control circuit for controlling the number of subfields in one field of display; and a waveform read-only memory for outputting program control data of a discharge pulse required for discharge, and each output of the read-only memory and the field control circuit. Based on this, each row-side and column-side driver drives a row electrode and a column electrode of the discharge panel so that the emission luminance and the number of gradations are adjusted.

A discharge panel driving apparatus according to a third aspect of the present invention controls the mode selection circuit of the waveform read-only memory so as to adjust the pulse width of each of the R, G, and B sustain pulses for each subfield. A field control circuit is provided.

According to a fourth aspect of the present invention, there is provided a discharge panel driving device including a field control circuit for controlling a waveform data generation circuit so as to adjust the pulse width of each of the R, G, and B sustain pulses for each subfield. It is a thing.

[0025]

In the discharge panel driving device according to the first aspect of the present invention, the logic circuit constituting the waveform data generation circuit enables highly precise fine adjustment of the pulse width in units of the operation frequency of the counter circuit.

In the discharge panel driving device according to the second aspect of the present invention, the display duty is increased by selecting the number of display gradations by the gradation number selection circuit, and the overall luminance is improved.

According to the third aspect of the present invention, the discharge panel driving device changes the relationship among the sustain pulses R, G, and B for each subfield so as to balance the color of the emitted light.

In the discharge panel driving device according to the fourth aspect of the present invention, the relationship between the sustain pulses R, G, and B output from the pulse generator constituted by a logic circuit is changed to obtain a more accurate color balance. To be able to

[0029]

[Embodiment 1] An embodiment of the first aspect of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 21 denotes a discharge panel, 22 denotes a row-side driver, 23 denotes a column-side driver, 24 denotes a waveform read-only memory (hereinafter referred to as a waveform ROM) as a waveform memory,
Reference numeral 25 denotes a waveform ROM timing control circuit (waveform read-on memory timing control circuit), and reference numeral 26 denotes a waveform ROM mode selection circuit (waveform read-on memory mode selection circuit).

Further, FIG. 2 shows R, G, each of the sustain pulse applied to the column-side driver 23, which is separated into three color signals of B, and the mode selection state of the waveform ROM mode selection circuit 26 It is a time chart.

[0031] Next, the operation will be described. First, when displaying an image on the discharge panel 21, the row-side driver 22
And the column-side driver 23 are driven by a control pulse output from the waveform ROM 24 controlled by the waveform ROM timing control circuit 25 to cause a discharge in a target discharge cell, and the number of times corresponding to the weight of the display data. Only sustain discharge is performed.

In the case of a color image, one pixel is composed of three discharge cells for R, G, and B. Usually, the emission colors of R, G, and B are ultraviolet rays and phosphors are used. Is excited, so that if the discharge is performed under the same conditions, a balanced emission color cannot be obtained. Therefore, the pulse width of the sustain pulse is adjusted for each of R, G, and B to adjust the color balance of the emission color.

In FIG. 2, in the mode A selected by the waveform ROM mode selection circuit 26, the sustain pulses R, G, and B have the same pulse width. The width of R becomes large, the width of sustain pulse B becomes small while sustain pulse G remains unchanged.

[0034] Thus, the emission intensity of the R color in the mode B is strengthened, the emission intensity of the B color weakens. If the number of modes is increased to provide any combination of sustain pulses, the color balance can be easily adjusted.

Embodiment 2 FIG . In the above embodiment, the waveform ROM 2 is used as the pulse generator.
4 is used, a high-precision pulse generator can be formed by a logic circuit. FIG. 3 shows this embodiment.

[0036] That is, 27 the plurality of set-reset type flip-flop, 28 and 29 as the first comparator and the second comparator of the plurality of sets that are connected to a set input terminal and a reset input terminal of each flip-flop 27 Comparators, 30 and 31 are latch buffers serving as a first latch buffer and a second latch buffer connected to each of the comparators 28 and 29, 32 is a counter circuit, 33 is a waveform data generation circuit, an operation input unit, a processor , A latch buffer and a shift register.

In this embodiment, the waveform data generation circuit 33
Output data indicating the rising timing and the falling timing of each of the sustain pulses R, G, and B. The rising timing data of the sustain pulse R is latched in the latch buffer 30, and the data indicating the falling timing of the sustain pulse R is latched in the latch buffer 31.

The comparator 28 compares the output value of the latch buffer 30 with the ever-changing output value of the counter circuit 32, and sets the set / reset flip-flop 27 as the rising timing of the sustain pulse R when the two coincide with each other. On the other hand, the comparator 29
The output value of 1 and the output value of the counter circuit 32 are compared, and the set reset flip-flop 27 is reset when the two values coincide with each other as the falling timing of the sustain pulse R.

[0039] In this way, the desired sustain pulse R is generated. The sustain pulse G and the sustain pulse B are also generated by independent and similar circuit operations.

When the waveform ROM 24 as in the first embodiment is used, the number of pulse width patterns is limited by the number of address inputs of the ROM, but the logic circuit constituting the waveform data generation circuit 33 of this embodiment. Thus, fine adjustment can be performed in units of the operating frequency of the counter circuit 32.

With the spread of custom ICs such as a field programmable gate array (FPGA) in recent years, it can be realized with simple hardware.

Embodiment 3 FIG . Further, in the conventional example, since one field is divided into eight subfields and scanned for 256 gradations, the display duty is 25%. However, the emission luminance and the number of gradations are selected. Thus, the display duty can be improved.

[0043] This embodiment is shown in FIG. In FIG.
Reference numeral 34 denotes a field control circuit for controlling a sub-scan required for gradation display. In the case of 8-bit 256 gradations, one field is divided into eight sub-fields to perform display control.

[0044] However, not very necessary number of gradations, whereas, when it is desired to improve the overall brightness, operating in gray-scale level selecting circuit 35, a desired number of gradations of the control waveform from the field control circuit 34 The display duty is increased so as to be output.

FIG . 5 shows a subfield configuration when 4 bits and 16 gradations are used. In this case, the display duty is 50.
%. If the number of gradations is further reduced to achieve 1-bit binary display, the display duty becomes 100%.

In normal image display, if the contrast is high, the image quality is clear even if the luminance is insufficient, so that the luminance decreases when the number of gradations is large and increases when the number of gradations is small. Is a meaningful function.

Embodiment 4 FIG . Further, the color balance is affected by various conditions such as the amount of ultraviolet rays generated by the discharge and the characteristics of the phosphor excited by the ultraviolet rays, so that the relationship with the number of discharges may be non-linear. When gradation is displayed, the relationship between the sustain pulses R, G, and B, which are balanced in the MSB, that is, the subfield that displays the most significant bit, is directly changed to the LSB, that is, the subfield that displays the least significant bit. In some cases, it cannot be applied to subfields.

In this case, the relationship between the sustain pulses R, G, and B may be changed for each subfield. FIG. 6 shows the embodiment. In this embodiment, the field control circuit 3
When the sub-field 4 controls the sub-field, a part of the control signal is transmitted to the waveform ROM mode selection circuit 26, and the relationship between the sustain pulses R, G and B is synchronized with the sub-field switching as shown in FIG. Then, for example, the mode is switched from mode A to mode B, and changes every subfield.

Embodiment 5 FIG . In the fourth embodiment, the waveform ROM mode selection circuit 26 is controlled by the field control circuit 34 so that the waveform ROM 2
The pulse width of each of the sustain pulses R, G, and B output from FIG. 4 is changed. The waveform data generation circuit 33 shown in the second embodiment is controlled to generate a pulse generated by a logic circuit. The relationship between the sustain pulses R, G, and B output from the detector may be changed. FIG. 7 shows the embodiment.

[0050] According to this, when the field control circuit 34 controls the sub-fields, some of the control signal is transmitted to the waveform data generation circuit 33, each set of the latch buffer 30, 31, comparators 28 and 29, When the operation of the set / reset flip-flop 27 changes, for example, the pulse width of the sustain pulse R changes, and similarly, the sustain pulses G and B also change, and the relationship between the sustain pulses R, G and B changes.

[0051] Therefore, according to this embodiment, the fourth embodiment
, A more accurate color balance can be obtained.

[0052]

As described above , according to the first aspect of the present invention, the first latch buffer for latching the pulse data of the rising timing and the pulse data of the falling timing of the pulse data indicating the rising timing and the falling timing is provided. A second latch buffer; a first comparator and a second comparator for comparing output values of the first latch buffer and the second latch buffer with an ever-changing output value from a counter circuit; The reset flip-flop is set as the rising timing of the sustain pulse when each value compared in the first comparator matches, and is set as the rising timing of the sustain pulse when each value compared in the second comparator matches. Reset as falling timing Having urchin configuration, using logical circuits, which the pulse width adjustment in units of operating frequency of the counter circuit can be realized with high accuracy is the effect obtained.

[0053] Based on the output of the gray scale number selection circuit according to the invention of claim 2, a field control circuit for controlling the number of subfields in one field display, the program control data of discharge pulses required discharge A read-only memory for outputting, based on the outputs of the read-only memory and the field control circuit,
Each driver on the row side and the column side is configured to drive the electrode of the row and the electrode of the column of the discharge panel so that the emission luminance and the number of gradations are adjusted. There is an effect that what can display a clear image can be obtained by setting.

[0054] By According if the field control circuit to the third aspect of the present invention, to adjust R, G, and pulse width of each sustain pulse of B for each subfield, controlling the mode selection circuit of the waveform read-only memory By changing the relationship between the sustain pulses for each subfield, it is possible to obtain the required emission luminance and obtain a color balance that can be set for each gradation of the multi-gradation control. is there.

[0055] The field control circuit according to the invention of claim 4, the sustain pulse R for each sub-pulse, G, since it is configured so as to adjust the pulse width of B, and which further can be set with high color balance accurate There is an effect that can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a discharge panel driving device according to a first embodiment of the present invention .

FIG. 2 is a timing chart showing signals of respective parts of a block in FIG. 1;

FIG. 3 is a block diagram showing a discharge panel driving device according to a second embodiment of the present invention .

FIG. 4 is a block diagram showing a discharge panel driving device according to Embodiment 3 of the present invention .

FIG. 5 is an explanatory diagram showing a subfield configuration in the embodiment of FIG.

FIG. 6 is a block diagram showing a discharge panel driving device according to Embodiment 4 of the present invention .

FIG. 7 is a block diagram showing a discharge panel driving device according to Embodiment 5 of the present invention .

FIG. 8 is a configuration diagram showing a structure of a conventional discharge panel display device.

FIG. 9 is a block diagram illustrating a driving method of a conventional discharge panel display device.

FIG. 10 is a timing chart showing an operation of the conventional discharge panel display device.

FIG. 11 is an explanatory diagram showing a relationship between a light emission time in one field and gradation control in a conventional discharge panel display device.

[Explanation of symbols]

21 Discharge Panel 22 Row Side Driver 23 Column Side Driver 24 Waveform ROM (Waveform Read Only Memory) 25 Waveform ROM Timing Control Circuit (Waveform Read Only Memory Timing Control Circuit) 26 Waveform ROM Mode Selection Circuit (Waveform Read Only Memory Mode Selection Circuit) 27 Set-Reset Flip-Flop 28 Comparator (First Comparator) 29 Comparator (Second Comparator) 30 Latch Buffer (First Latch Buffer) 31 Latch Buffer (Second Latch Buffer) 32 Counter Circuit 33 Waveform Data Generation Circuit 34 Field control circuit 35 Tone number selection circuit

Claims (4)

(57) [Claims] 1. A waveform data generating circuit for outputting pulse data indicating rising timing and falling timing, and a pulse data and a falling timing of the rising timing of the pulse data are provided for R, G, and B color signals. A first latch buffer and a second latch buffer for latching the pulse data of the first and second latch buffers, and a first latch buffer for comparing the output values of the first latch buffer and the second latch buffer with the ever-changing output value from the counter circuit. A comparator and a second comparator;
The time when the values compared by the first comparator match is set as the rising timing of the sustain pulse, and the value when the values compared by the second comparator match is set as the falling timing of the sustain pulse. A discharge panel drive device comprising: a set / reset flip-flop to be reset. 2. A gradation number selection circuit for selecting a gradation number for obtaining a predetermined light emission luminance, and controlling the number of subfields in one field of display based on an output of the gradation number selection circuit. A field control circuit, a waveform read-only memory for outputting program control data of a discharge pulse necessary for discharging to obtain the light emission luminance, and a light emission luminance and a gradation based on each output of the read only memory and the field control circuit. So that the key is adjusted,
A discharge panel driving device comprising: a row driver and a column driver for driving a row electrode and a column electrode of the discharge panel. 3. A waveform read-only memory timing control circuit for outputting a waveform control signal of a pulse corresponding to a discharge time of a discharge generated between a row electrode and a column electrode constituting a discharge panel; A waveform read-only memory mode selection circuit for selecting R, G, B color signals by mode, and a waveform read-only memory for adjusting the pulse width of each of the R, G, B sustain pulses for each subfield. A field control circuit for controlling a mode selection circuit; a waveform read only memory for receiving each output of the waveform read only memory mode selection circuit and the waveform read only memory timing control circuit and outputting program control data of the discharge pulse; Based on the program control data from the waveform read-only memory, Discharge panel drive device and a row-side driver and the column-side driver for driving the column electrodes. 4. A waveform data generating circuit for outputting pulse data indicating rising timing and falling timing, and said waveform data generating circuit adjusting the pulse width of each of R, G, B sustain pulses for each subfield. A field control circuit for controlling the circuit, a first latch buffer provided for the R, G, and B color signals and a second latch buffer for latching the pulse data of the rising timing and the falling timing of the pulse data; A latch buffer, a first comparator and a second comparator for comparing output values of the first latch buffer and the second latch buffer with an ever-changing output value from the counter circuit, and The rising timing of the sustain pulse is when the values to be compared match. It is set to, on the other hand, the second
And a set-reset flip-flop that is reset when the values compared by the comparators match each other as the fall timing of the sustain pulse.