JP3120840B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a flip-chip connection structure using solder balls.

[0002]

2. Description of the Related Art A conventional example will be described with reference to FIGS. FIG. 7A is a plan view of a pad electrode in a semiconductor device having a conventional flip-chip connection structure, and shows only a pattern located above the uppermost wiring layer. FIG.
(B) to (D) show AA 'in the chip around the wafer.
9 (E) to 9 (G) are enlarged cross-sectional views taken along line AA ′ of the central chip of the wafer.

With reference to FIGS. 8B to 8D, a conventional semiconductor device having a flip-chip connection structure, particularly a wafer peripheral chip, will be described. First, FIG. 8 (B)
As shown in FIG.
An uppermost wiring layer 12 composed of an iN / Ti film, an AlCu film, and a TiN / Ti film is sequentially formed by a conventional sputtering technique to form a desired wiring pattern. Next, an insulating film 13 made of an oxide film and a nitride film is formed on the entire surface of the wafer by a CVD technique. The insulating film 13 is composed of a multilayer film of a polyimide 11, a plasma oxide film, and a plasma nitride film. Subsequently, a polyimide 11 is applied thereon.

After that, the insulating film 13 is anisotropically etched only at a portion connected to the uppermost wiring layer 12 to open the cover pattern 1 shown in FIG.

Next, after a TiW film 9 and a Cu film 7 are sequentially formed on the entire surface of the wafer by a sputtering technique, a resist 5 is applied, and a resist pattern is formed into a desired pad electrode pattern by a lithography technique (FIG. 8).
(B)).

Next, the Cu film 7 and the TiW film 9 are sequentially wet.
Etching is performed by etching. As an etchant
Is, for example, P heated to 60 ° C. during Cu etching.
Use HC liquid. Phosphoric acid is phosphoric acid, nitric acid, glacial acetic acid
And water in a ratio of about 1: 1: 1: 50.
Liquid. On the other hand, at the time of TiW etching, for example, H _Two
O_Two(Aqueous hydrogen peroxide). Here, the Cu film wafer
In the wet etching process, the etching proceeds isotropically
Therefore, the Cu film is side-etched (FIG. 8C).

After that, as shown in FIG. 8D, the resist 5 is peeled off, and the solder balls 15 are formed on the pattern of the Cu film 7.
To form a semiconductor device having a desired flip-chip connection structure.

Although the description has been given of the case of the chip at the peripheral portion of the wafer, the chip at the central portion of the wafer is manufactured by the same process as shown in FIGS.

FIG. 10 is a model diagram showing a state in which a plurality of semiconductor chips are arranged on a wafer. FIG.
Each square in (A) corresponds to a semiconductor chip. Regardless of the layout of the lower wiring, the pad electrode 2
0 is provided in the entire layout area. The number of pad electrodes is
For example, about 1000 to 1500 pins per chip.

Although a large number of pad electrodes 20 are formed on the entire surface of the wafer, it is difficult to reduce these dimensional variations by the prior art.

That is, in a semiconductor device having a flip-chip connection structure according to the prior art, the Cu film at an unnecessary portion when the pad electrode 20 is formed as shown in FIGS. Is removed by wet etching, the chip at the peripheral portion of the wafer has a larger side etch than the chip at the central portion of the wafer due to the batch-type characteristics of the wet etching apparatus, and the completed pad dimensions of the pad electrode 20 are reduced. Was. The cause of the dimensional difference of the pad electrode 20 due to the side etching is that the chip around the wafer has a larger wraparound of the etching solution than the chip at the center of the wafer, and the chip around the wafer has a larger etching rate. This is because the etching rate of Cu, which proceeds isotropically, increases.

The Cu film constituting the electrode pad pattern is usually about 3 μm thick. However, since the thickness is large, there is a large variation in the amount to be etched. In some cases, the dimensional difference from the finished pad dimensions of the chip was significantly large. For example, when a 6-inch wafer (wafer diameter 150 mm) is wet-etched with Cu at 60 ° C. using a PHC solution and wet-etched with TiW using H ₂ O ₂ , the wafer peripheral portion and the wafer central portion have a thickness of 10 μm to 20 μm. Dimensional difference occurs.

[0013]

As described above, in the conventional semiconductor device having the flip-chip connection structure, the completed pad dimensions of the chip around the wafer are limited to the following.
There is a disadvantage that the size is smaller than the completed pad size of the chip at the center of the wafer. Therefore, when the Cu film as the pad electrode is connected to the solder ball, if there is a dimensional difference in the pad electrode, the contact area between the pad electrode and the solder ball varies, and the shape of the finally formed solder ball differs. As a result, the height of the solder balls varied. In particular, when the height of the solder ball varies from chip to chip, a stable connection condition cannot be found at the time of connection with the flip chip substrate in a later step, and the yield of LSI is reduced due to a defective connection open with the flip chip substrate. Was causing it.

Conversely, if the etching time is shortened in order to secure the pad size of the chip at the peripheral portion of the wafer, the etching margin at the central portion of the wafer becomes insufficient, and the etching residue of the Cu film and TiW film occurs due to process variations. However, there is a problem that adjacent pads are short-circuited at the center of the wafer, and the yield is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and does not increase the number of mask patterns and does not complicate the process. The purpose is to reduce.

[0016]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention suppresses the dimensional variation of the pad electrode by making it difficult for an etching solution to enter between the dummy pattern and the pad electrode when forming the pad electrode pattern. It is.

The present invention is specified by the following items [1] to [13]. [1] A semiconductor device comprising a semiconductor chip and a pad electrode formed on the surface thereof and having a flip-chip connection structure using solder balls, wherein the pad electrode is provided at a predetermined distance from the periphery of the pad electrode. A semiconductor device having a dummy pattern formed so as to go around the periphery, wherein the dummy pattern is formed at an interval of 5 to 50 μm from a periphery of the pad electrode. [2] A semiconductor device comprising a semiconductor chip and a pad electrode formed on the surface thereof and having a flip-chip connection structure using solder balls, wherein the pad electrode is separated from the periphery of the pad electrode by a predetermined distance. A semiconductor device having a dummy pattern formed so as to go around the periphery, wherein the dummy pattern has a width of 5 to 50 μm in a direction orthogonal to a peripheral edge of the pad electrode. [3] A semiconductor device comprising a semiconductor chip and a pad electrode formed on the surface thereof and having a flip-chip connection structure using solder balls, wherein the pad electrode is provided at a predetermined distance from the periphery of the pad electrode. A plurality of block-shaped dummy patterns formed so as to go around the periphery, wherein the length of the block-shaped dummy pattern in a direction along a peripheral edge of the pad electrode is 10 to 100 μm; A semiconductor device, wherein a distance between the dummy patterns is 5 to 50 μm. [4] A semiconductor device comprising a semiconductor chip and a pad electrode formed on the surface thereof and having a flip-chip connection structure using solder balls, wherein the pad electrode is provided at a predetermined distance from the periphery of the pad electrode. A semiconductor device, comprising: a plurality of block-shaped dummy patterns formed so as to go around the periphery, wherein the dummy patterns are formed at intervals of 5 to 50 μm from the periphery of the pad electrode. [5] A semiconductor device comprising a semiconductor chip and a pad electrode formed on the surface thereof and having a flip-chip connection structure using solder balls, wherein the pad electrode is provided at a predetermined distance from the periphery of the pad electrode. A semiconductor device having a plurality of block-shaped dummy patterns formed so as to go around the periphery, wherein the dummy patterns have a width of 5 to 50 μm in a direction orthogonal to a peripheral edge of the pad electrode. [6] A semiconductor device comprising a semiconductor chip and a pad electrode formed on the surface thereof and having a flip-chip connection structure using solder balls, wherein the pad electrode is arranged at a predetermined distance from the periphery of the pad electrode. A plurality of block-shaped slits are provided so as to be parallel to the peripheral edge, and the dimension of the block-shaped slit is such that the length along the peripheral edge is 5 to 50 μm and the direction perpendicular to this direction is A semiconductor device having a width of 5 to 50 μm. [7] a step of forming a conductive layer on a semiconductor substrate provided with a semiconductor chip, a pad electrode forming mask, and a dummy on the conductive layer at a predetermined distance from the periphery of the pad electrode forming mask A method for manufacturing a semiconductor device, comprising: providing a pattern forming mask; and wet-etching the conductive layer to form a pad electrode and a dummy pattern. [8] a step of forming a conductive layer on a semiconductor substrate on which a semiconductor chip is provided, a pad electrode forming mask, and a plurality of pads formed on the conductive layer at predetermined intervals from the periphery of the pad electrode forming mask Providing a mask for forming a block-shaped dummy pattern and wet etching the conductive layer to form a pad electrode and a dummy pattern. [9] The block-shaped dummy pattern forming mask has a length of 10 to 100 μm in a direction along a peripheral edge of the pad electrode forming mask, and a distance between adjacent block-shaped dummy pattern forming masks is small. 5-50 μm
The method for manufacturing a semiconductor device according to [8], wherein: [10] The semiconductor device according to any one of [7] to [9], wherein the dummy pattern forming mask is formed at an interval of 5 to 50 μm from a periphery of the pad electrode forming mask. Manufacturing method. [11] The dummy pattern forming mask has a width of 5 to 5 in a direction orthogonal to a peripheral edge of the pad electrode forming mask.
The method for manufacturing a semiconductor device according to any one of [7] to [10], wherein the thickness is 0 μm. [12] A step of forming a conductive layer on a semiconductor substrate provided with a semiconductor chip, a step of providing a pad electrode forming mask on the conductive layer, and wet etching of the conductive layer to form a pad electrode Forming a plurality of block-shaped slits so that the pad electrode forming mask is parallel to the peripheral edge at a predetermined distance from the peripheral edge thereof. Production method. [13] The dimension of the block-shaped slit is 5 to 50 in the direction along the periphery of the pad electrode forming mask.
μm, and the width in a direction orthogonal to this direction is 5 to 50.
[12] The method for manufacturing a semiconductor device according to [12], wherein the thickness is μm.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A dummy pattern in a semiconductor device of the present invention is formed so as to go around a pad electrode. As shown in FIG. 1A, a dummy pattern formed continuously in a loop may be used.
A form in which a plurality of block-shaped dummy patterns are provided as shown in FIG. In the case where a plurality of block-shaped dummy patterns are provided, since the etching liquid easily escapes, the remaining of the etching liquid hardly occurs as described later, and the dimensional variation of the pad electrode can be further suppressed.

When a plurality of block-shaped dummy patterns are provided, the dimensions of each block-shaped dummy pattern are preferably as follows. That is, the length in the direction along the pad electrode periphery is preferably 10 to 100 μm,
More preferably, the thickness is 20 to 50 μm. The distance between the adjacent block-shaped dummy patterns is preferably 5 to 50 μm, more preferably 10 to 30 μm. This makes it possible to more effectively prevent the unetched portion and to further suppress the dimensional variation of the pad electrode.

The dummy pattern is preferably 5 to 50 μm, more preferably 10 to 50 μm from the periphery of the pad electrode.
Preferably, they are formed at intervals of 30 μm. This makes it difficult for the etchant to enter between the dummy pattern and the pad electrode, thereby further suppressing the dimensional variation of the pad electrode.

The width of the dummy pattern in a direction orthogonal to the periphery of the pad electrode is preferably 5 to 50 μm, more preferably 10 to 30 μm. By setting the thickness to 50 μm or less, the density at which the semiconductor devices are arranged in the wafer plane can be increased. When the thickness is 5 μm or more, the interval between the dummy pattern and the pad electrode can be reliably ensured. The “width in a direction orthogonal to the pad electrode periphery” refers to, for example, the width of the dummy electrode in FIG. 1A, and the short width of the rectangular dummy electrode arranged on the pad electrode periphery in FIG. The length of the side.

When a plurality of block-shaped slits are provided on the pad electrode as shown in FIG.
The length along the pad electrode periphery is preferably 5 to 5
0 μm, more preferably 10 to 30 μm. Further, the width in the direction orthogonal to this direction is preferably 5 to 50 μm.
m, more preferably 10 to 30 μm. This makes it difficult for the etchant to enter between the dummy pattern and the pad electrode, thereby further suppressing the dimensional variation of the pad electrode.

The method of manufacturing a semiconductor device according to the present invention
The present invention relates to a method of manufacturing a semiconductor device having a semiconductor chip and a pad electrode formed on the surface thereof and having a flip-chip connection structure using solder balls. Here, the dummy pattern forming mask in the method for manufacturing a semiconductor device of the present invention is formed so as to go around the periphery of the pad electrode. The dummy pattern forming mask may be in a continuous form in a loop shape, or may be in a form including a plurality of block-shaped dummy patterns. When a plurality of block-shaped dummy pattern forming masks are provided, the etchant easily escapes, so that the etchant does not easily remain as described later, and the dimensional variation of the pad electrode can be further suppressed.

When a plurality of block-shaped dummy pattern forming masks are provided, the dimensions of each block-shaped dummy pattern forming mask are preferably as follows. That is, the length in the direction along the peripheral edge of the pad electrode is preferably 10 to 100 μm, more preferably 20 to 5 μm.
0 μm. The distance between adjacent block-shaped dummy pattern forming masks is preferably 5 to 50.
μm, more preferably 10 to 30 μm. This makes it possible to more effectively prevent the unetched portion and to further suppress the dimensional variation of the pad electrode.

The dummy pattern forming mask is preferably 5 to 50 μm from the periphery of the pad electrode forming mask.
More preferably, they are formed at intervals of 10 to 30 μm. This makes it difficult for the etchant to enter between the mask for forming the dummy pattern and the mask for forming the pad electrode, thereby further suppressing the dimensional variation of the pad electrode.

The width of the dummy pattern forming mask in a direction perpendicular to the periphery of the pad electrode is preferably 5 to 50.
μm, more preferably 10 to 30 μm. 50μ
By setting m or less, the density at which the semiconductor devices are arranged in the plane of the wafer can be increased. When the thickness is 5 μm or more, the gap between the dummy pattern forming mask and the pad electrode forming mask can be reliably ensured.

When a plurality of block-shaped slits are provided in the pad electrode forming mask as shown in FIG. 3A, the length of the slits in the direction along the periphery of the pad electrode forming mask is preferably 5 to 5. 50 μm, more preferably 1 μm
0 to 30 μm. Further, the width in the direction perpendicular to this direction is preferably 5 to 50 μm, more preferably 10 to 50 μm.
It is 30 μm. This makes it difficult for the etchant to enter between the mask for forming the dummy pattern and the mask for forming the pad electrode, thereby further suppressing the dimensional variation of the pad electrode.

[0028]

(Embodiment 1) A first embodiment of the present invention will be described with reference to FIGS. FIG. 1A is a plan view of a pad electrode in a semiconductor device having a flip-chip connection structure according to the first embodiment. FIGS. 2B to 2D are enlarged cross-sectional views taken along the line AA ′ in the order of steps.

The difference between this embodiment and the prior art is that
As shown in FIG. 1A, a dummy pattern 4 is provided around the pad electrode pattern 3 along the periphery of the pad electrode pattern 3. Hereinafter, a method of manufacturing a semiconductor according to the present embodiment will be described.

First, as shown in FIG. 2B, a TiW film 9 and a Cu film 7 are sequentially formed on the entire surface of the wafer by a sputtering technique according to a conventional technique, and then a resist is applied by a lithography technique to form a resist of a pad electrode pattern. I do. The resist patterns 5 and 6 shown in FIG.
Is a mask for forming a pad electrode pattern 3 and a dummy pattern 4 surrounding the pad electrode pattern 3 as shown in FIG. The interval between the resist patterns 5 and 6 is about 30 μm, and the width of the resist pattern 6 is about 30 μm.

Next, as shown in FIG. 2C, the Cu films are wet-etched with a PHC solution using the resist patterns 5 and 6 as masks to form patterns of the Cu films 7 and 8. Next, resist patterns 5 and 6 and Cu films 7 and 8
Is used as a mask to perform wet etching of the TiW film with an H ₂ O ₂ solution to form a pattern of the TiW films 9 and 10. Next, as shown in FIG. 2D, the resist patterns 5 and 6 are peeled off, and solder balls 15 are mounted on the Cu film 7 to form a semiconductor device having a desired flip-chip connection structure.

In the first embodiment, when the pad electrode pattern is wet-etched as shown in FIG. 2B, a dummy pattern is provided outside the pad electrode pattern. The PHC solution as an etchant is less likely to enter the narrow space portion regardless of the pad position in the wafer surface, and the progress of etching of the Cu film 7 in the lower layer portion of the portion a is uniformly slowed down. Then T
During wet etching of the iW film, the resist spacing a and C
Since the distance b between the u films is small, H ₂ O _{2 as an} etchant does not easily enter the portions a and b, and the etching progresses slowly.

Therefore, the progress of etching in the space between the pad electrode pattern 3 and the adjacent dummy pattern 4 shown in FIG. 1A is uniformly slowed down over the entire surface of the wafer. Since the difference in the etching rate of the film becomes smaller, the variation in the finished dimensions of the pad electrode can be reduced. As shown in FIGS. 2C and 2D, the Cu film 8 and the TiW film 10, which are dummy patterns, are patterns that are not particularly required in a subsequent process, and the finished dimensions may be reduced during wet etching. It is sufficient that the completed pad dimensions of the pad electrode pattern formed by the Cu film 7 and the TiW film 9 are secured. The completed dimensions of the dummy pattern do not affect the connection strength when connecting the pad electrode to the solder ball and the height of the solder ball after connection.

It is preferable that the dummy pattern is provided for all pad patterns. By doing so, the effect of improving the yield of LSI increases.

(Embodiment 2) A second embodiment of the present invention will be described with reference to FIGS. FIG. 3A is a plan view of a semiconductor device having a flip-chip connection structure according to the second embodiment, and FIGS. 4B to 4D are enlarged cross-sectional views taken along line AA ′ in the order of steps. FIG.

In this embodiment, as shown in FIG. 3A, a pad pattern provided with a slit pattern 16 along the periphery of the pad pattern 3 is formed.

With such a structure, FIG.
As shown in (C), during the Cu and TiW wet etching, the Cu film and the TiW film below the slit pattern are hardly wet-etched, and the completed dimensions of the pad electrode do not depend on the position in the wafer surface. And become uniform. The size of the slit is about 30 μm in width, the length is preferably about 10 to 20 μm, and the slit-slit interval is set to about 10 μm.
It is appropriate to provide along the outermost periphery of the pad pattern at a position 10 μm from the outermost periphery of the pattern, which is highly effective.

(Embodiment 3) FIGS. 5 and 6 show a third embodiment.
This will be described with reference to FIG. FIG. 5A is a plan view of a semiconductor device having a flip-chip connection structure according to the third embodiment, and FIGS. 6B to 6D are enlarged cross-sectional views taken along line AA ′ in the order of steps. FIG.

In this embodiment, a plurality of dummy patterns 17 are formed along the outermost periphery of the pad pattern 1 as shown in FIG.

In comparison with the first embodiment, a plurality of dummy patterns 15 are provided in a line along the outermost periphery in such a manner that one dummy pattern is divided. Therefore, as shown in FIG. 6 (C), in the lower part of the c portion where the resist interval is small at the time of Cu wet etching, the lower Cu film and the TiW film are hardly wet-etched, and the finished pads of the chip at the peripheral portion of the wafer and the chip at the central portion of the wafer are formed. Dimensional differences are reduced. Further, as compared with the first embodiment, since the etchant is easily removed after etching the Cu film, the etchant is less likely to remain, and the dimensional variation of the pad electrode can be further suppressed. Therefore, as shown in FIGS. 6B and 6C, the completed dimensions of the pad electrode after etching the Cu film and the TiW film can be made even more uniform in the wafer surface without depending on the position in the wafer surface.

The size of the dummy pattern 17 is about 30 μm in width, and the length is about 30 to 50 μm.
It is preferable to arrange them at an interval of 0 μm, and it is appropriate to set the interval between the pad electrode patterns 3 to 20 μm to 20 μm, and the effect is large.

[0042]

As described above, according to the present invention, by forming a dummy pattern around a pad electrode pattern, the progress of etching between the pad electrode pattern and the dummy pattern during wet etching is reduced, and the etching rate is reduced. , The variation in finished pad dimensions within the wafer surface can be reduced without increasing the number of manufacturing steps. As a result, there is an effect of reducing the displacement of the connection between the pad electrode and the solder ball, an effect of making the height of the solder ball constant, and an effect of significantly increasing the yield of the semiconductor device having the flip-chip connection structure.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device of the present invention.

FIG. 2 is a process sectional view of the semiconductor device of the present invention.

FIG. 3 is a process sectional view of the semiconductor device of the present invention.

FIG. 4 is a plan view of the semiconductor device of the present invention.

FIG. 5 is a process sectional view of the semiconductor device of the present invention.

FIG. 6 is a process sectional view of the semiconductor device of the present invention.

FIG. 7 is a plan view of a conventional semiconductor device.

FIG. 8 is a process sectional view of a conventional semiconductor device.

FIG. 9 is a process sectional view of a conventional semiconductor device.

FIG. 10 is a model diagram of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Cover pattern 2 Top layer wiring pattern 3 Pad electrode pattern 4 Dummy pattern 5, 6 Resist pattern 7, 8 Cu film 9, 10 TiW film 11 Polyimide 12 Top layer wiring 15 Solder ball 16 Slit pattern 18 Semiconductor device in central part of wafer 19 Semiconductor device around wafer 20 Electrode pad portion A portion Narrow space between resist patterns b portion Narrow space between Cu film patterns

Claims (13)

(57) [Claims] 1. A semiconductor device comprising: a semiconductor chip; and a pad electrode formed on a surface of the semiconductor device, the semiconductor device having a flip-chip connection structure using solder balls, wherein the pad is separated from a periphery of the pad electrode by a predetermined distance. A semiconductor device having a dummy pattern formed so as to go around the periphery of an electrode, wherein the dummy pattern is formed at an interval of 5 to 50 μm from a periphery of the pad electrode. 2. A semiconductor device comprising: a semiconductor chip; and a pad electrode formed on a surface of the semiconductor device, the semiconductor device having a flip-chip connection structure using solder balls, wherein the pad is separated from a periphery of the pad electrode by a predetermined distance. A semiconductor device having a dummy pattern formed so as to go around the periphery of an electrode, wherein the dummy pattern has a width of 5 to 50 μm in a direction orthogonal to a peripheral edge of the pad electrode. 3. A semiconductor device comprising: a semiconductor chip; and a pad electrode formed on a surface of the semiconductor device, the semiconductor device having a flip-chip connection structure using solder balls, wherein the pad is separated from a periphery of the pad electrode by a predetermined distance. It has a plurality of block-shaped dummy patterns formed so as to go around the periphery of the electrode, and the block-shaped dummy patterns are:
The length in the direction along the periphery of the pad electrode is 10 to 100
A semiconductor device, wherein the distance between adjacent block-shaped dummy patterns is 5 to 50 μm. 4. A semiconductor device comprising a semiconductor chip and a pad electrode formed on the surface thereof and having a flip-chip connection structure using solder balls, wherein the pad is separated from a periphery of the pad electrode by a predetermined distance. A semiconductor having a plurality of block-shaped dummy patterns formed so as to go around the periphery of the electrode, wherein the dummy pattern is formed at an interval of 5 to 50 μm from a periphery of the pad electrode; apparatus. 5. A semiconductor device, comprising: a semiconductor chip; and a pad electrode formed on a surface of the semiconductor device, the semiconductor device having a flip-chip connection structure using solder balls, wherein the pad is separated from a periphery of the pad electrode by a predetermined distance. A semiconductor having a plurality of block-shaped dummy patterns formed so as to go around the periphery of the electrode, wherein the dummy pattern has a width of 5 to 50 μm in a direction orthogonal to a peripheral edge of the pad electrode; apparatus. 6. A semiconductor device comprising a semiconductor chip and a pad electrode formed on the surface thereof and having a flip-chip connection structure using solder balls, wherein the pad electrode has a predetermined distance from the periphery of the pad electrode. A plurality of block-shaped slits are provided so as to be parallel to the peripheral edge, and the dimension of the block-shaped slit is 5 to 50 μm in the direction along the peripheral edge, and is orthogonal to this direction. A semiconductor device having a width in a direction of 5 to 50 μm. 7. A step of forming a conductive layer on a semiconductor substrate on which a semiconductor chip is provided, a mask for forming a pad electrode, and a predetermined distance from a periphery of the mask for forming a pad electrode on the conductive layer. Providing a dummy pattern forming mask, and wet etching the conductive layer to form a pad electrode and a dummy pattern. 8. A step of forming a conductive layer on a semiconductor substrate provided with a semiconductor chip, a pad electrode forming mask, and a predetermined distance from a periphery of the pad electrode forming mask on the conductive layer. And providing a plurality of block-shaped masks for forming a dummy pattern and wet etching the conductive layer to form pad electrodes and dummy patterns. 9. The block-shaped dummy pattern forming mask has a length in a direction along a peripheral edge of the pad electrode forming mask of 10 to 100 μm, and is provided between adjacent block-shaped dummy pattern forming masks. Distance is 5-5
9. The method for manufacturing a semiconductor device according to claim 8, wherein the thickness is 0 μm. 10. The mask for forming a dummy pattern,
The method of manufacturing a semiconductor device according to claim 7, wherein the pad electrode forming mask is formed at an interval of 5 to 50 μm from a peripheral edge of the mask. 11. The mask for forming a dummy pattern,
The width of the pad electrode forming mask in a direction orthogonal to the peripheral edge is 5 to 50 μm.
0. A method for manufacturing a semiconductor device according to any one of [1] to [10]. 12. A step of forming a conductive layer on a semiconductor substrate provided with a semiconductor chip, a step of providing a pad electrode forming mask on the conductive layer, and wet-etching the conductive layer to form a pad. A step of forming an electrode, wherein the pad electrode forming mask is provided with a plurality of block-shaped slits at a predetermined distance from a peripheral edge thereof so as to be parallel to the peripheral edge. Device manufacturing method. 13. The dimensions of the block-like slit are as follows:
13. The semiconductor device according to claim 12, wherein a length of the pad electrode forming mask in a direction along a peripheral edge is 5 to 50 [mu] m, and a width in a direction orthogonal to this direction is 5 to 50 [mu] m. Production method.