JP3117308B2 - Baseband signal receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a baseband signal receiving apparatus for performing communication with a plurality of mobile stations by time division multiplexing using a plurality of time slots. The present invention relates to a baseband signal receiving apparatus which is capable of making the rising of a baud rate clock synchronized with a system clock coincide with the eye position of an eye pattern, thereby enabling a stable operation.

[0002]

2. Description of the Related Art Conventionally, as a baseband signal receiving apparatus for performing communication with a plurality of mobile stations by time-division multiplexing using a plurality of time slots, for example, the one shown in FIG. 8 is known.

[0003] The baseband signal receiving apparatus shown in FIG.
A received signal of the I channel supplied from a demodulation circuit (not shown) via an input terminal 1 is converted into a digital signal by an A / D converter 2, and the digital signal is adjusted in timing by a timing adjustment circuit 3. The received signal of the channel is filtered by an RCROF filter (root cosine roll-off filter) 4 to suppress intersymbol interference, and this output is detected by a detection circuit 5
To supply.

Similarly, a Q-channel received signal supplied from a demodulation circuit (not shown) via an input terminal 6 is converted into an A / D signal.
The digital signal is converted into a digital signal by the converter 7, the timing of the digital signal is adjusted by the timing adjustment circuit 8, and the received signal of the Q channel whose timing has been adjusted is converted into an RCR signal.
After filtering by an OF filter (root cosine roll-off filter) 9 to suppress intersymbol interference, this output is supplied to a detection circuit 5.

[0005] The I-channel and Q-channel filter outputs supplied to the detection circuit 5 are detected, and the detection output (demodulation output) is judged by the judgment circuit 11 to be "1" or "0". The outputs of the I channel and the Q channel are combined by the I / Q combining circuit 14 to reproduce the original data, and the reproduced data is output via the output terminal.

[0006] A receiving / reproducing circuit 17 is constituted by a circuit shown by a dashed line. The receiving / reproducing apparatus 17 synchronizes with a system clock supplied via an input terminal 16 from a receiving apparatus main body of a radio base station (not shown). It is working. Also,
The detection output of the I channel and the Q channel of the detection circuit 5 is clock-recovered by the received clock recovery circuit 10, and the plurality of time slot control circuits 1 are used based on the recovered clock.
2 controls the timing adjustment circuits 13, 3 and 8. These timing adjustment circuits 13, 3 and 8 are provided with a judgment circuit 1.
In order to make the determination without error at 1, the adjustment of the A / D converters 2 and 7 is performed so that the rise of the baud rate clock synchronized with the system clock coincides with the eye position of the eye pattern which is the detection output for each time slot. This is for providing a delay before the detection circuit 5.

Here, when control is performed with a fineness of 1/16 of the symbol rate, the timing adjustment circuit 13 of the baseband receiver shown in FIG. 8 has a circuit configuration shown in FIG. That is, the timing adjustment circuit 13 shown in FIG.
Is an input terminal 32 to which a baud rate clock BRCK is supplied, and an input terminal 3 to which a sampling clock is supplied.
3. 1 by D-type flip-flop circuits d1 to d15
Five-stage shift register, input terminals 32 and AND circuits and1 to 16 and AND1 to which output data of output terminals Q of D-type flip-flop circuits d1 to d15 and corresponding output data of decoder 31, respectively, are input. And or 16 to which the output data is input.

The operation of the timing adjustment circuit 13 is as follows. When a 4-bit control signal from the multiple time slot control circuit 12 shown in FIG. A signal is output from each output terminal based on the bit control signal, and these signals are supplied to AND circuits and1 to and16, respectively.
On the other hand, the baud rate clock is supplied to the AND circuit and1 via the input terminal 32, and the output from each output terminal Q of the flip-flop circuits d1 to d15 is sequentially supplied to the AND circuits and2 to and16, respectively. The output of the AND 16 is supplied to an OR circuit 34, and the OR circuit 34 outputs the logical sum of these OR signals to an output terminal 35.
Output via. Accordingly, a signal obtained by performing a logical sum operation on a logical product output of 16 decode outputs corresponding to a 4-bit control signal from the multiple time slot control circuit 12 and a signal whose timing is sequentially changed is used as a sampling clock. To the A / D converters 2 and 7 shown in FIG. As a result, sampling is performed at the optimum position where the delay for each time slot is corrected.

Next, the timing adjusting circuits 3 and 8 of the baseband signal receiving apparatus of FIG. 8 will be described with reference to FIG. The timing adjustment circuits 3 and 8 shown in FIG. 10 include an input terminal 38 to which data is supplied, an input terminal 39 to which a sampling clock is supplied, a 15-stage shift register by D-type flip-flop circuits d1 to d15, and an input terminal 38. AND circuits and to which output data of output terminals Q of D-type flip-flop circuits d1 to d15 and corresponding output data of decoder 37 are input, respectively.
and16, and an OR circuit 34 to which output data from the AND circuits and1 to and16 are input.

The operation of the timing adjustment circuits 3 and 8 is as follows.
4 from the multiple time slot control circuit 12 shown in FIG.
A bit control signal is supplied to the decoder 37 via the input terminal 36.
, The decoder 37 outputs a signal from each output terminal based on the control signal, and supplies these signals to AND circuits and1 to and16, respectively. On the other hand, the data from the A / D converters 2 and 7 is supplied to the AND circuit and1 via the input terminal 38, and the output from each output terminal Q of the D-type flip-flop circuits d1 to d15 is sequentially output to the AND circuits and2 and and16. , And the outputs of the AND circuits and1 to and16 are supplied to the OR circuit 40. The OR circuit 40 outputs the logical sum of the AND circuits via the output terminal 41. Therefore, a signal obtained by performing a logical OR operation on the logical product of the decoded output of the decoder 37 and the data corresponding to the 4-bit control signal from the multiple time slot control circuit 12 is used as data, and this data is used as the RCROF filter 4 shown in FIG. , 9 to the detection circuit 5. As a result, the phase error of each time slot matches.

As described above, in the conventional baseband signal receiving apparatus, the timing adjustment circuits 13, 3 and 8 are controlled by the plurality of time slot control circuits 12 to adjust the timing, thereby performing filtering and detection with a common system clock. Such as digital signal processing.

However, in this method, the sampling clock of the A / D converter is changed for each time slot, two timing adjustments are required, the control is complicated, and the method has been described with reference to FIGS. 9 and 10. As described above, when the control is performed at 1/16 of the symbol rate, the timing adjustment circuits 13, 3 and 8 each have one latch.
Six is required, the number of gates is increased, and the circuit scale is increased.

If such a clock supply circuit and a timing adjustment circuit of the A / D converter are provided, digital signal processing such as filtering, detection, and judgment can be performed by the system clock. Since communication is performed using a plurality of time slots, it is difficult to control the clock supply circuit and the timing adjustment circuit of the A / D converter for each time slot.

[0014]

As described above, in the conventional apparatus, the sampling clock of the A / D converter is changed for each time slot, and two timing adjustments are required, and the control is complicated. FIG. 9
And 1/1 of the symbol rate as described in FIG.
6, the timing adjustment circuits 13, 3 and 8
Are required, 16 latches are required, the number of gates is increased, and the circuit scale is large.

If such a clock supply circuit and a timing adjustment circuit of the A / D converter are provided, digital signal processing such as filtering, detection, and determination can be performed by the system clock. For example, in a time division multiple access system, Since communication is performed using a plurality of time slots, there is a problem that it is difficult to control the clock supply circuit and the timing adjustment circuit of the A / D converter for each time slot.

Accordingly, the present invention makes it possible to make the rising of the baud rate clock synchronized with the system clock coincide with the eye position of the eye pattern, which is the detection output of each time slot, by simple control, thereby enabling stable operation. An object of the present invention is to provide a baseband signal receiving device.

[0017]

SUMMARY OF THE INVENTION The present invention detects a phase shift of a plurality of time slots from a detected output obtained by detecting a received baseband signal converted into a digital signal by suppressing intersymbol interference using a filter. In a baseband signal receiving apparatus that corrects the phase of a plurality of time slots and performs signal processing in synchronization with a system clock of the entire receiving apparatus, a filter coefficient of the filter based on the detected phase shift of the plurality of time slots. , And a filter coefficient control means for correcting the phases of the plurality of time slots.

Further, the filter coefficient control means includes storage means for storing filter coefficients of a plurality of the filters corresponding to the amount of phase correction.

[0019]

According to the present invention, a baseband signal receiving apparatus detects a phase shift of a plurality of time slots from a detection output obtained by detecting a received baseband signal converted into a digital signal by suppressing intersymbol interference by a filter, By controlling the filter coefficients of the filter based on the detected phase shifts of the plurality of time slots, correction is performed to synchronize the phases of the plurality of time slots with the system clock of the entire receiver.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a baseband signal receiving apparatus according to an embodiment of the present invention.

FIG. 1 is a block diagram showing a configuration of a baseband signal receiving apparatus according to an embodiment of the present invention. FIG.
In the figure, portions corresponding to those of the conventional device shown in FIG. 8 are denoted by the same reference numerals for convenience of explanation.

In the embodiment shown in FIG. 1, a baseband signal receiving apparatus according to the present invention is applied to, for example, a base station modem of a communication system employing a TDMA communication system. In FIG. 1, a baseband signal receiving apparatus according to the present invention includes an input terminal 1 to which an I-channel baseband signal is supplied from a demodulation circuit for orthogonally demodulating an I-channel received signal (not shown), a Q-channel received signal (not shown). Input terminals 6 and 1 to which a baseband signal of Q channel is supplied from a demodulation circuit for quadrature demodulating
A / D converters 2 and 7 for converting a baseband reception signal from the A / D converter into digital signals, and a loop cosine roll-off filter (hereinafter referred to as a "cosine roll-off filter") for suppressing intersymbol interference of signals output from A / D converters 2 and 7 18, 19, the RCROF filter 18,
A detection circuit 5 for detecting the signal from the signal 19; a determination circuit 11 for determining whether the detection output of the I and Q channels from the detection circuit 5 is “1” or “0”; An I / Q synthesizing unit 14 for synthesizing the Q channel data to obtain the original data; a reception clock reproduction circuit 10 for reproducing a clock from the output signal of the detection circuit 5; A plurality of time slot control circuits 20 for outputting a phase error as a control signal, and an RCROF coefficient control circuit 21 for supplying coefficient data of the RCROF filters 18 and 19 based on the control signals output from the plurality of time slot control circuits 20 are provided. In the rectangle of the one-dot chain line which is a circuit for performing digital processing, a receiving / reproducing circuit 22 is provided. A system clock is supplied from the entire receiving device (not shown) of the base station or the modem itself, and is synchronized with the system clock. , Each component circuit in the reception / reproduction circuit 22 operates.

Next, referring to FIG. 2, the RC shown in FIG.
The internal configuration of the ROF filters 18 and 19 will be described. In the internal configuration of the RCROF filters 18 and 19 shown in FIG. 1, received data converted into digital signals by the A / D converters 2 and 7 is input from an input terminal 70, for example, as shown in FIG. The input terminal 70 is connected to the delay circuit z1, the output terminal of the delay circuit z1 is connected to the input terminal of the delay circuit z2, and so on, similarly to the input terminal of the delay circuit z11. For input data from the input terminal 70 and the output terminal of each of the delay circuits z1 to z11, the multipliers k1 to k12 output the RCROF coefficient control circuit 2
Weighting is multiplied by the coefficient data output from 1. The signals subjected to weighted multiplication by the multipliers k1 to k12 are input to the addition circuit 71. Adder circuit 7
1 adds the signals from the multipliers k1 to k12 and outputs to the detection circuit 5 a signal in which the phase of the received data is controlled by the coefficient data.

Next, a control method of the coefficient data input to the multipliers k1 to k12 in the RCROF filters 18 and 19 will be described with reference to FIG. FIG.
Multipliers k1 to k1 in CROF filters 18 and 19
2 shows how to take the coefficient data input to 2. Here, for example, it is assumed that filtering is performed at a rate twice as high as the symbol rate using coefficients of 6 symbols and 12 taps. Here, the tap coefficients correspond to the coefficient data of the multipliers k1 to k12 shown in FIG. FIG.
, The tap coefficients ha1 to ha12 indicated by solid lines
When the output of filtering is compared with tap coefficients hb1 to hb12 indicated by broken lines calculated temporally shifted by 1/16 of the symbol rate, the tap coefficients for the same input data to the RCROF filters 18 and 19 are compared. h
The filtering output by b1 to hb12 is delayed from the filtering output of tap coefficients ha1 to ha12 by 1/16 of the symbol rate. RCROF
The phase control of the filters 18 and 19 utilizes this property. That is, the RCROF filters 18 and 19 perform waveform shaping for suppressing intersymbol interference of the output signal and control the phase of the output signal by appropriately controlling the tap coefficients. As a result, the phase of the received input signal for each time slot is controlled for each time slot, and the phase matches the system clock.

FIG. 4 shows the RCROF filters 18 and 19 depending on how the coefficient of the tap coefficient ha6 is selected.
Shows how the output changes. In FIG. 4, a solid arrow b1 indicates a direction in which the phase is delayed, and an arrow b2 indicates a direction in which the phase is advanced. With the position indicated by the coefficient data ct as the center, the position of the coefficient data m1 is delayed by 1/16 of the symbol rate, and the filter coefficient m
7 is delayed by 7/16 of the symbol rate. Further, the filter coefficient p1 advances by 1/16 of the symbol rate, and the filter coefficient p8 advances by 8/16 of the symbol rate. That is, in the symbol rate time interval, 16 types of filter coefficients m7 to m
1, ct and the phase is changed by p1 to p8. Here, the center tap coefficient ha6 has been described for convenience of description, but tap coefficients ha1 to h1 other than the tap coefficient ha6.
Similarly, a5 and tap coefficients ha7 to ha12 are shown in FIG.
Are changed to the same phase.

FIG. 5 shows how the output eye pattern of the detection circuit 5 is changed by the coefficient control of the RCROF coefficient control circuit 21. When the RCROF filters 18 and 19 use the filter coefficient ct shown in FIG. 4, the detection output IP1 shown in FIG. 5 (B) becomes 1/1 / the rising edge of the baud rate clock BRCK shown in FIG. 5 (A).
When the phase is delayed by 8 and the RCROF filters 18 and 19 use the filter coefficient p2 advanced by 2/16 of the symbol rate for all taps, FIG.
For the same input as (B), the detection output IP in FIG.
1 is the detection output IP2 shown in FIG. That is, the rising edge of the baud rate clock BRCK and the eye position of the eye pattern of the detection output IP2 match.

Next, the RCROF coefficient control circuit 21 shown in FIG. 1 will be described with reference to FIGS.

As described with reference to FIG. 5, by changing the filter coefficients of the RCROF filters 18 and 19 by the 4-bit control signal from the multiple time slot control circuit 20 of FIG. 1, the reception input signal of each time slot is changed. By changing the phase, the eye pattern of the detection output can be shifted to the rising edge of the baud rate clock synchronized with twice the system clock. Here, as shown in FIG. 6, the RCROF coefficient control circuit 21 includes, for example, a ROM 50
As shown in FIG. 7, the RCROF coefficient control circuit 21 is composed of 8 bits stored in advance according to a control signal of 4-bit address data output from the multiple time slot control circuit 20, as shown in FIG. The coefficient data of the twelve tap coefficients ha1 to ha12 are output from output terminals out1 to out12. Here, as shown in FIG. 7, the ROM 50 of the RCROF coefficient control circuit 21 stores the filter coefficient so that the detection output is delayed by 1/16 of the symbol rate every time the 4-bit address from the multiple time slot control circuit 20 increases by one. ct, m1-m7, p8-
p1 is arranged, and tap coefficients ha1 to ha12 to which the filter coefficients are added are output. That is, in the present embodiment, 16 types of filter coefficients ct, m1 to m1 are respectively assigned to the addresses “0000” to “1111”.
7, p8 to p1 are prepared correspondingly, so by changing the address and designating an appropriate filter coefficient, the phase can be arbitrarily set to 1/16 of the symbol rate as described with reference to FIG. A shifted detection output can be obtained.

Accordingly, in the RCROF filters 18 and 19 shown in FIG. 2, the input data from the A / D converters 2 and 7 are sequentially delayed, and the sequentially delayed data is supplied to the RCROF filters in the multipliers k1 to k12. Weighting is performed by multiplication with a tap coefficient added with a filter coefficient for controlling the phase from the coefficient control circuit 21, and the outputs of the multipliers k1 to k12 are added by the addition circuit 71. The added output is shown in FIG. The detected signal is supplied to the detection circuit 5.

Next, the operation of the baseband signal receiving apparatus shown in FIG. 1 will be described.

For example, the multiple time slot control circuit 20
Supplies a control signal of a 4-bit address of “0000”, the RCROF coefficient control circuit 21 converts the tap coefficients ha1 to ha12 in consideration of the filter coefficient ct into RCR
This is supplied to the OF filters 18 and 19. The RCROF filters 18 and 19 perform filtering based on tap coefficients ha1 to ha12 from the RCROF coefficient control circuit 21. The output obtained by this filtering is detected by the detection circuit 5. For example, when the detection output of the detection circuit 5 is the detection output IP1 as described with reference to FIG. 5, the reception clock recovery circuit 10 sets the detection output eye pattern to the rising edge of the baud rate clock by ８ of the symbol rate. The delay is transmitted to the multiple time slot control circuit 20. The multiple time slot control circuit 20 holds the delay phase amount at this time, and sets the address “1110” to RCROF when receiving the next same time slot.
Output to the coefficient control circuit 21. The RCROF coefficient control circuit 21 supplies the tap coefficients ha1 to ha12 in consideration of the filter coefficient p2 to the RCROF filters 18 and 19 based on the address "1110". RCROF
The filters 18 and 19 are provided with the supplied tap coefficients ha1 to ha1.
Filtering is performed based on ha12. The data obtained by this filtering is detected by the detection circuit 5, and the detection output coincides with the rise of the baud rate clock. As a result, the determination circuit 11 can make a correct determination.

As described above, in this embodiment, a plurality of filter coefficients for suppressing intersymbol interference are prepared, and the filter coefficients are changed for each time slot, and the phase correction of the detection output of each time slot is performed. I do. In this phase correction, correction is performed to match the eye position of the eye pattern, which is the detection output, and the rise of the baud rate clock synchronized with twice the system clock is matched to make a correct determination without error. .

In the above embodiment, the case where the RCROF filter is used has been described. However, the present invention is not limited to this. For example, the phase may be adjusted by using another filter such as a cosine roll-off filter or a Butterworth filter. Correction may be performed.

[0034]

As described above, according to the present invention, a plurality of filter coefficients for suppressing intersymbol interference are prepared, and the coefficients of the filter are changed for each time slot. Is performed. And
In this phase correction, correction is performed to match the eye position of the eye pattern which is the detection output, and the rise of the baud rate clock synchronized with twice the system clock is matched, so that an error-free and correct determination is performed. A / D
There is an advantage that it is possible to provide a baseband signal receiving device that operates stably with simple control without requiring complicated control for adjusting the clock and timing of the converter.

In addition, since the demodulated signal for each time slot is already synchronized with the system clock in the subsequent demultiplexing processing, it is not necessary to newly synchronize with the system clock. There is an advantage that a device with low power consumption can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a baseband signal receiving apparatus according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a filter.

FIG. 3 is an explanatory diagram of phase correction using an RCROF filter coefficient.

FIG. 4 is a diagram illustrating types and contents of filter coefficients in a filter.

FIG. 5 is a waveform chart for explaining a phase correcting operation of the baseband signal receiving apparatus of FIG. 1;

FIG. 6 is a detailed configuration block diagram of an RCROF coefficient control circuit.

FIG. 7 is a table configuration diagram showing correspondence between addresses and filter coefficients stored in an RCROF coefficient control circuit.

FIG. 8 is a configuration block diagram showing a conventional baseband signal receiving device.

FIG. 9 is a block diagram showing a main part of a conventional baseband signal receiving device.

FIG. 10 is a block diagram showing a main part of a conventional baseband signal receiving device.

[Explanation of symbols]

 2, 7 A / D converter 5 Detection circuit 10 Receive clock regeneration circuit 11 Judgment circuit 14 I / Q synthesis circuit 18, 19 RCROF filter 20 Multiple time slot control circuit 21 RCROF coefficient control circuit 22 Reception reproduction circuit

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04B 7/26 H04J 3/00 H04Q 7/00

Claims (2)

(57) [Claims] 1. A phase difference of a plurality of time slots is detected from a detection output obtained by detecting a received baseband signal converted into a digital signal by suppressing intersymbol interference by a filter, and correcting the phases of the plurality of time slots. A baseband signal receiving apparatus that performs signal processing in synchronization with a system clock of the entire receiving apparatus, wherein a filter coefficient of the filter is controlled based on a phase shift of the detected plurality of time slots, and A baseband signal receiving apparatus comprising: a filter coefficient control unit for correcting a phase of a slot. 2. The baseband signal receiving apparatus according to claim 1, wherein said filter coefficient control means includes storage means for storing filter coefficients of a plurality of said filters corresponding to a phase correction amount.