JP3115295B2 - Timing calibration device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing calibration device for performing timing calibration for aligning the timing of a test pattern supplied to each terminal pin of a device under test in a semiconductor test device.

"Prior art" In a semiconductor test apparatus, for example, Japanese Patent Application Laid-Open No. 58-32178
As shown in the publication, the test signal path to each terminal pin of the IC device under test and the signal path of each path of the strobe signal for checking the signal from the output terminal pin of the IC device under test have a delay amount there. If not given, they must be the same delay amount. A timing calibration (skew adjustment) for adjusting the delay amount by inserting a variable delay circuit into each signal path and adjusting the delay amount of each signal path has been performed as follows.

That is, as shown in FIG. 5, temporary data, for example, 0 is written into the calibration register for controlling the delay amount of the inserted variable delay circuit, and the timing is confirmed. That is, the output of the signal path and the reference phase signal are compared with each other. Are performed, and the correction data determined from the result is derived, and the step of writing the correction data to the calibration register is repeated. Each of these steps is executed by the dedicated timing calibration program, and proceeds to the next step.

For this reason, the execution speed of the program is limited, so that much time is required for the timing calibration.

According to the present invention, an edge to be calibrated is supplied to a timing confirmation circuit through a variable delay circuit, and a clock synchronized with a reference timing is supplied to a gate, which is opened by a timing calibration start signal. It is closed by the timing calibration completion flag from the timing confirmation circuit.
The output clock of the gate is counted by a counter, and the counted value is supplied to a variable delay circuit as delay amount control data.

FIG. 1 shows an embodiment of a timing calibration device according to the present invention in one communication path. The edge to be calibrated is supplied to the timing confirmation circuit 12 through the variable delay circuit 11. A variable delay circuit that counts the counter 13 as delay amount control data
Supplied to 11. A clock synchronized with the reference timing is supplied to the counter 13 through the gate 14 and counted. The gate 14 is opened by the timing calibration start signal from the terminal 15 and closed by the timing calibration completion flag from the timing confirmation circuit 12. The timing confirmation circuit 12 detects whether the edge to be calibrated supplied through the variable delay circuit 11 is calibrated at a prescribed timing, that is, performs a phase comparison with a reference phase signal, which is not shown in the drawing, A detection is made as to whether the phases match, and if calibration is confirmed, a timing calibration completion flag is issued. The counter 13 is reset by the reset signal of the terminal 16, and the data of the terminal 18 is loaded by the load signal of the terminal 17.

Reset signal A to the counter 13 as shown in FIG. 2 A is inputted at the start timing calibration, the output D ₀ of the counter-
The D ₃ and 0, also the timing calibration start signal B terminal 15 high level "1" as shown in FIG. 2 B, the gate 14 is opened. By running the test pattern for timing calibration, a clock synchronized therewith passes through the gate 14 and is counted by the counter 13 as shown in FIG. 2C. This delay control data D ₀ to D ₃ than the counter 13 change with, thus the delay amount of the variable delay circuit 11 is changed. That is, the delay amount control data from the counter 13 is
After the delay amount corresponding to the data is set in the variable delay circuit 11, the edge to be calibrated is provided to the communication path, and the output of the communication path, that is, the edge to be calibrated delayed by the variable delay circuit 11, The reference clock signal and the reference phase signal are phase-compared by a timing confirmation circuit 12, and it is confirmed whether or not the comparison is made. After that, the next clock is counted by a counter 13, and a delay amount according to the counted value is set to a variable 11, the edge to be calibrated is provided to the communication path, the phase of the edge to be calibrated delayed by the variable delay circuit 11 is compared with the reference phase signal, and so on. When a match is detected in the phase comparison, that is, when the set delay amount of the variable delay circuit 11 becomes appropriate, the timing check circuit
From 12 the timing calibration completion flag E stands before the next clock is generated as shown in FIG. 2E, the gate 14 closes, the counting operation of the counter 13 is stopped, and the count value of the counter 13 is held at that value. That is, proper delay amount control data for the variable delay circuit 11 is obtained. The timing calibration completion flag E is also sent to other components in the semiconductor test apparatus to give the whole apparatus a recognition that the timing calibration has been completed.

In the above description, the sequential search of the timing is performed in one direction. However, more accurate data can be obtained by performing the search in the up direction and the down direction and using the average value of the obtained two data as the final data. An example is shown in FIG. The edge to be calibrated is supplied to the timing confirmation circuit 12 through the variable delay circuit 11.
An up counter 21 and a down counter 22 are provided.
The data at the terminal 18 is passed through the inverted output and non-inverted output of the OR gate 23, and further through the gates 24 and 25, the up counter 21,
It is supplied to the down counter 22, and the gates 24 and 25 have the terminal 15
Is supplied after being inverted. The clock at the terminal 26 is supplied to the clock input terminals of the up counter 21 and the down counter 22 through the gates 27 and 28, respectively. The timing calibration start signal of the terminal 15 is supplied to the gates 27 and 28, the determination signal from the timing confirmation circuit 12 is supplied to the gate 27, and the inverted signal of the determination signal is supplied to the gate 28.

The count value of the up counter 21 and the count value of the down counter 22 are supplied to the variable delay circuit 11 as delay amount control data through gates 31 and 32 and further through a common OR gate 33. The gates 31 and 32 are supplied with a timing calibration start signal of the terminal 15, and the gate 31 is supplied with the judgment signal.
32 is supplied with an inverted signal of the determination signal.
The count values of the up counter 21 and the down counter 22 are averaged by the data operation circuit 34, and the average value is supplied to the OR gate 33 through the gate 35. Gate 15 has terminal 15
Of the timing calibration start signal is supplied.

Any one of the count value of the up counter 21, the count value of the down counter 22, and the average output value of the data operation circuit 34 can be extracted by the selector 36 according to the selection signal of the terminal 37.

Except during the timing calibration operation, the timing calibration start signal is at a low level "0" as shown in FIG.
24, 25 and 35 are opened, and the data at the terminal 18 is supplied to the up counter 21 and the down counter 22 through the gates 24 and 25. At this time, when the load signal of the terminal 17 is supplied to the counters 21 and 22 as shown in FIG. 4B, the up counter 21 initializes all bits “0” and the down counter 22 initializes all bits “0”. 1 "is set for each. The outputs D _{0 to} D ₂ of the up counter 21 and the outputs E _{0 to} E ₂ of the down counter 22
Are averaged by the data operation circuit 34, and the average is gated.
The data is supplied to the variable delay circuit 11 through 35 as delay amount control data.

Simultaneously with the start of the timing calibration, the timing calibration start signal becomes a high level "1" as shown in FIG.
The gates 24, 25 are closed, "1" is given to the gates 27, 28, 31, 32, and the judgment signal from the timing confirmation circuit 12 is initially at a high level "1" as shown in FIG. 4F. . So the gate
27 and 31 are open. The clock at the terminal 26 (FIG. 4C) is counted by the up counter 21 through the gate 27.
The clock is a clock synchronized with the test cycle,
The counter 21 counts up every test cycle, and the count values D _{0 to} D ₂ are passed through the gate 31 to the variable delay circuit.
11 is set as data in synchronization with the test cycle. This operation is repeated, and when an appropriate delay amount is obtained, the timing confirmation circuit 12 inverts the determination signal F.

As a result, the gates 28 and 32 are opened, and the clock of the terminal 26 is counted down by the down counter 22. The count values E _{0 to} E _{2 of the} down counter 22 are supplied to the variable delay circuit 11 through the gate 32. When appropriate data is obtained, the timing calibration completion flag generating circuit 38 sets a timing calibration completion flag as shown in FIG. 4H. Here, the timing calibration start signal becomes low level “0”, and a series of timing calibration operations is completed. The up counter 21 and the down counter 22 hold data obtained by the up-count sequential search and the down-count sequential search, respectively, and these data are averaged through the data arithmetic circuit 34, and the average value is variable. This is set in the delay circuit 11.

The timing calibration completion flag generating circuit 38 is configured, for example, as shown in FIG. That is, the high level “1” is latched by the latch 39 by the clock supplied to the up counter 21 which is the output of the gate 27, and the output of the latch 39 is supplied to the latch 41. When the determination signal F is inverted from the high level "1" to the low level "0", the latch 41 is latched by the inverted output of the OR gate 42, and the high level "1" of the latch 41 is supplied to the AND gate 43. When the judgment signal F becomes low level "0", the gate 28 is opened, and the high level "1" is latched in the latch 44 by the clock supplied to the down counter 22 which is the output of the gate 28, and the latch output is latched. Supplied to 45. Next, when the judgment signal F is inverted from the low level “0” to the high level “1”, the latch 45 is latched by the judgment signal F, and the output of the latch 45 becomes the high level “1”, which is supplied to the AND gate 43. , A timing calibration completion flag H is obtained from the AND gate 43.

[Effects of the Invention] As described above, according to the present invention, timing calibration can be performed at a high speed because timing is calibrated because of its hardware configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing the operation thereof, FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. FIG. 5 is a flowchart showing a conventional timing calibration method.

Claims (1)

(57) [Claims] 1. A timing calibration device for adjusting a signal propagation delay time of each signal path of a semiconductor test device, wherein a timing amount is provided to an edge to be calibrated based on delay amount control digital data. A variable delay circuit that supplies a clock synchronized with the reference timing, is opened by a timing calibration start signal, and is closed by a timing calibration completion flag from the timing confirmation circuit. Counting, supplying the counted value to the variable delay circuit as the delay amount control digital data for each output clock of the gate, and providing the count value when the gate is closed to the variable delay circuit, And the edge to be calibrated supplied from the variable delay circuit is A timing confirmation circuit for detecting whether or not calibration has been performed at a prescribed timing, and outputting a timing calibration completion flag when it is confirmed that the calibration has been performed as prescribed, for each of the signal paths. apparatus.