JP3113520B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to three memory cells per memory cell.
EEPRO capable of storing multi-valued data of more than value
The present invention relates to a nonvolatile semiconductor memory device such as M, EPROM, or mask ROM.

[0002]

2. Description of the Related Art As a rewritable nonvolatile semiconductor memory device, an EPROM [Erasable Programmab] is used.
le Read-Only Memory] and EEPROM [Electrically EP
ROM]. EPROM is based on FAMOS [Floating gate Avalanche injection MO using the avalanche effect.
An S] structure memory cell is generally used.
FLOTOX [Floating gate T using tunnel effect]
[unnel OXide] memory cell is common. FAM
Both the OS structure and the FLOTOX structure are MIS [Metal Ins
ulator Semiconductor] (MOS [Metal Oxide Semicond
uctor]) · FET [Field Effect Transistor]
A floating gate is provided in the gate insulator described above, and data is stored by changing the threshold voltage of the MIS • FET by injecting charges into the floating gate. However, MIS ・ F of FAMOS structure
ET discharges the charge of the floating gate by a non-electrical method such as ultraviolet irradiation, whereas FLOT
The MIS-FET having the OX structure releases charges of the floating gate by a tunnel effect caused by application of a high voltage. Also, the EEPROM is a DRAM [Dynamic Rando
m Access Memory] and NVDRAM [[Non-Vo
Latile DRAM]. Here, a read-only mask ROM or the like is also treated as a nonvolatile semiconductor memory device.

Of the above nonvolatile semiconductor memory devices, 2
The circuit of the read unit of the EEPROM that stores the value data will be described with reference to FIG.

A cell transistor 2 constituting a memory cell 1 of this EEPROM has a floating gate 2a provided in a gate insulator of a MISFET. When a high positive voltage is applied between the gate and the drain of the cell transistor 2, electrons are injected into the floating gate 2a, and the threshold voltage of the cell transistor 2 changes. Therefore, depending on whether or not electrons are injected into the floating gate 2a, 2
Value (1 bit) data can be stored. When a high negative voltage is applied between the gate and the drain, electrons in the floating gate 2a are emitted to the substrate and data is erased, so that data can be rewritten.

The cell transistor 2 has a drain connected to the bit line 3, a source connected to the source line 4,
The gate is connected to the word line 5. Note that the actual E
On the EPROM, a large number of bit lines 3 and a large number of source lines 4 and word lines 5 are provided orthogonally thereto, and a large number of memory cells 1 are arranged in a matrix at each intersection. However, here, only one memory cell 1 and one bit line 3, one source line 4, and one word line 5 are shown. The same applies to the following description.

[0006] The bit line 3 is connected to a data line 7 via a Y decoder 6 for selecting the bit line 3. The data line 7 is connected to a precharge circuit 8 for precharging the bit line 3 based on a precharge signal PS. The data line 7 is also connected to one input of the sense amplifier 9. A bit line to which a dummy cell (not shown) is connected is connected to the other input of the sense amplifier 9, and a reference voltage Vref, which is the voltage of the bit line, is input. The sense amplifier 9 is a differential amplifier that inputs the voltage of the bit line 3 via the data line 7 and the Y decoder 6 and differentially amplifies the voltage with respect to the reference voltage Vref. The sense output signal STP output from the sense amplifier 9 is output to the outside via a latch circuit, a buffer, and the like. The word line 5 is connected to an X decoder 12 for selecting the word line 5 and applying a gate voltage.

The read operation of the EEPROM having the above configuration will be described.

First, when the precharge signal PS becomes active at the start of the read operation, the precharge circuit 8
Precharges the bit line 3 to a voltage of about 1 to 2 V (a voltage of 1.4 V in FIG. 13 described below). At the time of this read operation, the source line 4 is grounded.

When the precharge is completed, FIG.
, The X decoder 12 applies a 5V gate voltage to the word line 5. Then, the cell transistor 2 of the memory cell 1 is turned on, and the charge of the bit line 3 is transferred to the source line 4.
And the voltage gradually decreases. However, as shown in the figure, when electrons are not injected into the floating gate 2a of the cell transistor 2 and the low threshold voltage Vth1 is set, the voltage of the bit line 3 drops sharply. On the other hand, when electrons are injected into the floating gate 2a and the high threshold voltage Vth2 is set, the voltage of the bit line 3 gradually decreases. A dummy cell (not shown) corresponds to the cell transistor 2
Is set to an intermediate threshold voltage between the two types of threshold voltages Vth1 and Vth2, the voltage of the bit line connected to the dummy cell, that is, the reference voltage Vref, is set at an intermediate speed. Decrease. Therefore, the sense amplifier 9
Can output a sense output signal STP corresponding to the threshold voltages Vth1 and Vth2 of the cell transistor 2 by comparing the voltage of the bit line 3 with the reference voltage Vref and performing differential amplification. Binary (1 bit) data stored in the transistor 2 can be read.

However, in the configuration of the above-mentioned EEPROM, 1
Since only binary data can be stored in the memory cells 1, there is a limit to increasing the storage capacity. Therefore, various nonvolatile semiconductor memory devices capable of storing multi-valued data of three or more values in one memory cell 1 have been conventionally proposed.

As an invention for storing such multi-value data, for example, a nonvolatile semiconductor memory device as shown in FIG. 14 has been conventionally proposed (JP-A-56-1535).
No. 82). Components having the same functions as those of the conventional example shown in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted. The proposed nonvolatile semiconductor memory device is for storing multi-valued data in a read-only ROM. Here, multi-valued data is stored in an EEPROM similar to that shown in FIG. The case will be described.

The memory cell 1 of this EEPROM is shown in FIG.
2, but by adjusting the amount of electrons injected into the floating gate 2a of the cell transistor 2, four types of threshold voltages Vth1 to Vth4
Can be set. Also, this EEPROM is
Three types of power supply voltages V1 to V3 by a power supply circuit (not shown)
The power supply switching circuit 21 sequentially switches these power supply voltages V1 to V3 based on the clock signal CLK from the oscillator 11, and supplies the power supply voltages to the X decoder 12. These three types of power supply voltages V1 to V3 are determined to be intermediate voltages of the four types of threshold voltages Vth1 to Vth4.

In this EEPROM, the reference voltage Vref to be compared with the differential amplifier by the sense amplifier 9 is a predetermined constant voltage. The sense output signal STP output from the sense amplifier 9 is input to a shift register 22 that performs a three-stage shift operation based on a clock signal CLK. The 3-bit parallel output of the shift register 22 is output to the encoder 23
, And the encoder 23 outputs quaternary data of two bits of the upper bit HB and the lower bit LB.

The read operation of the EEPROM having the above configuration will be described.

First, at the start of the read operation, the precharge circuit 8 precharges the bit line 3 as in the case of FIG. When the precharge is completed, FIG.
As shown in 5, the X decode signal XS becomes H level, the oscillator 11 starts oscillating output of the clock signal CLK, and the X decoder 12 starts driving operation of the word line 5. However, the X decoder 12 outputs the clock signal C
Since the power supply voltages V1 to V3 sequentially supplied from the power supply switching circuit 21 are applied to the word line 5 each time LK rises,
The gate voltage increases stepwise as shown.

Here, if electrons are not injected into the floating gate 2a of the cell transistor 2 and the threshold voltage Vth1 is set to the lowest value, the bit line is set when the gate voltage becomes the first power supply voltage V1. 3, the voltage of the sense output signal STP output from the sense amplifier 9 is inverted at the time t21 to become lower than the reference voltage Vref at the time t21, and becomes L level. In addition, floating gate 2
a, the second lowest threshold voltage V
When the gate voltage is set to th2, the voltage of the bit line 3 starts to decrease when the gate voltage becomes the second power supply voltage V2, and at time t22, the sense output signal STP goes to the L level, and the floating gate When a little more electrons are injected into 2a and the third threshold voltage Vth3 is set, the voltage of the bit line 3 drops when the gate voltage becomes the third power supply voltage V3. start,
At time t23, sense output signal STP goes to L level. If the maximum threshold voltage Vth4 is set by injecting the most electrons into the floating gate 2a, the voltage of the bit line does not decrease even at time t24, and the sense output signal STP is also high. Remains at the level.

Accordingly, the 3-bit parallel output at time t24 of the shift register 22, which sequentially latches and shifts the sense output signal STP at each rising of the clock signal CLK, has the L level when the threshold voltage is Vth1. Since the shift is performed three times, it becomes [L, L, L]. In the case of the threshold voltage Vth2, the L level is shifted twice, so that it becomes [L, L, H]. In the case of the threshold voltage Vth3, it becomes L. Since the level is shifted only once, the level becomes [L, H, H]. In the case of the threshold voltage Vth4, the level becomes [H, H, H] since all inputs are at the H level. If the parallel output at this time is encoded by the encoder 23 based on Table 1, the encoder 23 converts the parallel output into 2-bit data of the upper bit HB and the lower bit LB according to the threshold voltage Vth of the cell transistor 2. Four-level data is output.

[0018]

[Table 1]

As a device for storing the multi-value data, a nonvolatile semiconductor memory device as described below has also been proposed (Japanese Patent Laid-Open No. 55-80888).
issue). This non-volatile semiconductor memory device changes the IV characteristics of a MIS-FET as a cell transistor.
When a constant gate voltage is applied to the gate, this I
This utilizes the phenomenon that the drain current of the cell transistor changes due to the difference in -V characteristics, so that the speed of the voltage drop of the bit line changes. In particular,
At a specific point in time after the gate voltage is applied to the gate of the cell transistor, the voltage of the bit line is compared with, for example, three types of reference voltages.
This is to obtain quaternary data corresponding to the difference in V characteristics.

[0020]

However, FIG.
In the conventional EEPROM shown in (1), a plurality of types of power supply voltages are required to change the gate voltage stepwise,
In addition, since these power supply voltages are required to have a current supply capability for driving the word line 5, there is a problem that the power supply circuit becomes complicated, the chip area increases, and the power consumption also increases. These power supplies are connected to the word line 5
Since it takes time to apply a voltage to the gate and stabilize the gate voltage at each stage, there is a risk that the access speed may be hindered. Further, the X decoder 12
In addition, a power supply switching circuit 21 for switching and supplying these power supply voltages is also required, which causes a problem that the chip area is further increased.

In the case of a nonvolatile semiconductor memory device in which the voltage of a bit line is compared with a reference voltage at a specific point in time, it is not necessary to change the gate voltage. A reference voltage is required, and
Since each reference voltage must be a high-precision constant voltage without voltage fluctuation, there is a problem that a circuit for generating such a reference voltage increases the chip area.

The present invention has been made to solve such a problem of the prior art, and the IV characteristic or the threshold voltage of the MIS-FET can be improved by simply applying a single voltage to the word line. It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of detecting a difference and outputting multi-value data according to the difference.

[0023]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device, wherein one of a source and a drain of a MIS-FET set to one of a plurality of types of IV characteristics is used for a read operation. A memory cell connected to a bit line that is precharged at the start and whose other terminal is connected to a power supply having a voltage different from the precharge voltage during a read operation, and a comparison that compares the bit line voltage with a reference voltage A MISFET of the memory cell after the bit line is precharged.
A word line driving means for applying a predetermined gate voltage to the gate of the memory, and a read operation from a predetermined time after the start of the read operation until the comparison result of the comparison circuit changes, or after the comparison result of the comparison circuit changes. It is provided with timer means for measuring the time until a predetermined time before the end of the operation, and multi-value data output means for outputting multi-value data in accordance with the result of counting by the timer means, whereby the object can be achieved. .

According to a second aspect of the present invention, there is provided a nonvolatile semiconductor memory device which is set to one of a plurality of types of threshold voltages.
A memory in which one terminal of a source or a drain of an IS-FET is connected to a bit line to be precharged at the start of a read operation, and the other terminal is connected to a power supply having a voltage different from the precharge voltage at the time of a read operation. In a semiconductor memory device including a cell and a comparison circuit for comparing the voltage of the bit line with a reference voltage, after the bit line is precharged, the power supply voltage asymptotically changes based on a single power supply voltage The gate voltage is applied to the MIS
Word line driving means applied to the gate of the FET and a predetermined time after the start of the read operation until the comparison result of the comparison circuit changes, or before the end of the read operation after the comparison result of the comparison circuit changes And a multivalued data output means for outputting multivalued data in accordance with the time measurement result of the timer means, whereby the above object can be achieved.

According to a third aspect of the present invention, there is provided a nonvolatile semiconductor memory device which is set to one of a plurality of types of threshold voltages.
A memory in which one terminal of a source or a drain of an IS-FET is connected to a bit line to be precharged at the start of a read operation, and the other terminal is connected to a power supply having a voltage different from the precharge voltage at the time of a read operation. In a semiconductor memory device including a cell and a comparison circuit for comparing the voltage of the bit line with a reference voltage, after the bit line is precharged, the power supply voltage asymptotically changes based on a single power supply voltage The gate voltage is applied to the MIS
Word line driving means applied to the gate of the FET, quantization means for quantizing the gate voltage when the comparison result of the comparison circuit changes, and multi-valued data corresponding to the quantization result of the quantization means are output. And a multi-valued data output means for achieving the above object. The invention of claim 4 is
In the nonvolatile semiconductor memory device of the present invention, when the comparison result of the comparison circuit has not changed by a predetermined time before the end of the read operation, It is characterized in that multi-valued data different from any of the time counting result of the timer means or the multi-valued data according to the quantization result of the quantization means is output.

According to a fifth aspect of the present invention, in the nonvolatile semiconductor memory device of the present invention, the MIS-FET of the memory cell is provided.
Is provided with a floating gate, and charges are stored in the floating gate to change the threshold voltage of the FET to set one of a plurality of types of IV characteristics or a plurality of types of threshold voltages. It is characterized in that it is configured to be performed.

According to a sixth aspect of the present invention, in the nonvolatile semiconductor memory device of the present invention, the MIS-FET of the memory cell is provided.
Is characterized in that various constants are changed in a manufacturing process to set one of a plurality of types of IV characteristics or a plurality of types of threshold voltages.

[0028]

The MISFET in the memory cell of the present invention
In the case of an enhancement type N-channel FET, normally, the drain is connected to the bit line precharged to a positive voltage and the source is grounded, and the word line driving means applies a positive gate voltage to the gate. Apply. When the MIS • FET is turned on by the application of the gate voltage, the positive charge of the bit line is discharged via the source, and the precharged voltage decreases.

According to the first aspect of the present invention, the I / O
By changing the -V characteristic, multi-value data is stored in the memory cell. What is the IV characteristic of MIS • FET?
This refers to the static characteristics of the drain current ID with respect to the drain voltage VD as shown in FIG. In this IV characteristic,
In the linear region where the drain voltage VD is lower than the saturation voltage VDsat, the channel conductance gd defined by the equation (1)
Is higher, the rate of increase of the drain current ID is sharper, and the slope of the IV characteristic curve is larger.

[0030]

(Equation 1)

The value of the channel conductance gd is determined by the difference between the gate voltage VG and the threshold voltage Vth (VG-V
th) and the channel width W, and inversely proportional to the channel length. Therefore, for example, FLOTO used for EEPROM
FAMO for X-structure MIS • FET and EPROM
In the case of an S-structure MIS-FET, if the amount of charge injected into the floating gate is adjusted to change the threshold voltage Vth, the characteristics of the channel conductance gd change, and different IV characteristics are set. Can be. For example, in the case of a MIS • FET used for a mask ROM, in addition to changing the impurity concentration and the like on the surface of the substrate to change the threshold voltage Vth and changing the channel width W, the channel length, and other constants in the manufacturing process. Thus, the characteristics of the channel conductance gd can be adjusted to set different IV characteristics without changing the threshold voltage Vth. Note that the drain voltage VD is equal to the saturation voltage VDsa
Even in a saturation region higher than t, the transconductance gm similarly changes, which also affects the IV characteristics.

As shown in FIG. 17, the capacitor C charged to the voltage V is connected to the MI to which the gate voltage VG is applied.
When discharging via S-FET, this MIS-FET
Is regarded as a resistance Rm, the terminal voltage v of the capacitor C becomes
As shown in Equation 2, it decreases transiently with the passage of time t.

[0033]

(Equation 2)

Since the resistance Rm of the MIS-FET is represented by the reciprocal of the channel conductance gd, if the value of the channel conductance gd is different, the value of the resistance Rm is also changed, and as shown in FIG. In this case, the time constant RmC changes, so that the terminal voltage v
The rate of decline will also be different. In other words, if the IV characteristics of the MIS • FET of the memory cell are different, the word line driving means applies a predetermined gate voltage and this MIS • FET
, The speed at which the voltage of the pre-charged bit line decreases can be made different from each other as shown in FIG.

The comparison circuit is a circuit for comparing the voltage of the bit line with a reference voltage, and is constituted by a differential amplifier or the like used for a sense amplifier of a semiconductor memory device. However, since this comparison circuit must compare these voltages as needed over time, the voltage of the bit line at a certain time is compared with the reference voltage, and the bit line is determined in accordance with the comparison result. A flip-flop type sense amplifier that changes its own voltage cannot be used.
When the comparison circuit performs such a comparison, the comparison result changes when the voltage of the bit line becomes lower than the reference voltage.
Then, as shown in FIG. 18, the I-
If the V characteristics are different, the time when the bit line voltage becomes lower than the reference voltage also changes.

The timer means measures the time from a predetermined time after the start of the read operation to the time when the comparison result of the comparison circuit changes, and detects a difference in the IV characteristics of the MIS • FET. Also, when the time from the time when the comparison result of the comparison circuit changes to a predetermined time before the end of the read operation is measured, only the relationship of the length of the time measurement result is reversed. A difference in -V characteristics can be detected.

The multi-value data output means outputs multi-value data in an appropriate format in accordance with the result of counting by the timer means.
When the timer means is constituted by a binary counter and outputs one type of count result for each type of IV characteristic, the multi-value data output means includes two bits of the count result. The above binary values can be output as multi-value data as they are. However, when there is a possibility that the timer means may output a plurality of types of count results for one type of MIS • FET having the IV characteristic, the bit value may be appropriately converted to the minimum number of bits, and then the multi-valued data may be output. Output as In the case where the timer means shifts the comparison result of the comparison circuit by the shift register and measures the time by the shift number, the timer means encodes the result into a binary value and then outputs it as multi-valued data. The multi-valued data is normally output in a format encoded as a binary value in this way, but this does not exclude output in other formats.

As a result, according to the first aspect of the present invention, the voltage of the bit line is compared with one type of reference voltage, and the point in time at which the comparison result changes is measured, whereby the IV characteristic of the MIS • FET is improved. The difference can be detected and multi-valued data corresponding to the difference can be output. Therefore, there is no need for the word line driving means to output a plurality of types of gate voltages in a stepwise manner or to compare the bit line voltages based on a plurality of reference voltages.

According to the second aspect of the present invention, the multi-value data is stored in the memory cell by changing the threshold voltage of the MIS-FET. Further, the word line driving means applies a gate voltage that changes asymptotically to the gate of the MIS • FET. At this time, a single power supply voltage for applying a gate voltage is used instead of sequentially switching power supplies of a plurality of voltages or changing the power supply voltage itself. Even if a single power supply voltage is applied, it is necessary to charge the distributed capacitance of a wiring such as a word line. Therefore, a gate voltage which gradually changes asymptotically has been applied to the gate of the MIS • FET. However, conventionally, the current driving capability of the driver has been increased as much as possible so that the gate voltage quickly reaches a predetermined voltage. On the other hand, according to the invention of claim 2, the current driving capability of the output transistor of the driver is limited,
By inserting a resistor into the output of this driver,
The change in the gate voltage applied to the gate of the MIS • FET is made more gradual. When the gate voltage is gradually changed in this manner, the MIS-FETs become conductive at different times according to the set threshold voltage. As a result, the point in time at which the voltage of the precharged bit line drops to become lower than the reference voltage also changes.

The comparison circuit, the timer means and the multi-value data output means have the same configuration as the first aspect of the present invention. Therefore, the comparison circuit changes the output when the voltage of the bit line becomes lower than the reference voltage due to the conduction of the MIS-FET, and the timer means measures the time when the comparison result of the comparison circuit changes, thereby obtaining the MIS-FET. , The multi-level data output means outputs multi-level data in an appropriate format in accordance with the result of counting by the timer means.

As a result, also in the case of the second aspect of the present invention, the voltage of the bit line is compared with one type of reference voltage, and the time when the result of the comparison changes is measured, thereby obtaining the MIS • FET.
Of the threshold voltages can be detected and multi-valued data corresponding to the differences can be output. Therefore, there is no need for the word line driving means to output a plurality of types of gate voltages in a stepwise manner or to compare the bit line voltages based on a plurality of reference voltages.

According to a third aspect of the present invention, the timer means of the second aspect of the present invention is replaced with a quantizing means. The quantization means quantizes the gate voltage when the comparison result of the comparison circuit changes. Quantization refers to the operation of rounding the gate voltage, which is an analog value, to one of multiple digital values.
By comparing this gate voltage with a plurality of reference voltages, it can be converted into such a digital value. Here, when the gate voltage reaches the threshold voltage set for the MIS • FET, the voltage of the bit line decreases and the comparison result of the comparison circuit changes. The gate voltage is a voltage close to the set threshold voltage of the MIS • FET and having a substantially constant relationship with the threshold voltage. Therefore, the threshold voltage of the MIS • FET can be detected by quantizing the gate voltage when the comparison result changes with a plurality of reference voltages. Then, the multi-level data output means converts the quantization result into multi-level data of an appropriate format and outputs the result. When the quantization means outputs a binary digital value, the multi-value data output means only needs to output the quantization result as it is.

As a result, in the case of the third aspect of the present invention, a plurality of reference voltages are required for comparison with the gate voltage at the time of quantization, but the word line driving means outputs a single power supply voltage. By doing so, multi-valued data corresponding to the threshold voltage of the MIS • FET can be output, so that it is not necessary for the word line driving means to output a plurality of types of gate voltages stepwise.

According to a fourth aspect of the present invention, the multi-level data output means outputs different multi-level data when the comparison result of the comparison circuit does not change. Can be increased by one or the occurrence of an over program can be detected.

According to a fifth aspect of the present invention, there is provided an E-type device using a MISFET having a FLOTOX structure having a floating gate.
The present invention shows a case where the present invention is applied to an EPROM or an EPROM using a MIS • FET having a FAMOS structure, and the invention of claim 6 shows a case where the present invention is applied to a mask ROM or the like.

[0046]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 to 5 show a first embodiment of the present invention. FIG. 1 is a block diagram showing a circuit configuration of a read section of an EEPROM, and FIG. FIG. 3 is a block diagram showing the configuration of the counter, FIG. 4 is a block diagram showing the configuration of the oscillator, and FIG. 5 is a time chart showing the read operation of the EEPROM. Components having the same functions as those of the conventional example shown in FIGS. 12 and 14 are denoted by the same reference numerals.

In the present embodiment, the MIS of the FLOTOX structure is used.
The circuit of the read section of the EEPROM having the FET will be described. As shown in FIG. 1, a cell transistor 2 constituting a memory cell 1 of this EEPROM has a MIS
The floating gate 2a is provided in the gate insulator of the FET, and an appropriate amount of electrons are injected into the floating gate 2a to change the threshold voltage Vth. Can be set to either. In this case, four types of threshold voltages Vth according to the amount of the electrons, including the state in which the electrons of the floating gate 2a are completely emitted, are used.
It can be set to 1 to Vth4. The injection and emission of electrons into and from the floating gate 2a can be repeatedly performed electrically, so that data can be written and erased. The cell transistor 2 has a drain connected to the bit line 3, a source connected to the source line 4, and a gate connected to the word line 5.

The bit line 3 is connected to a data line 7 via a Y decoder 6. The Y decoder 6 has an EEP
This circuit selects one of the plurality of bit lines 3 by decoding an address input to the ROM and connects the selected bit line 3 to the data line 7. Here, it is assumed that the illustrated bit line 3 is connected to the data line 7 via the Y decoder 6. This data line 7
The precharge circuit 8 is connected. The precharge circuit 8 supplies a precharge signal PS at the start of the read operation.
Is activated, the bit line 3 is precharged to a predetermined voltage via the data line 7 and the Y decoder 6.

The data line 7 is also connected to one input of the sense amplifier 9. As shown in FIG. 2, the sense amplifier 9 includes a differential amplifier composed of P-channel FETs 9a and 9b and N-channel FETs 9c and 9d, and outputs the output of the differential amplifier to the inverter 9e from the drain of the P-channel FET 9a. Via the sense output signal STP
To be sent out. The data line 7 is connected to the gate of one P-channel FET 9a. The gate of the other P-channel FET 9b has a reference voltage V lower than the precharge voltage.
ref has been entered. Therefore, this sense amplifier 9
Is that the sense output signal STP is set to H level when the voltage of the bit line 3 via the data line 7 and the Y decoder 6 is higher than the reference voltage Vref, and when the voltage of the bit line 3 becomes lower Sense output signal STP is set to L level.
Since the differential amplifier of the sense amplifier 9 is connected to the power supply via the P-channel FET 9f and the N-channel FET 9g, it performs the sensing operation only when the sense operation signal SS becomes active during the read operation.

The sense output signal STP output from the sense amplifier 9 is sent to the counter 10. The counter 10 has a clock signal C from the oscillator 11.
LK is also input. As shown in FIG. 3, the counter 10 includes a binary 2-digit counter circuit composed of two-stage T-type flip-flops 10a and 10b, sequentially counts the rising edges of the clock signal CLK, and outputs the count result to T. The outputs of the flip-flops 10a and 10b are sent to the outside as lower bits LB and upper bits HB, respectively. However, this clock signal CLK is supplied to two three-state buffers 10c and 10d.
To the first stage T-type flip-flop 10a. Then, a sense output signal STP is input to a control input of one of the three-state buffers 10c. Therefore, when the sense output signal STP goes low, the counter 10 stops counting the clock signal CLK. Also, the upper bit HB and the lower bit LB output from the T-type flip-flops 10a and 10b are
The output of the NAND gate 10e is input to the control input of the other three-state buffer 10d. Accordingly, when the two-stage T-type flip-flops 10a and 10b finish counting and both the upper bit HB and the lower bit LB become H level,
The counting of the clock signal CLK is stopped. The control inputs of these three-state buffers 10c and 10d are L
Since a high impedance state is output in the case of the level, this output is pulled down as necessary.

The oscillator 11 has an X decode signal XS
Is entered. This oscillator 11, as shown in FIG.
A logical oscillator in which one NAND gate 11a having a long delay time and two inverters 11b and 11c are connected in a loop is provided, and the output of the logical oscillator is determined at an H / L level via another inverter 11d. After that, the clock signal CLK is sent out to the outside. Then, X decode signal XS is input to the other input of NAND gate 11a. Therefore, the oscillator 11 oscillates only when the X decode signal XS is at the H level (active), and the clock signal C
LK is output.

The NAND gate 11a and the inverter 11 which constitute the logical oscillator of the oscillator 11
b and 11c are P-channel FETs 11e to 11g and N
It is connected to a power supply via channel FETs 11h to 11j. In addition, these P-channel FETs 11e to 11e
1g and the gates of the N-channel FETs 11h to 11j are:
A diode-connected P-channel FET 111 and an N-channel FET connected in series between power supplies via a resistor 11k.
Each is connected to an 11 m gate. Therefore, when the threshold voltage Vth of the MIS FET fluctuates due to a temperature change, the oscillator 11
And the applied voltage between the source and the gate of the N-channel FET 11m changes.
11g and the N-channel FETs 11h to 11j limit the power supply current of the logical oscillator, so that the fluctuation of the oscillation frequency due to the temperature change can be suppressed.

The word line 5 is connected to the X decoder 12. The X decoder 12 is a circuit that selects one of a plurality of word lines 5 by decoding an address input to the EEPROM and applies a gate voltage VG to the selected word line 5. The X decoder 12 is also supplied with the X decode signal XS. When the X decode signal XS becomes H level, the operation of selecting the word line 5 and applying the gate voltage VG is performed.

The read operation of the EEPROM having the above configuration will be described.

First, when the precharge signal PS becomes active at the start of the read operation, the precharge circuit 8 precharges the bit line 3 selected by the Y decoder 6. The precharge refers to an operation of once raising the bit line 3 to a predetermined precharge voltage, disconnecting the power supply, setting a high impedance state, and accumulating charges in the distributed capacitance of the bit line 3. If the precharge voltage is too low, the margin of differential amplification in the sense amplifier 9 is reduced and the operation reliability is reduced. However, if the precharge voltage is too high, the floating gate 2 of the cell transistor 2 is not used.
There is a possibility that charge injection occurs in a and data is destroyed. Therefore, the precharge voltage is preferably in the range of 1.0 V or more and 1.5 V or less in this embodiment, and is set to 1.4 V here. At the time of this read operation, the source line 4 is grounded.

When the precharge of the bit line 3 is completed,
As shown in FIG. 5, at time t1, the X decode signal XS goes high.
Level, and the X decoder 12 applies a gate voltage VG of 5 V to the word line 5. Then, the cell transistor 2 of the memory cell 1 becomes conductive, the charge of the bit line 3 is discharged, and the voltage gradually decreases. However, in this cell transistor 2, the higher the threshold voltage Vth, the lower the channel conductance gd and the longer the time constant at the time of discharging the bit line 3, so that the cell transistor 2 has four different threshold voltages Vth1 to Vth4. As shown, the rate of decrease in the voltage of the bit line 3 changes. Therefore, when the cell transistor 2 is set to the lowest threshold voltage Vth1, the voltage of the bit line 3 drops rapidly and becomes lower than the reference voltage Vref at time t2. If the cell transistor 2 is set to a higher threshold voltage Vth2 to Vth4, the voltage of the bit line 3 becomes lower than the reference voltage Vref at times t3 to t5. When the voltage of the bit line 3 becomes lower than the reference voltage Vref, the sense output signal STP output from the sense amplifier 9 changes to the L level. If the reference voltage Vref is set to about half of the precharge voltage, a sufficient margin can be obtained with respect to variations in the precharge voltage. Therefore, here, the reference voltage Vref is set to 0.7 V as shown in FIG. Even if the voltage slightly exceeds 1.4 V, a normal operation can be performed.

By the way, at the time t1 when the X decode signal XS becomes H level, the oscillator 11 also starts oscillating. By this time, the T-type flip-flops 10a and 10b of the counter 10 are reset, and the upper bit HB
And the lower bit LB are both at L level. Then, originally, the pulse of the clock signal CLK rises at an intermediate point between the times t2 and t5 as shown in the figure, and the counter 10 counts. However, when the cell transistor 2 is set to the threshold voltage Vth1, the sense output signal STP changes to the L level at the time t2.
K is cut off and the counter 10 does not count once, and both the upper bit HB and the lower bit LB remain at the L level. When the cell transistor 2 is set to the threshold voltage Vth2, the sense output signal STP changes to the L level at the time t3, so that the counter 10 counts only once and only the lower bit LB is set. It becomes H level. Further, when the threshold voltage Vth3 is set, the counter 10 counts twice, and the upper bit HB becomes H level and the lower bit LB becomes L level. When the threshold voltage Vth4 is set, the counter 10 counts three times,
Both B and the lower bit LB become H level.

Therefore, after time t5, the upper bit HB and the lower bit L output from the counter 10 are output.
B has a threshold voltage Vth1 when the H level is "1".
, [0,1] for the threshold voltage Vth2, [1,0] for the threshold voltage Vth3,
Further, in the case of the threshold voltage Vth4, the two-bit value becomes [1, 1] different from each other. Then, at an appropriate timing after the time t5 or later, the 2-bit value output from the counter 10 is latched and output to the outside.
It becomes possible to read quaternary data from the memory cell 1 composed of the cell transistors 2.

The amount of electrons injected into the floating gate 2a of the cell transistor 2 further increases,
When the threshold voltage Vth exceeds, for example, a gate voltage VG of 5 V, the voltage of the bit line 3 does not become lower than the reference voltage Vref during the reading period. However, in this embodiment, the counter 10 stops counting and does not count any more when both the upper bit HB and the lower bit LB become H level. It can be handled similarly to the case where the cell transistor 2 is set to the threshold voltage Vth4. Further, by detecting whether or not sense output signal STP remains at the H level at an appropriate timing after time t5, it is possible to detect the occurrence of such an overprogram.

As a result, according to the EEPROM of this embodiment, by measuring the time until the voltage of the bit line 3 becomes lower than the reference voltage Vref, one memory cell 1 can be operated in accordance with the time measurement result. Four-value data can be read. In addition, at this time, the gate voltage V of the word line 5 is
G may be fixed at 5 V, and there is no need to generate a plurality of reference voltages.

(Second Embodiment) FIG. 6 shows a second embodiment of the present invention and is a block diagram showing a circuit configuration of a read section of a mask ROM. In addition, the first shown in FIG.
Constituent members having functions similar to those of the embodiment are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, a circuit of a read section of a mask ROM will be described. The cell transistor 2 constituting the memory cell 1 of the mask ROM is composed of a normal MIS-FET without a floating gate. However, in the cell transistor 2, the threshold voltage Vth is changed by changing the impurity concentration or the like on the substrate surface during the manufacturing process, or by changing the channel width W, the channel length, or other constants. Can be set to any one of a plurality of types of IV characteristics by adjusting the characteristics of the channel conductance gd without changing. Other configurations are the same as those of the first embodiment shown in FIG.

Also in the case of the mask ROM of the present embodiment, the time constant at the time of discharging the bit line 3 can be changed by changing the characteristics of the channel conductance gd of the cell transistor 2, as shown in FIG. The multi-value data can be read by the same operation as in the first embodiment.

(Third Embodiment) FIGS. 7 to 9 show a third embodiment of the present invention. FIG. 7 is a block diagram showing a circuit configuration of a read section of an EEPROM, and FIG. 8 is an EEPROM.
FIG. 9 is a time chart showing the read operation of the OM, and FIG. 9 is a time chart showing the charging characteristics of the word line. Note that components having the same functions as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, as in the case of the first embodiment,
EEPRO with MISFET of FLOTOX structure
The circuit of the M reading unit will be described. Therefore, the configuration of the memory cell 1 is the same as that of the first embodiment, and depends on the amount of electrons injected into the floating gate 2a.
Different threshold voltages Vth1 to Vth4 can be set. The configurations of the Y decoder 6, the precharge circuit 8, the sense amplifier 9, the counter 10, and the oscillator 11 are the same as those in the first embodiment.

The X decoder 12 applies a power supply voltage of 5 V to the word line 5 as it is, as in the first embodiment. However, the X decoder 12 is configured such that the current supply capability is lower than that of the first embodiment. In order to reduce the current supply capability, the drive capability of the output transistor of the X decoder 12 may be reduced, or the X decoder 12 may be connected to the word line 5 via a resistor. A resistor Rd and a capacitor Cd connected to the word line 5 shown in FIG. 7 respectively represent the distributed resistance and the distributed capacitance of the word line 5 as lumped constants. In this embodiment, the current supply capability of the X decoder 12 may be the same as that of the first embodiment, and the word line 5 may be formed so that the values of the resistor Rd and the capacitor Cd are increased. Further, the current supply capability of the X decoder 12 can be reduced, and the values of the resistor Rd and the capacitor Cd can be increased.

Here, it is assumed that the X decoder 12 has a sufficient current supply capability, and when the word line 5 including the resistor Rd and the capacitor Cd is charged to the voltage V, the capacitor Cd
, I.e., the voltage v of the word line 5 transiently rises with the passage of time t as shown in Expression 3.

[0069]

(Equation 3)

When the value of the resistor Rd and the value of the capacitor Cd are changed, the time constant RdCd changes, so that the speed at which the voltage v of the word line 5 rises differs as shown in FIG.
The larger the time constant RdCd is, the more slowly it rises. Therefore, by adjusting the values of the resistance Rd and the capacitor Cd of the word line 5, the gate voltage V applied to the word line 5 is adjusted.
G can be gradually increased at an arbitrary speed from 0V to 5V. Also, such a gate voltage VG
It is apparent that the control of the rising speed can be realized by adjusting the current supply capability of the X decoder 12 as described above. In order to prevent the gate voltage VG from being largely different depending on the position on the word line 5, the time constant RdCd is made as small as possible, and the current supply capability of the X decoder 12 is reduced, so that the substantial charging time constant is obtained. It is preferable to increase.

The read operation of the EEPROM having the above configuration will be described.

First, at the start of the read operation, the precharge signal PS becomes active, and the precharge circuit 8 precharges the bit line 3. When the precharge is completed, as shown in FIG. 8, the X decode signal XS goes high at time t11, and the X decoder 12 applies a 5V power supply voltage to the word line 5. However, even if the X decoder 12 applies a power supply voltage of 5V, the gate voltage VG applied to the gate of the cell transistor 2 does not immediately rise to 5V but rises slowly as shown. Then, the points at which the gate voltage VG exceeds the four types of threshold voltages Vth1 to Vth4 are also different from each other.
Bit lines 3 according to these threshold voltages Vth1 to Vth4
The timing at which the voltage of the power supply begins to decrease also changes. As a result, the voltage of the bit line 3 is changed to the reference voltage Vre of the sense amplifier 9.
The time point at which the threshold voltage becomes lower than f also changes. At the time of the threshold voltage Vth1, the time t12, and at the time of the threshold voltage Vth2, the time t1.
3. If the threshold voltage is Vth3, the sense output signal STP goes low at time t14. However, in this embodiment,
Since the threshold voltage Vth4 is set to 5 V or more, the gate voltage VG does not exceed this, and the sense output signal STP does not change to the L level. However, the first
As described with reference to FIG. 3 in the case of the embodiment, the counter 10 stops counting after counting three times, so that the threshold voltage Vth4 is set to a lower voltage,
Even if sense output signal STP is changed to L level at time t15, the result is the same. Therefore, thereafter, as in the case of the first embodiment shown in FIG. 5, the counter 10 sets the upper bit H according to the threshold voltage Vth of the cell transistor 2.
Four-level data can be output by two bits of B and the lower bit LB.

It is preferable that the rate of increase of the gate voltage VG in this embodiment is as fast as possible in order to improve the access speed. However, when the rising speed is increased, the difference at the time when the voltage of the bit line 3 becomes lower than the reference voltage Vref becomes smaller due to the difference in the threshold voltage Vth. Limited to operating speed. For example, four types of threshold voltages Vth
Is equal to the voltage up to 5V, the interval between the threshold voltages Vth is 1.25V. Since the reaction speed of the sense amplifier 9 usually requires about 5 to 10 nsec, it is necessary that the rise of the gate voltage VG does not exceed 1.25 V including the margin during the 5 to 10 nsec. Therefore, the rise rate of the gate voltage VG in this case is suitably about 0.1 V / n seconds.

As a result, according to the EEPROM of this embodiment, the gate voltage VG is gradually increased, and the time until the gate voltage VG becomes lower than the reference voltage Vref is measured. From the memory cell 1 can be read. Moreover, at this time, it is only necessary to apply a power supply voltage of 5 V to the word line 5, and it is not necessary to generate a plurality of reference voltages.

(Fourth Embodiment) FIGS. 10 and 11 show a fourth embodiment of the present invention, and FIG.
FIG. 11 is a block diagram illustrating a configuration of the voltage comparison circuit 13. Note that components having the same functions as those of the third embodiment shown in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted.

This embodiment is similar to the third embodiment,
EEP for gradually increasing the gate voltage VG of the word line 5
The ROM will be described. The EEPROM of this embodiment is
A voltage comparison circuit 13 is provided in place of the counter 10 and the oscillator 11 of the third embodiment. This voltage comparison circuit 1
3 is connected to the word line 5 together with the output of the sense amplifier 9, and receives the sense output signal STP and the gate voltage VG of the word line 5.

The voltage comparison circuit 13 has three sense amplifiers 13a to 13c as shown in FIG. The three sense amplifiers 13a to 13c are circuits that compare the input gate voltage VG with the three types of reference voltages Vr1 to Vr3 to perform differential amplification. The three types of reference voltages Vr1 to Vr3 are reference voltages set to be intermediate voltages of the four types of threshold voltages Vth1 to Vth4. Each of the sense amplifiers 13a to 13c outputs an H level when the gate voltage VG is higher than the reference voltages Vr1 to Vr3, and outputs an L level when the gate voltage VG is low. The three types of reference voltages Vr1 to Vr3 are:
The voltage must be a high-precision constant voltage with no voltage fluctuation. However, since it is only differentially amplified by the sense amplifiers 13a to 13c, the current supply capability is hardly necessary.

The outputs of the sense amplifiers 13a to 13c are input to a circuit of two NAND gates 13d and 13e and two inverters 13f and 13g, and are encoded based on Table 2 and are output to a 2-bit latch circuit 13h. Is entered.

[0079]

[Table 2]

The latch circuit 13h receives the sense output signal ST
P is input via an AND gate 13i, and the encoding result is latched at the time of falling of the sense output signal STP. Then, the 2-bit output of the latch circuit 13h is output as the upper bit HB and the lower bit LB, respectively, and this becomes the 4-value data read from the memory cell 1. The other input of the AND gate 13i is supplied with a timeout signal TO which falls to the L level at an appropriate time before the end of the read operation. Therefore, when the sense output signal STP does not change to the L level, the time-out signal TO
The change to the level ensures that the encoding result is latched by the latch circuit 13h.

The read operation of the EEPROM having the above configuration will be described with reference to FIG. 8 showing the third embodiment.

When precharging of bit line 3 is completed and X decoder 12 applies a power supply voltage of 5 V to word line 5 at time t11, gate voltage VG of word line 5 rises slowly as shown. . Then, the cell transistor 2
At times t12 to t12 depending on the threshold voltages Vth1 to Vth4 of
At 14 the sense output signal STP goes low. And
When this sense output signal STP becomes L level,
Since the result of comparison of the gate voltage VG by the voltage comparison circuit 13 is encoded and latched, the actual voltage of the word line 5 near the gate voltage VG exceeding the threshold voltages Vth1 to Vth4 is monitored and quaternary data Can be output. However, in the case of the threshold voltage Vth4, the sense output signal STP does not actually change to the L level. However, in this case as well, since the latch is performed by the timeout signal TO, no problem occurs. If the sense output signal STP is still at the H level when the time-out signal TO changes to the L level, the sense output signal STP is separately detected and another data is output, so that over-programming is performed. Occurrence can be detected.

As a result, according to the EEPROM of this embodiment, the gate voltage VG is gradually increased to detect the gate voltage VG when the voltage of the bit line 3 becomes lower than the reference voltage Vref. Four-level data can be read from one memory cell 1. At this time, three types of reference voltages Vr1 to Vr3 are required, but it is only necessary to apply a power supply voltage of 5V to the word line 5.

In each of the above embodiments, a nonvolatile semiconductor memory device for storing quaternary data has been described. However, the present invention is not limited to this. The same can be applied to a semiconductor memory device.

[0085]

As is apparent from the above description, the nonvolatile semiconductor memory device of the present invention requires only a single voltage to be applied to a word line to reduce the IV characteristic or threshold voltage of a MIS-FET. Since the difference can be detected and multi-valued data can be output in accordance with the difference, a power supply of a plurality of types of voltages for driving the word line and a circuit for switching the power supply voltage are not required, thereby increasing the chip area. And an increase in power consumption can be suppressed. Except for the invention of claim 3, since it is only necessary to compare the voltage of the bit line with one type of reference voltage, a circuit for generating a plurality of types of reference voltages becomes unnecessary, which also reduces the chip area. The increase can be suppressed.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of the present invention, in which EE
FIG. 3 is a block diagram illustrating a circuit configuration of a reading unit of the PROM.

FIG. 2 is a block diagram illustrating a configuration of a sense amplifier according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a counter according to the first embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of an oscillator according to a first embodiment of the present invention.

FIG. 5 is a view showing a first embodiment of the present invention, in which EE is used.
6 is a time chart illustrating a read operation of a PROM.

FIG. 6 is a block diagram showing a second embodiment of the present invention and showing a circuit configuration of a read section of a mask ROM.

FIG. 7 shows a third embodiment of the present invention, in which EE
FIG. 3 is a block diagram illustrating a circuit configuration of a reading unit of the PROM.

FIG. 8 shows a third embodiment of the present invention, in which EE
6 is a time chart illustrating a read operation of a PROM.

FIG. 9 is a time chart showing a third embodiment of the present invention and showing charging characteristics of a word line.

FIG. 10 shows a fourth embodiment of the present invention,
FIG. 3 is a block diagram illustrating a circuit configuration of a reading unit of the EPROM.

FIG. 11 is a block diagram illustrating a configuration of a voltage comparison circuit 13 according to a fourth embodiment of the present invention.

FIG. 12 shows a first conventional example, and is a block diagram illustrating a circuit configuration of a read unit of an EEPROM that stores binary data.

FIG. 13 shows a first conventional example, and shows an EEPR.
6 is a time chart illustrating an OM read operation.

FIG. 14 is a block diagram showing a second conventional example and showing a circuit configuration of a read section of an EEPROM for storing multi-value data.

FIG. 15 shows a second conventional example, in which EEPR is used.
6 is a time chart illustrating an OM read operation.

FIG. 16 is for explanation of the present invention, and is a MIS.
FIG. 5 is a diagram showing IV characteristics of an FET.

FIG. 17 is for explanation of the present invention,
FIG. 3 is a circuit diagram illustrating a discharge circuit of an FET.

FIG. 18 is for explanation of the present invention,
6 is a time chart showing discharge characteristics of the FET.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell 2 Cell transistor 2a Floating gate 3 Bit line 8 Precharge circuit 9 Sense amplifier 10 Counter 11 Oscillator 12 X decoder 13 Voltage comparison circuit

Claims (6)

(57) [Claims] 1. One of a source and a drain of a MIS • FET set to one of a plurality of types of IV characteristics is connected to a bit line to be precharged at the start of a read operation, and the other is connected to a bit line. A semiconductor memory device comprising: a memory cell having a terminal connected to a power supply having a voltage different from a precharge voltage during a read operation; and a comparison circuit for comparing the voltage of the bit line with a reference voltage. Later, the MIS
A word line driving means for applying a predetermined gate voltage to the gate of the FET; a predetermined time after the start of the read operation until the comparison result of the comparison circuit changes, or after the comparison result of the comparison circuit changes A nonvolatile semiconductor memory device comprising: timer means for measuring a time until a predetermined time before the end of a read operation; and multi-value data output means for outputting multi-value data in accordance with a result of the timer. 2. One of a source and a drain of a MIS • FET set to one of a plurality of types of threshold voltages is connected to a bit line to be precharged at the start of a read operation, and the other is connected to the other. A semiconductor memory device comprising: a memory cell having a terminal connected to a power supply having a voltage different from a precharge voltage during a read operation; and a comparison circuit for comparing the voltage of the bit line with a reference voltage. Later, word line driving means for applying a gate voltage asymptotically changing to this power supply voltage based on a single power supply voltage to the gate of the MIS • FET of the memory cell; Timer for measuring the time until the comparison result of the comparison circuit changes, or until the predetermined time before the end of the read operation after the comparison result of the comparison circuit changes Stage and the nonvolatile semiconductor memory device including a multi-value data output means for outputting multi-valued data corresponding to the time measurement result of the timer means. 3. A source or drain terminal of a MIS-FET set to one of a plurality of types of threshold voltages is connected to a bit line to be precharged at the start of a read operation, and the other terminal is connected to a bit line. A semiconductor memory device comprising: a memory cell having a terminal connected to a power supply having a voltage different from a precharge voltage during a read operation; and a comparison circuit for comparing a voltage of the bit line with a reference voltage. A word line driving means for applying a gate voltage asymptotically changing to the power supply voltage to the gate of the MIS-FET of the memory cell based on a single power supply voltage; A non-volatile semiconductor device comprising: a quantizing means for quantizing a gate voltage of the multi-valued data; and a multi-valued data output means for outputting multi-valued data according to a quantization result of the quantizing means. Conductor storage. 4. The method according to claim 1, wherein the multi-valued data output means measures the time of the timer means when the comparison result of the comparison circuit has not changed by a predetermined time before the end of the read operation. 4. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device outputs multi-valued data different from a result or multi-valued data according to the quantization result of the quantization means. 5. The MIS-FET of the memory cell includes a floating gate, and charges are stored in the floating gate to change a threshold voltage of the FET, thereby providing a plurality of types of IV characteristics or 5. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is set to one of a plurality of types of threshold voltages. 6. A plurality of types of I / Os by changing various constants in the MIS-FET of the memory cell in a manufacturing process.
5. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is set to one of a -V characteristic and a plurality of types of threshold voltages.