JP3108542B2 - Phase adjustment circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase adjusting circuit for adjusting the phase of a clock for data used in a repeater in a transmission system.

[0002]

2. Description of the Related Art Conventionally, a phase adjustment circuit physically adjusts a signal propagation delay caused by a delay line or a delay element. However, since the adjustment is difficult and the adjustment man-hour is large, it is input to an identification circuit. Data and clock phase difference
Various circuits have been studied which automatically adjust the phase of a clock for data to an optimum state by electrically controlling the amount of delay of the clock.

FIG. 2 is a circuit diagram showing an example of a conventional phase adjusting circuit of this type (for example, Proceedings of the 1988 IEICE Spring National Convention (B-1)). -404). In FIG. 2, input data 30 input from a data input unit 21 is branched by a buffer circuit 27a, one of which is input to an EXOR circuit 26a, and the other is input to a latch circuit 25a. Clock input unit 22
Is input to the variable phase circuit 24, the normal phase clock 31 is input to the latch circuit 25a, and the negative phase clock 32 is input to the latch circuit 25b. The output 33 of the latch circuit 25a is branched by the buffer circuit 27b.
One is an EXOR circuit 26a and the other is a buffer circuit 27c.
Through the EXOR circuit 26b and the latch circuit 25b. The output 34 of the latch circuit 25b is the buffer circuit 2
The data is output to the EXOR circuit 26b and the data output unit 23 via 7d. The output 35 of the EXOR circuit 26a is input to the operational amplifier 29 via the integration circuit 28a, and the output 36 of the EXOR circuit 26b is input to the operational amplifier 29 via the integration circuit 28b. The output of the operational amplifier 29 is input to the phase variable circuit 24, and changes the phases of the output clocks 31, 32.

FIG. 3 is a signal waveform diagram showing signal waveforms at various parts in FIG. Assuming that the phases of the clocks 31 and 32 output from the phase variable circuit 24 lag behind the input data 30 input from the data input unit 21 by φ _D , the output 35 of the EXOR circuit 26a outputs the input data 3
Varying the pulse width to be output at the timing of 0 is equal waveform to the phase difference phi _D. The output 36 of the EXOR circuit 26b has a waveform in which the pulse width output at a timing delayed by the phase difference φ _D from the timing at which the input data 30 changes is equal to the rising phase difference between the clocks 31 and 32.

[0005] Therefore, as shown in FIG.
, A voltage 38 corresponding to the change probability of the input data 30 and the phase difference φ _D between the input data 30 and the rising edge of the clock 31 appears at the output of the integration circuit 28a. A voltage 37 appears. The operational amplifier 29 applies a voltage proportional to the difference between the output voltage 37 of the integration circuit 28a and the output voltage 38 of the integration circuit 28b to the phase variable circuit 24 to form a feedback loop. The phase is automatically controlled so that the difference becomes zero.

[0006]

However, in the phase adjusting circuit having the above structure, the phase difference between the input data and the input clock input to the latch circuit as the identification circuit is automatically adjusted based on the pulse width of the clock. For this reason, the standard for automatic adjustment cannot be arbitrarily set, and it is difficult to match the optimum phase relationship.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a phase adjustment circuit capable of adjusting the phase relationship between input data input to an identification circuit and an input clock to an optimum state. The purpose is to do.

[0008]

In order to achieve the above object, the present invention provides a phase variable circuit for changing the phase of an input clock based on a control signal, and synchronizing input data with an output clock of the phase variable circuit. A discriminating circuit for outputting, a first EXOR circuit for taking an exclusive OR of an output of the discriminating circuit and the input data, a first integrating circuit for integrating an output of the first EXOR circuit, and a delay time A variable delay circuit variably delaying the input data or the output of the identification circuit, and a second exclusive OR of an output of the variable delay circuit and the input data or the output of the identification circuit.
EXOR circuit, a second integration circuit for integrating an output of the second EXOR circuit, and a difference between an output of the first integration circuit and an output of the second integration circuit is output as the control signal. It has an operational amplifier.

[0009]

According to the present invention, a signal having a pulse width corresponding to the phase difference between input data and an input clock in the identification circuit is generated at the timing of change of the input data by using the identification circuit and the first EXOR circuit, and is varied. Delay circuit and second EXO
Using the R circuit, a signal having a pulse width corresponding to the delay time of the variable delay circuit is generated at the timing of the change of the input data. The difference between the DC components of the two signals is obtained by the first integration circuit, the second integration circuit, and the operational amplifier and input to the phase variable circuit, and the phase of the input clock supplied to the identification circuit is calculated by the phase difference. Is automatically controlled to match the delay time. The phase of the input clock with respect to the input data in the identification circuit is adjusted to an optimum state by adjusting the delay time.

[0010]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In FIG. 1, a data input section 1 is connected to an input of a buffer circuit 12a,
One of the outputs is connected to the input of the buffer circuit 12b, and the other is connected to the input of the buffer circuit 12c.
One of the two outputs of the buffer circuit 12c is connected to the input of the EXOR circuit 9b, and the other is connected to the input (D) of the identification circuit 5 composed of a D-type flip-flop or the like. The output (Q) of the identification circuit 5 is input to the input of the buffer circuit 12d.
One of the two outputs of the buffer circuit 12d is connected to the data output unit 3, the other is connected to the EXOR circuit 9b, and the output of the EXOR circuit 9b is connected to the input of the integration circuit 10a.

One of the two outputs of the buffer circuit 12b is input to the EXOR circuit 9a, the other is input to the variable delay circuit 8, and the output of the variable delay circuit 8 is the EXOR circuit 9a.
And the output of the EXOR circuit 9a is connected to the input of the integrating circuit 10b. Integrating circuits 10a and 10
The output of b is connected to the input of the operational amplifier 11, and the output of the operational amplifier 11 is connected to the phase control terminal of the phase variable circuit 6, respectively. The clock input unit 2 includes a phase variable circuit 6
, The output of the phase variable circuit 6 is connected to the clock input section (CLK) and the clock output section 4 of the identification circuit 5.

Next, the operation of this embodiment will be described with reference to signal waveforms at various parts shown in FIG.

Consider a case where input data 13 having a waveform as shown in FIG. The input data 13 is input to the buffer circuit 12b and branched, one of which is input as it is to the EXOR circuit 9a, and the other is provided with the delay time T by the variable delay circuit 8 and then EX.
The signal is input to the OR circuit 9a, and an exclusive OR is obtained at both inputs. Thereby, as shown in FIG. 5, the output of the EXOR circuit 9a changes at the timing when the input data 13 changes.
An output 14 having a pulse width equal to the delay time T, that is, a differential waveform of the input data 13 is obtained.

On the other hand, if the input clock input to the clock input unit 2 is input to the phase variable circuit 6 and given a phase delay of φ _D , the clock input unit (CLK) of the identification circuit 5 A clock 15 having a waveform as shown is input. Therefore, the output (Q) of the identification circuit 5 is shown in FIG.
As shown in the figure, data 16 having a waveform whose phase is delayed by φ _D from the input data 13 is output. This data 16 is EX
The data is input to the OR circuit 9b, and an exclusive OR with the input data 13 is obtained. Thus, the output of the EXOR circuit 9b, as shown in FIG. 5, at the timing of changing the input data 13, the output 17 of the waveform having a pulse width corresponding to a phase difference phi _D is obtained.

The output 14 of the EXOR circuit 9a is output to the integration circuit 1
When the input value is input to 0b and its integral value is calculated, the output of the integrating circuit 10b outputs an output 19 which is a DC voltage of a level corresponding to the probability of change of the input data 13 and the delay time T as shown in FIG. Is obtained. Further, when the output 17 of the EXOR circuit 9b is input to the integration circuit 10a and its integrated value is obtained,
The output of the integrating circuit 10a, as shown by A in FIG. 6, the input output 18 is the probability and the level of the DC voltage corresponding to the phase difference phi _D of varying data 13 is obtained, the output 18 is phase difference phi _It changes linearly with the change of _D.

The outputs 18 and 19 are connected to the operational amplifier 11
The control signal 20 having a value corresponding to the phase difference φ _{D using the} output 19 as a reference signal is obtained at the output. The control signal 20 is input to the phase control terminal of the phase variable circuit 6, and the phase variable circuit 6 forming the feedback loop makes the output 18 and the output 19 equal based on the control signal 20, that is, φ _D = T and the phase of the input clock is controlled and output to the identification circuit 5. Thus, the phase difference phi _D of the input and the input data that is input to the identification circuit 5 clock is maintained to automatically equal to the delay time T of the variable delay circuit 8 without adjusting from the outside, it is stabilized Will be.

Here, the delay time T of the variable delay circuit 8 is represented by Δ
When T is changed, the output 19 output from the integration circuit 10b changes from the level indicated by B to the level indicated by C as shown in FIG. 6, and the control signal 20 changes accordingly. The phase variable circuit 6 determines φ _D −Δφ in accordance with the control signal 20.
Since the phase of the input clock is controlled so that = T−ΔT, the phase difference between the input data in the identification circuit 5 and the clock 15 is set to T−ΔT. That is, by adjusting the delay time T of the variable delay circuit 8, the phase difference between the input data and the clock 15 in the identification circuit 5 can be adjusted so as to be in an optimal state for identifying the input data.

FIG. 7 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, as shown in FIG. 7, a band-pass filter 40 for extracting a clock component from the output of the EXOR circuit 9a and the extracted clock component are converted into a clock waveform by the phase adjustment circuit shown in FIG. And a limiter amplifier 41 that supplies the clock signal to the phase variable circuit 6.
Unlike the embodiment shown in FIG. 1, the present invention can be applied to a case where a clock is not supplied from the outside and it is necessary to extract a clock from input data.

NRZ (Non Return)
When a clock is generated from input data having no clock component such as a “to Zero” code, for example, a so-called differential circuit including a buffer circuit 12b, a delay circuit 8, and an EXOR circuit 9a as shown in FIG. Must be used to extract the clock generation. In this embodiment, as shown in FIG. 7, since the above-mentioned differentiating circuit is already provided in the phase difference detecting circuit 7, it is configured to be shared with a differentiating circuit for clock extraction. As a result, a clock can be generated from input data only by adding the clock extraction circuit 39, and power consumption can be reduced by sharing.

FIG. 8 is a circuit diagram showing a third embodiment of the present invention.

In this embodiment, the buffer circuit 12a and the data output section 3 in the phase adjusting circuit shown in FIG. 1 are eliminated, and the output of the buffer circuit 12d is connected to the input of the buffer circuit 12b. That is, the present embodiment is different from the phase adjusting circuit shown in FIG. 1 in that the output of the buffer circuit 12d is input to the buffer circuit 12b instead of the input data 13, and the other points are the same. Therefore, the operation of this embodiment is almost the same as that of FIG.

FIG. 9 shows signal waveforms at various parts in FIG. The output 19 of the integrating circuit 10b shown in FIG.
Relationship between the phase difference phi _D of the input data and the clock 20 in the identification circuit 5 and is the same as that shown in FIG.

[0025]

As described above in detail, according to the present invention, the phase variable circuit uses the phase variable circuit so that the phase difference between the input data and the input clock in the identification circuit matches the delay time set by the variable delay circuit. Since the phase of the input clock is automatically controlled, the phase relationship between the input data and the input clock in the identification circuit can be adjusted to an optimum state by adjusting the delay time.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional phase adjustment circuit.

FIG. 3 is a signal waveform diagram showing signal waveforms at various parts in FIG. 2;

4 is a diagram showing an output 38 of an integrating circuit 28b and a phase difference φ _{D of} FIG. 2;
FIG.

FIG. 5 is a signal waveform diagram showing signal waveforms of respective units in FIG. 1;

FIG. 6 shows an output 19 of the integrating circuit 10b of FIG. 1 and a phase difference φ _D.
FIG.

FIG. 7 is a circuit diagram showing a second embodiment of the present invention.

FIG. 8 is a circuit diagram showing a third embodiment of the present invention.

FIG. 9 is a signal waveform diagram showing signal waveforms at various parts in FIG.

[Explanation of symbols]

 Reference Signs List 5 discrimination circuit 6 phase variable circuit 7 phase difference detection circuit 8 variable delay circuit 9a, 9b EXOR circuit 10a, 10b integration circuit 11 operational amplifier 12a to 12d buffer circuit 39 clock extraction circuit

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiro Akiyama 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-58-95447 (JP, A) (58) ) Surveyed field (Int.Cl. ⁷ , DB name) H03K 5/04 H04L 7/02 H04L 25/02

Claims (3)

(57) [Claims] 1. A phase variable circuit that changes the phase of an input clock based on a control signal, an identification circuit that outputs input data in synchronization with an output clock of the phase variable circuit, and an output of the identification circuit and the input. A first EXOR circuit that takes an exclusive OR of data, a first integration circuit that integrates an output of the first EXOR circuit, a variable delay circuit that has a variable delay time and delays the input data, A second EXOR circuit that takes an exclusive OR of an output of the variable delay circuit and the input data; a second integration circuit that integrates an output of the second EXOR circuit; and an output of the first integration circuit And an operational amplifier for outputting a difference between the control signal and the output of the second integration circuit as the control signal. 2. A phase variable circuit that changes a phase of an input clock based on a control signal, an identification circuit that outputs input data in synchronization with an output clock of the phase variable circuit, and an output of the identification circuit and the input. A first EXOR circuit for obtaining an exclusive OR of data; a first integration circuit for integrating an output of the first EXOR circuit; a variable delay circuit having a variable delay time and delaying an output of the identification circuit A second EXOR circuit that takes an exclusive OR of an output of the variable delay circuit and an output of the identification circuit; a second integration circuit that integrates an output of the second EXOR circuit; A phase adjustment circuit comprising: an operational amplifier that outputs a difference between an output of an integration circuit and an output of the second integration circuit as the control signal. 3. A phase variable circuit for changing a phase of a clock based on a control signal, an identification circuit for outputting input data in synchronization with an output clock of the phase variable circuit, an output of the identification circuit and the input data A first EXOR circuit that takes an exclusive OR of a first EXOR circuit, a first integration circuit that integrates an output of the first EXOR circuit, a variable delay circuit that has a variable delay time and delays the input data, A second EXOR circuit that takes an exclusive OR of an output of the variable delay circuit and the input data, a second integration circuit that integrates an output of the second EXOR circuit, and an output of the first integration circuit. An operational amplifier that outputs a difference from an output of the second integration circuit as the control signal; and a clock extraction circuit that generates a clock from an output of the second EXOR circuit and outputs the clock to the variable phase circuit. Phase adjusting circuit and having a road.